Prosecution Insights
Last updated: October 02, 2026
Application No. 17/932,735

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §103
Filed
Sep 16, 2022
Priority
Oct 18, 2021 — CN 202111210387.X
Examiner
KOLB, THADDEUS J
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Innolux Corporation
OA Round
3 (Non-Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
28 granted / 33 resolved
+16.8% vs TC avg
Strong +22% interview lift
Without
With
+21.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
31 currently pending
Career history
71
Total Applications
across all art units

Statute-Specific Performance

§103
62.2%
+22.2% vs TC avg
§102
22.3%
-17.7% vs TC avg
§112
15.6%
-24.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 33 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment/Argument Applicant’s arguments, see remarks, filed 05/15/2026, with respect to the rejection of claim 17 under 35 U.S.C. 112(b) have been fully considered and are persuasive. The rejection of claim 17 has been withdrawn. Applicant's arguments filed 05/15/2026 with respect to the rejection of claims 13-20 under 35 U.S.C. 102 and 103 have been fully considered but they are not persuasive. The prior art combination of record for the subject matter of canceled claim 15 does teach the limitation of “a Young's modulus ranging from 1 MPa to 100 MPa” because optically clear silicone falls within this range and provides the benefit of absorbing stress caused by differential thermal expansion and contraction between a chip and a substrate (¶0030 of Vadhavkar). Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 13-14 and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US-20220271018-A1 – hereinafter Chen) in view of Vadhavkar (US-20200098965-A1). Regarding claim 13, Chen teaches an electronic device (Fig.16; ¶0075), comprising: a substrate (Fig.16 16; ¶0075); a patterned metal layer (Fig.16 122; ¶0045) on the substrate (16); a metal layer (Fig.16 192) on the patterned metal layer (122); an electronic component (Fig.16 19; ¶0075) comprising a plurality of bonding pads (Fig.16 191; ¶0069) on the metal layer (122); and a glue (Fig.16 20; ¶0075) between the bonding pads (191). Chen does not teach wherein the glue has a Young's modulus ranging from 1 MPa to 100 MPa to absorb stress generated from a coefficient of thermal expansion (CTE) mismatch between the electronic component and the substrate. Vadhavkar teaches an underfill material that is optically clear silicone (¶0030 of Vadhavkar) disposed between a chip (Fig.1 102; ¶0030 of Vadhavkar) and a substrate (Fig.1 104; ¶0030 of Vadhavkar). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the silicone based material of Vadhavkar (¶0030 of Vadhavkar) as the underfill material for the underfill of Chen (20 of Chen) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of absorbing stress caused by differential thermal expansion and contraction between a chip and a substrate (¶0030 of Vadhavkar). Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen. Regarding claim 14, Chen teaches the electronic device as claimed in claim 13. Chen does not teach wherein the glue has a thickness ranging from 50 microns to 600 microns. However, it would have been obvious to form the thickness within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)). Regarding claim 16, Chen teaches the electronic device as claimed in claim 13. Chen does not teach wherein the glue comprises white glue, optical glue or waterproof glue. Vadhavkar teaches an underfill material that is optically clear silicone (¶0030 of Vadhavkar) disposed between a chip (Fig.1 102; ¶0030 of Vadhavkar) and a substrate (Fig.1 104; ¶0030 of Vadhavkar). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the silicone based material of Vadhavkar (¶0030 of Vadhavkar) as the underfill material for the underfill of Chen (20 of Chen) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of absorbing stress caused by differential thermal expansion and contraction between a chip and a substrate (¶0030 of Vadhavkar). Regarding claim 17, Chen teaches the electronic device as claimed in claim 13, wherein the metal layer (192) is between the substrate (16) and the bonding pads (191) of the electronic component (19). Regarding claim 18, Chen teaches the electronic device as claimed in claim 17, further comprising a solder (Fig.16 193; ¶0069) on the metal layer (122), wherein the bonding pads (191) of the electronic component (19) are on the solder (193). Regarding claim 19, Chen teaches the electronic device as claimed in claim 13, wherein the glue (16) surrounds the bonding pads (191) from a top view of the electronic device (¶0082). Regarding claim 20, Chen teaches the electronic device as claimed in claim 13, wherein the glue (16) surrounds the electronic component (19) from a top view of the electronic device (¶0014). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /T.J.K./ Examiner, Art Unit 2817 /ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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Prosecution Timeline

Sep 16, 2022
Application Filed
Aug 22, 2025
Non-Final Rejection mailed — §103
Nov 20, 2025
Response Filed
Jan 21, 2026
Final Rejection (signed) — §103
Feb 23, 2026
Final Rejection mailed — §103
May 15, 2026
Request for Continued Examination
May 19, 2026
Response after Non-Final Action
Sep 08, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751304
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4y 3m to grant Granted Sep 29, 2026
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INTEGRATION STRUCTURE FOR CONNECTING A PLURALITY OF SEMICONDUCTOR DEVICES, ASSOCIATED METHODS, ASSEMBLY AND SYSTEM
3y 9m to grant Granted Sep 22, 2026
Patent 12733310
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4y 1m to grant Granted Sep 08, 2026
Patent 12720930
DISPLAY DEVICE
3y 11m to grant Granted Aug 25, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+21.7%)
3y 8m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 33 resolved cases by this examiner. Grant probability derived from career allowance rate.

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