DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 19, 2025 has been entered.
Response to Amendment
This Office Action is in response to Applicant's amendments filed November 4, 2025. Claims 1-2, and 5-6 have been amended. Claim 24 has been added. No claims have been canceled. Currently, claims 1-24 are pending.
Applicant’s Amendment to claim 2 overcomes the claim objection outlined in the previous Office Action. The claim objection of claim 2 is withdrawn.
Response to Arguments
Applicant’s arguments with respect to claims 1-2, and 5-6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the second semiconductor region is formed over an entire surface of the third semiconductor region but the portion overlapping the first semiconductor region in the planar view” of claim 24 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 2 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Matsumoto (US 20220163674 A1).
Regarding claim 2, Fig. 1 of Matsumoto discloses a photoelectric conversion apparatus (Fig. 1, sensor chip 1, ¶ [0040]) comprising:
a plurality of avalanche diodes (Fig. 1, SPAD 2, ¶ [0041]) arranged in a semiconductor layer (Fig. 1, semiconductor substrate 10, ¶ [0042]) having a first surface (Fig. 1, light entering surface 10A, ¶ [0042]) and a second surface (Fig. 1, surface 10C, ¶ [0042]) facing the first surface (10A),
wherein the avalanche diode (2) includes:
a first semiconductor region (Fig. 1, cathode 16, ¶ [0044]) of a first conductivity type (Fig. 1, “The cathode 16 is an n-type semiconductor region”, ¶ [0047]), which is arranged at a first depth,
a second semiconductor region (Fig. 1, p-type semiconductor region 14¸¶ [0044]) of a second conductivity type (Fig. 1, “The p-type semiconductor region 14 is a p-type semiconductor region”, ¶ [0046]), which is arranged at a second depth deeper than the first depth with respect to the second surface (10C),
a third semiconductor region (Fig. 1, n-type semiconductor region 15, ¶ [0044]) provided adjacent an end of the first semiconductor region (16) in a planar view from the second surface (10C),
a first wiring portion (Fig. 1, first wiring line 25B, ¶ [0054]) electrically connected to the first semiconductor region (16) via a first contact plug (Fig. 1, contact layer 25A, ¶ [0054]) (Fig. 1, “The contact layer 25A is provided in such a manner as to… couple the anode 13 or the cathode 16 to the first wiring line 25B”, ¶ [0054]), and
a second wiring portion (25B) electrically connected to the second semiconductor region (14) via a second contact plug (25A) (Fig. 1, “The contact layer 25A is provided in such a manner as to… couple the anode 13 or the cathode 16 to the first wiring line 25B”, ¶ [0054]),
wherein an avalanche multiplication region (Fig. 1, multiplication region MR, ¶ [0042]) is formed across the first semiconductor region (16) and the second semiconductor region (14), and
wherein, in a planar view from the second surface (10C), at least part of a line dividing a distance equally between a boundary between the first wiring portion (25B) and an insulating film (24) and a boundary between the second wiring portion (25B) and the insulating film (24) overlaps the third semiconductor region (15) and does not overlap the first semiconductor region (16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7, 9-17, and 19-23 are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto (US 20220163674 A1) in view of Kurata et al. (US 20220149221 A1) herein after “Kurata”.
Regarding claim 1, Fig. 11 of Matsumoto discloses a photoelectric conversion apparatus (Fig. 11, sensor chip 1H, ¶ [0093]) comprising:
an avalanche diode (Fig. 11, SPAD 2, ¶ [0041]) arranged in a semiconductor layer (Fig. 11, semiconductor substrate 10, ¶ [0042]) having a first surface (Fig. 11, light entering surface 10A, ¶ [0042]) and a second surface (Fig. 11, surface 10C, ¶ [0042]) facing the first surface (10A),
wherein the avalanche diode (2) includes:
a first semiconductor region (Fig. 11, cathode 16, ¶ [0044]) of a first conductivity type (Fig. 11, “The cathode 16 is an n-type semiconductor region”, ¶ [0047]), which is arranged at a first depth,
a second semiconductor region (Fig. 11, p-type semiconductor region 14¸¶ [0044]) of a second conductivity type (Fig. 11, “The p-type semiconductor region 14 is a p-type semiconductor region”, ¶ [0046]), which is arranged at a second depth deeper than the first depth with respect to the second surface (10C),
a third semiconductor region (Fig. 11, n-type semiconductor region 15, ¶ [0044]) provided adjacent an end of the first semiconductor region (16) in a planar view from the second surface (10C),
a first wiring portion (Fig. 11, first wiring line 25B, ¶ [0054]) electrically connected to the first semiconductor region (16) via a first contact plug (Fig. 11, contact layer 25A, ¶ [0054]) (Fig. 11, “The contact layer 25A is provided in such a manner as to… couple the anode 13 or the cathode 16 to the first wiring line 25B”, ¶ [0054]), and
a second wiring portion (25B) electrically connected to the second semiconductor region (14) via a second contact plug (25A) (Fig. 11, “The contact layer 25A is provided in such a manner as to… couple the anode 13 or the cathode 16 to the first wiring line 25B”, ¶ [0054]),
wherein an avalanche multiplication region (Fig. 11, multiplication region MR, ¶ [0042]) is formed across the first semiconductor region (16) and the second semiconductor region (14).
Matsumoto fails to disclose wherein, in a planar view from the second surface, at least part of a boundary between an insulating film and the second wiring portion that faces the first wiring portion overlaps the third semiconductor region and does not overlap the first semiconductor region.
In the similar field of endeavor of photodetectors, Fig. 1 of Kurata discloses wherein, in a planar view from the second surface, at least part of a boundary between an insulating film (Fig. 1, interlayer insulating film 220, ¶ [0049]) and the second wiring portion (Fig. 1, wirings 221 connected to anode 213P, ¶ [0049]) that faces the first wiring portion (Fig. 1, wirings 221 connected to contact region 211N, ¶ [0049]) overlaps the third semiconductor region (Fig. 1, first conductivity type region 211, ¶ [0054]) and does not overlap the first semiconductor region (Fig. 1, contact region 211N, ¶ [0057]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the apparatus of Matsumoto with the wiring portions as disclosed by Kurata, to simplify the manufacturing process (see Kurata, ¶ [0052]).
Regarding claim 3, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 1 as applied above, and Fig. 11 of Matsumoto further discloses wherein, in a planar view from the second surface (10C), an area of the first semiconductor region (16) is smaller than an area of the third semiconductor region (15).
Regarding claim 4, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 1 as applied above, and Fig. 11 of Matsumoto further discloses wherein an impurity concentration in the third semiconductor region (“The n-type semiconductor region 15 is an n-type semiconductor region (n+) having a high impurity concentration”, ¶ [0046]) is lower than an impurity concentration in the first semiconductor region (“The cathode 16 is an n-type semiconductor region (n++) having a high impurity concentration”, ¶ [0047]).
Regarding claim 5, Fig. 11 of Matsumoto discloses a photoelectric conversion apparatus (1H) comprising:
an avalanche diode (2) arranged in a semiconductor layer (10) having a first surface (10A) and a second surface (10C) facing the first surface (10A),
wherein the avalanche diode (2) includes:
a first semiconductor region (16) of a first conductivity type (N-type), which is arranged at a first depth,
an avalanche multiplication region (MR) formed across the first semiconductor region (16) and a second semiconductor region (14) of a second conductivity type (P-type), which is arranged at a second depth deeper than the first depth with respect to the second surface (10C),
a first wiring portion (25B) electrically connected to the first semiconductor region (16) via a first contact plug (25A), and
a second wiring portion (25B) electrically connected to the second semiconductor region (14) via a second contact plug (25A), and
wherein, in a planar view from the second surface (10C), at least part of a boundary between an insulating film (24) and the second wiring portion (25B) that faces the first wiring portion (25B) overlaps the area between the first semiconductor region (16) and the anode (Fig. 11, anode 13, ¶ [0044]).
Matsumoto does not explicitly disclose an electric field mitigation region surrounding the avalanche multiplication region in a planar view from the second surface, between the first semiconductor region and the anode.
In the similar field of endeavor of avalanche photodiodes, Figs. 1 and 4 of Kurata discloses an electric field mitigation region (Fig. 1, “the electric field relaxation effect between the first conductivity type region 211 and the anode 213P”, ¶ [0067]) surrounding the avalanche multiplication region (Fig. 1, “the second conductivity type region 212 where avalanche multiplication is to be performed”, ¶ [0083]) in a planar view from the second surface (In Fig. 4, the region 213 which contains the anode 213P surrounds both the first conductivity type region 211 and the second conductivity type region 212. Since the electric field mitigation region is between 211 and 213P, it must surround the avalanche multiplication region), between the first semiconductor region and the anode (Fig. 1, “the electric field relaxation effect between the first conductivity type region 211 and the anode 213P”, ¶ [0067]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photoelectric conversion apparatus disclosed by Matsumoto to include the electric field mitigation region between the first semiconductor region and the anode as disclosed by Kurata, to reduce edge breakdown (see Kurata, ¶ [0087]).
Regarding claim 6, Fig. 1 of Matsumoto discloses a photoelectric conversion apparatus (1) comprising:
an avalanche diode (2) arranged in a semiconductor layer (10) having a first surface (10A) and a second surface (10C) facing the first surface (10A),
wherein the avalanche diode (2) includes:
a first semiconductor region (16) of a first conductivity type (N-type), which is arranged at a first depth,
an avalanche multiplication region (MR) formed across the first semiconductor region (16) and a second semiconductor region (14) of a second conductivity type (P-type), which is arranged at a second depth deeper than the first depth with respect to the second surface (10C),
a first wiring portion (25B) electrically connected to the first semiconductor region (16) via a first contact plug (25A), and
a second wiring portion (25B) electrically connected to the second semiconductor region (14) via a second contact plug (25A), and
wherein, in a planar view from the second surface (10C), at least part of a line dividing a distance equally between a boundary between the first wiring portion (25B) and an insulating film (24), and a boundary between the second wiring portion (25B) and the insulating film (24) overlaps the area between the first semiconductor region (16) and the anode (13).
Matsumoto does not explicitly disclose an electric field mitigation region surrounding the avalanche multiplication region in a planar view from the second surface, between the first semiconductor region and the anode.
In the similar field of endeavor of avalanche photodiodes, Figs. 1 and 4 of Kurata discloses an electric field mitigation region (Fig. 1, “the electric field relaxation effect between the first conductivity type region 211 and the anode 213P”, ¶ [0067]) surrounding the avalanche multiplication region (Fig. 1, “the second conductivity type region 212 where avalanche multiplication is to be performed”, ¶ [0083]) in a planar view from the second surface (In Fig. 4, the region 213 which contains the anode 213P surrounds both the first conductivity type region 211 and the second conductivity type region 212. Since the electric field mitigation region is between 211 and 213P, it must surround the avalanche multiplication region), between the first semiconductor region and the anode (Fig. 1, “the electric field relaxation effect between the first conductivity type region 211 and the anode 213P”, ¶ [0067]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photoelectric conversion apparatus disclosed by Matsumoto to include the electric field mitigation region between the first semiconductor region and the anode as disclosed by Kurata, to reduce edge breakdown (see Kurata, ¶ [0087]).
Regarding claim 7, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 5 as applied above, and Fig. 11 of Matsumoto further discloses wherein, in a planar view from the second surface (10C), an area of the first semiconductor region (16) is smaller than an area between the first semiconductor region (16) and the anode (13), but fails to explicitly disclose that the area is an electric field mitigation region.
In the similar field of endeavor of avalanche photodiodes, Fig. 1 of Kurata discloses an electric field mitigation region between the first semiconductor region and the anode (Fig. 1, “the electric field relaxation effect between the first conductivity type region 211 and the anode 213P”, ¶ [0067]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photoelectric conversion apparatus disclosed by Matsumoto to include the electric field mitigation region between the first semiconductor region and the anode as disclosed by Kurata, to reduce edge breakdown (see Kurata, ¶ [0087]).
Regarding claim 9, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 1, and Fig. 11 of Matsumoto further discloses wherein the first wiring portion (25B) and the second wiring portion (25B) are formed in a same wiring layer included in a plurality of wiring layers (Fig. 11, “two or more wiring lines”, ¶ [0054]) stacked on a side on which the second surface (10C) is provided.
Regarding claim 10, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 1, and Fig. 11 of Matsumoto further discloses wherein a distance from the second surface (10C) to the second wiring portion (25B) in a direction vertical to the second surface (10C) is shorter than a distance from the first wiring portion (25B) to the second wiring portion (25B) in a direction horizontal to the second surface (10C).
Regarding claim 11, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 1, and Fig. 11 of Matsumoto further discloses wherein the first surface (10A) is a light incidence surface (Fig. 11, “One surface of the semiconductor substrate 10 corresponds to the light entering surface 10A”, ¶ [0042]).
Regarding claim 12, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 1, and Fig. 11 of Matsumoto further discloses wherein, in a planar view from the second surface (10C), the second wiring portion (25B) surrounds a perimeter of the first wiring portion (25B).
Regarding claim 13, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 1, and Fig. 11 of Matsumoto further discloses wherein, in a planar view from the second surface (10C), the first semiconductor region (16) is encompassed by the second semiconductor region (14).
Regarding claim 14, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 1, and Fig. 11 of Matsumoto further discloses wherein a fourth semiconductor region (12) of the second conductivity type (“The pinning layer 12 is a p-type semiconductor region”, ¶ [0048]), which is arranged at a third depth deeper than the second depth with respect to the second surface (10C), is included.
Regarding claim 15, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 14, and Fig. 11 of Matsumoto further discloses wherein a fifth semiconductor region (11) of the first conductivity type (“The well layer 11 may be an n-type semiconductor region”, ¶ [0045]) is provided between the second semiconductor region (14) and the fourth semiconductor region (12), and
wherein an impurity concentration of the first conductivity type (N-type) in the fifth semiconductor region (11) is lower than an impurity concentration of the first conductivity type (N-type) in the first semiconductor region (16) (“The well layer 11 is preferably an n-type… having a low concentration”, “The cathode 16 is an n-type semiconductor region (n++) having a high impurity concentration”, ¶ [0045] and [0047]).
Regarding claim 16, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 15, and Fig. 11 of Matsumoto further discloses wherein a potential difference between the first semiconductor region (16) and the second semiconductor region (14) is larger than a potential difference between the second semiconductor region (14) and the fifth semiconductor region (11) (“a high negative voltage is applied to the anode 13, which by a predetermined reverse voltage is applied to the p-n junction”, ¶ [0060]).
Regarding claim 17, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 1, and Fig. 11 of Matsumoto further discloses wherein the photoelectric conversion apparatus (1H) includes a plurality of the avalanche diodes (Fig. 11, “The sensor chip 1 includes a pixel array in which two or more pixels P are disposed in an array”, ¶ [0040]),
wherein the plurality of avalanche diodes (2) includes a first avalanche diode (Fig. 11, pixels P, ¶ [0041]) and a second avalanche diode (P) adjacent to the first avalanche diode (P), and
wherein a pixel isolation portion (Fig. 11, pixel separation film TI, ¶ [0043]) is included between the first avalanche diode (2) and the second avalanche diode (2).
Regarding claim 19, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 1, and Fig. 11 of Matsumoto further discloses wherein the semiconductor layer (10) includes an oxidized film (Fig. 11, “the passivation insulating film 23 includes a silicon oxide”, ¶ [0053]) and a nitride film (Fig. 11, “the sidewall insulating film 22 includes a silicon nitride”, ¶ [0053]) that are stacked on the second surface (10C).
Regarding claim 20, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 1, and Fig. 11 of Matsumoto further discloses wherein the semiconductor layer (10) includes a plurality of recess and protrusion structures provided in the first surface (Fig. 11, “first concave-convex section 10B is provided on the back surface (the light entering surface 10A of the SPAD 2)”, ¶ [0055]).
Regarding claim 21, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 20, and Fig. 11 of Matsumoto further discloses wherein at least part of a boundary of the second wiring portion (25B) that faces the first wiring portion (25B) is encompassed by a region in which the plurality of recess and protrusion structures (10B) is formed, in a planar view from the second surface (10C).
Regarding claim 22, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 1, and Fig. 14 of Matsumoto further discloses a photoelectric conversion system (Fig. 14, electronic apparatus 201, ¶ [0103]) comprising:
the photoelectric conversion apparatus (1H) according to claim 1 (Fig. 14, “an electronic apparatus including the sensor chip 1 according to any of the embodiment and the modifications thereof described”, ¶ [0102], and
a signal processing unit (Fig. 14, signal processing circuit 206, ¶ [0103]) configured to generate an image using a signal output by the photoelectric conversion apparatus (Fig. 14, “The signal processing circuit 206 performs various signal processes on the signal charge supplied from the sensor’, ¶ [0107]).
Regarding claim 23, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 1, and Figs. 15-16 of Matsumoto further disclose a movable body (Fig. 16, vehicle 12100, ¶ [0123]) including the photoelectric conversion apparatus (1H) according to claim 1 (Fig. 15, “an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied”, ¶ [0110]), the movable body comprising:
a control unit (Fig. 15, driving system control unit 12010, ¶ [0112]) configured to control a movement of the movable body using a signal output by the photoelectric conversion apparatus (Fig. 15, “The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs”, ¶ [0112]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto (US 20220163674 A1) and Kurata (US 20220149221 A1) in further view of Hynecek (US 20180308881 A1).
Regarding claim 8, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 1 as applied above, and Fig. 11 of Matsumoto further discloses wherein the first wiring portion (25B) and the second wiring portion (25B) are formed in a plurality of wiring layers stacked on a side of the second surface (10C).
Matsumoto and Kurata fail to disclose wherein the second wiring portion is formed in a wiring layer that is a wiring layer farther from the second surface than the first contact plug connecting the first semiconductor region and the first wiring portion, and that is a wiring layer closest to the second surface among the plurality of wiring layers.
In the similar field of endeavor of avalanche photodiodes, Fig. 2 of Hynecek discloses wherein the second wiring portion (Fig. 2, bump pad 207, ¶ [0030]) is formed in a wiring layer that is a wiring layer farther from the second surface than the first contact plug (Fig. 2, regions 205, ¶ [0030]) connecting the first semiconductor region (Fig. 2, N+ contact junction 107, ¶ [0026]) and the first wiring portion (Fig. 2, regions 206, ¶ [0030]), and that is a wiring layer closest to the second surface among the plurality of wiring layers (Fig. 2, SOI circuit section 201, ¶ [0025]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photoelectric conversion apparatus disclosed by Matsumoto to include separate wiring layers as disclosed by Hynecek, to reduce parasitic capacitance and improve performance (see Hynecek, ¶ [0024]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto (US 20220163674 A1) and Kurata (US 20220149221 A1) in further view of Suzuki et al. (US 20240006445 A1) herein after “Suzuki”.
Regarding claim 18, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 17, and Fig. 11 of Matsumoto further discloses wherein the plurality of avalanche diodes (2) includes a third avalanche diode (2) adjacent to the second avalanche diode (2),
wherein a first pixel isolation portion (TI) is included between the first avalanche diode (2) and the second avalanche diode (2),
wherein a second pixel isolation portion (TI) is included between the second avalanche diode (2) and the third avalanche diode (2).
Matsumoto and Kurata fail to disclose wherein the second semiconductor region in the second avalanche diode extends up to the second pixel isolation portion from the first pixel isolation portion in a cross section vertical to the first surface.
In the similar field of endeavor of single photon avalanche diodes, Fig. 18 of Suzuki discloses the second semiconductor region (Fig. 18, p-type semiconductor region 102, ¶ [0140]) in the second avalanche diode (Fig. 18, pixel 10, ¶ [0140]) extends up to the second pixel isolation portion (Fig. 18, pixel isolation unit 110, ¶ [0140]) from the first pixel isolation portion (110) in a cross section vertical to the first surface.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photoelectric conversion apparatus disclosed by Matsumoto to include the second semiconductor region as disclosed by Suzuki, to obtain the desired electric field (see Suzuki, ¶ [0187]).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto (US 20220163674 A1) and Kurata (US 20220149221 A1) in further view of Inui et al. (US 20200273894 A1) herein after “Inui”.
Regarding claim 24, Matsumoto and Kurata together disclose the photoelectric conversion apparatus (1H) according to claim 1, but the combination fails to disclose wherein the second semiconductor region is formed over an entire surface of the third semiconductor region but the portion overlapping the first semiconductor region in the planar view.
In the similar field of endeavor of photoelectric conversion devices, Fig. 1 of Inui discloses the second semiconductor region (Fig. 1, semiconductor region 72, ¶ [0052]) is formed over an entire surface of the third semiconductor region (Fig. 1, semiconductor region 76, ¶ [0052]) but the portion overlapping the first semiconductor region (Fig. 1, semiconductor region 71, ¶ [0052]) in the planar view.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photoelectric conversion apparatus disclosed by Matsumoto to include the arrangement as disclosed by Inui, to obtain the desired device sensitivity (see Inui, ¶ [0068]).
Conclusion
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893