DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed June 12, 2026. Claims 1, 2, 5, and 6 have been amended. Claim 25 has been added. Claim 24 has been canceled. Currently, claims 1-23, and 25 are pending.
Applicant’s cancelation of claim 24 overcomes the drawing objection outlined in the previous Office Action. The drawing objection has been withdrawn.
Response to Arguments
Applicant’s arguments with respect to claims 1, 2, 5, and 6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 25 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 25, the claim recites “an insulating layer” in line 3. Claim 1, from which claim 25 depends, provides antecedent basis for an insulating layer in line 19. It is indefinite as to whether the insulating layer of claim 25 is intended to be the same insulating layer as recited by claim 1 or an additional insulating layer. For the purpose of examination, the former interpretation will be used.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 9-12, 14-17, 22-23, and 25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kawahara (US 20220157867 A1).
Regarding claim 1, Figs. 2, 6, and 8 of Kawahara disclose a photoelectric conversion apparatus (Fig. 2, SPAD array unit 11, ¶ [0089]) comprising:
an avalanche diode (Fig. 6, photodiode 21, ¶ [0094]) arranged in a semiconductor layer (Fig. 6, semiconductor substrate 101, ¶ [0119]) having a first surface (top surface in Fig. 6) and a second surface (bottom surface in Fig. 6) facing the first surface (top surface in Fig. 6),
wherein the avalanche diode (21) includes:
a first semiconductor region (Fig. 6, N+type semiconductor region 106, ¶ [0120]) of a first conductivity type (N-type), which is arranged at a first depth,
a second semiconductor region (Fig. 6, P+type semiconductor region 105, ¶ [0120]) of a second conductivity type (P-type), which is arranged at a second depth deeper than the first depth with respect to the second surface (bottom surface in Fig. 6),
a third semiconductor region (Fig. 8, portion of 102 surrounding 106, ¶ [0121]) provided adjacent an end of the first semiconductor region (106) in a planar view from the second surface (bottom surface in Fig. 6),
a first wiring portion (Fig. 6, cathode electrode 121, ¶ [0130]) electrically connected to the first semiconductor region (106) via a first contact plug (Fig. 6, cathode contact 107, ¶ [0120]), and
a second wiring portion (Fig. 6, anode electrode 122, ¶ [0119]) electrically connected to the second semiconductor region (105) via a second contact plug (Fig. 6, anode contact 108, ¶ [0120]),
wherein an avalanche multiplication region is formed between the first semiconductor region (106) and the second semiconductor region (105) (“in the PN junction region between the P+type semiconductor region 105 and the N+type semiconductor region 106, a strong electric field that accelerates entering charge and generates the avalanche current”, ¶ [0147]), and
wherein, in a planar view from the second surface (bottom surface in Fig. 6), at least part of a boundary between an insulating film (Fig. 6, interlayer dielectric 123, ¶ [0140]) and the second wiring portion (122) that faces the first wiring portion (121) overlaps the third semiconductor region (102) and does not overlap the avalanche multiplication region (PN junction of 105 and 106).
Regarding claim 2, Figs. 2, 6, and 8 of Kawahara disclose a photoelectric conversion apparatus (11) comprising:
a plurality of avalanche diodes (21) arranged in a semiconductor layer (101) having a first surface (top surface in Fig. 6) and a second surface (bottom surface in Fig. 6) facing the first surface (top surface in Fig. 6),
wherein the avalanche diode (21) includes:
a first semiconductor region (106) of a first conductivity type (N-type), which is arranged at a first depth,
a second semiconductor region (105) of a second conductivity type (P-type), which is arranged at a second depth deeper than the first depth with respect to the second surface (bottom surface in Fig. 6),
a third semiconductor region (102), which overlaps the second semiconductor region (105), provided adjacent to an end of the first semiconductor region (106) in a planar view from the second surface (bottom surface in Fig. 6),
a first wiring portion (121) electrically connected to the first semiconductor region (106) via a first contact plug (107), and
a second wiring portion (122) electrically connected to the second semiconductor region (105) via a second contact plug (108),
wherein an avalanche multiplication region (PN junction of 105 and 106) is formed between the first semiconductor region (106) and the second semiconductor region (105), and
wherein, in a planar view from the second surface (bottom surface in Fig. 6), at least part of a line dividing a distance equally between a boundary between the first wiring portion (121) and an insulating film (123) and a boundary between the second wiring portion (122) and the insulating film (123) overlaps the third semiconductor region (102) and does not overlap the avalanche multiplication region (PN junction of 105 and 106).
Regarding claim 3, Figs. 2, 6, and 8 of Kawahara disclose the photoelectric conversion apparatus according to claim 1 as applied above, and Fig. 6 of Kawahara further discloses wherein, in a planar view from the second surface (bottom surface in Fig. 6), an area of the first semiconductor region (106) is smaller than an area of the third semiconductor region (102).
Regarding claim 4, Figs. 2, 6, and 8 of Kawahara disclose the photoelectric conversion apparatus according to claim 1 as applied above, and Fig. 6 of Kawahara further discloses wherein an impurity concentration in the third semiconductor region (102) is lower than an impurity concentration in the first semiconductor region (106) (“region 102 is, for example, an N-type well region or a region containing donors with low concentration”, “the N+type semiconductor region 106 is, for example, a region containing donors with higher concentration”, ¶ [0121] and [0124]).
Regarding claim 9, Figs. 2, 6, and 8 of Kawahara disclose the photoelectric conversion apparatus according to claim 1 as applied above, and Fig. 6 of Kawahara further discloses wherein the first wiring portion (121) and the second wiring portion (122) are formed in a same wiring layer included in a plurality of wiring layers stacked on a side on which the second surface (bottom surface in Fig. 6) is provided.
Regarding claim 10, Figs. 2, 6, and 8 of Kawahara disclose the photoelectric conversion apparatus according to claim 1 as applied above, and Fig. 6 of Kawahara further discloses wherein a distance from the second surface (bottom surface in Fig. 6) to the second wiring portion (122) in a direction vertical to the second surface (bottom surface in Fig. 6) is shorter than a distance from the first wiring portion (121) to the second wiring portion (122) in a direction horizontal to the second surface (The second wiring portion 122 is embedded in the second surface of the semiconductor layer 101. Therefore, the vertical distance is shorter than the horizontal distance between the first and second wiring portions).
Regarding claim 11, Figs. 2, 6, and 8 of Kawahara disclose the photoelectric conversion apparatus according to claim 1 as applied above, and Fig. 6 of Kawahara further discloses wherein the first surface (top surface in Fig. 6) is a light incidence surface.
Regarding claim 12, Figs. 2, 6, and 8 of Kawahara disclose the photoelectric conversion apparatus according to claim 1 as applied above, and Fig. 7 of Kawahara further discloses wherein, in a planar view from the second surface (bottom surface in Fig. 6), the second wiring portion (122) surrounds a perimeter of the first wiring portion (121).
Regarding claim 14, Figs. 2, 6, and 8 of Kawahara disclose the photoelectric conversion apparatus according to claim 1 as applied above, and Fig. 6 of Kawahara further discloses wherein a fourth semiconductor region (Fig. 6, P-type semiconductor region 104, ¶ [0122]) of the second conductivity type (P-type), which is arranged at a third depth deeper than the second depth with respect to the second surface (bottom surface in Fig. 6), is included.
Regarding claim 15, Fig. 6 of Kawahara discloses the photoelectric conversion apparatus according to claim 14 as applied above, and Fig. 6 of Kawahara further discloses wherein a fifth semiconductor region (Fig. 6, N-type semiconductor region 103, ¶ [0123]) of the first conductivity type (N-type) is provided between the second semiconductor region (105) and the fourth semiconductor region (104), and
wherein an impurity concentration of the first conductivity type (N-type) in the fifth semiconductor region (103) is lower than an impurity concentration of the first conductivity type (N-type) in the first semiconductor region (106) (“the N+type semiconductor region 106 is, for example, a region containing donors with higher concentration than the N-type semiconductor region 103”, ¶ [0124]).
Regarding claim 16, Fig. 6 of Kawahara discloses the photoelectric conversion apparatus according to claim 15 as applied above, and Fig. 6 of Kawahara further discloses wherein a potential difference between the first semiconductor region (106) and the second semiconductor region (105) is larger than a potential difference between the second semiconductor region (105) and the fifth semiconductor region (103) (“when the reverse bias voltage V_SPAD equal to or larger than the breakdown voltage is applied between the cathode contact 107 and the anode contact 108, an electric field for guiding the charge generated in the photoelectric conversion region 102 to the N-type semiconductor region 103 is formed due to a potential difference between the P-type semiconductor region 104 and the N+type semiconductor region 106”, ¶ [0147]).
Regarding claim 17, Figs. 2, 6, and 8 of Kawahara disclose the photoelectric conversion apparatus according to claim 1 as applied above, and Figs. 2 and 6 of Kawahara further disclose wherein the photoelectric conversion apparatus (11) includes a plurality of the avalanche diodes (“The SPAD array unit 11 includes a plurality of SPAD pixels 20 arranged in a matrix”, ¶ [0089])),
wherein the plurality of avalanche diodes (21) includes a first avalanche diode (21) and a second avalanche diode (21) adjacent to the first avalanche diode (21), and
wherein a pixel isolation portion (Fig. 6, element isolation portions 110, ¶ [0119]) is included between the first avalanche diode (21) and the second avalanche diode (21).
Regarding claim 22, Figs. 2, 6, and 8 of Kawahara disclose the photoelectric conversion apparatus according to claim 1 as applied above, and Fig. 37 of Kawahara further discloses a photoelectric conversion system (Fig. 37, imaging device 8201, ¶ [0257]) comprising:
the photoelectric conversion apparatus (11) according to claim 1, and
a signal processing unit (Fig. 37, signal processing circuit 8206, ¶ [0257]) configured to generate an image using a signal output by the photoelectric conversion apparatus (“The signal processing circuit 8206 performs various signal processing on the signal charge output from the solid-state imaging element 8204”, ¶ [0262]).
Regarding claim 23, Figs. 2, 6, and 8 of Kawahara disclose the photoelectric conversion apparatus according to claim 1 as applied above, and Fig. 39 of Kawahara further discloses a movable body (Fig. 39, vehicle 7900, ¶ [0273]) including the photoelectric conversion apparatus (11) according to claim 1, the movable body (7900) comprising:
a control unit (Fig. 39, integrated control unit 7600, ¶ [0279]) configured to control a movement of the movable body using a signal output by the photoelectric conversion apparatus (“The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 according to various programs, on the basis of information acquired”, ¶ [0287]).
Regarding claim 25, Figs. 2, 6, and 8 of Kawahara disclose the photoelectric conversion apparatus according to claim 1 as applied above, and Fig. 6 of Kawahara further discloses wherein, in a planar view from the second surface (bottom surface in Fig. 6), a line dividing a distance equally between a boundary between the first wiring portion (121) and an insulating film (123) and a boundary between the second wiring portion (122) and the insulating film (123) does not overlap the first semiconductor region (106).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kawahara (US 20220157867 A1) in view of Kurata et al. (US 20220149221 A1) herein after “Kurata”.
Regarding claim 5, Figs. 2, 6, and 8 of Kawahara disclose a photoelectric conversion apparatus (11) comprising:
an avalanche diode (21) arranged in a semiconductor layer (101) having a first surface (top surface in Fig. 6) and a second surface (bottom surface in Fig. 6) facing the first surface (top surface in Fig. 6),
wherein the avalanche diode (21) includes:
a first semiconductor region (106) of a first conductivity type (N-type), which is arranged at a first depth,
an avalanche multiplication region (PN junction of 105 and 106) formed between the first semiconductor region (106) and a second semiconductor region (105) of a second conductivity type (P-type), which is arranged at a second depth deeper than the first depth with respect to the second surface (bottom surface in Fig. 6),
an electric field mitigation region surrounding the avalanche multiplication region (PN junction of 105 and 106) in a planar view from the second surface (bottom surface in Fig. 6),
a first wiring portion (121) electrically connected to the first semiconductor region (106) via a first contact plug (107), and
a second wiring portion (122) electrically connected to the second semiconductor region (105) via a second contact plug (108), and
wherein, in a planar view from the second surface (bottom surface in Fig. 6), a boundary between an insulating film (123) and the second wiring portion (122) that faces the first wiring portion (121) overlaps the area between the first semiconductor region (106) and the second contact plug (108) and does not overlap the avalanche multiplication region (PN junction of 105 and 106).
Kawahara does not explicitly disclose an electric field mitigation region surrounding the avalanche multiplication region in a planar view from the second surface, between the first semiconductor region and the second contact plug.
In the similar field of endeavor of avalanche photodiodes, Figs. 1 and 4 of Kurata discloses an electric field mitigation region (Fig. 1, “the electric field relaxation effect between the first conductivity type region 211 and the anode 213P”, ¶ [0067]) surrounding the avalanche multiplication region (Fig. 1, “the second conductivity type region 212 where avalanche multiplication is to be performed”, ¶ [0083]) in a planar view from the second surface (In Fig. 4, the region 213 which contains the anode 213P surrounds both the first conductivity type region 211 and the second conductivity type region 212. Since the electric field mitigation region is between 211 and 213P, it must surround the avalanche multiplication region), between the first semiconductor region and the anode (Fig. 1, “the electric field relaxation effect between the first conductivity type region 211 and the anode 213P”, ¶ [0067]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photoelectric conversion apparatus disclosed by Kawahara to include the electric field mitigation region between the first semiconductor region and the anode as disclosed by Kurata, to reduce edge breakdown (see Kurata, ¶ [0087]).
Regarding claim 6, Figs. 2, 6, and 8 of Kawahara disclose a photoelectric conversion apparatus (11) comprising:
an avalanche diode (21) arranged in a semiconductor layer (101) having a first surface (top surface in Fig. 6) and a second surface (bottom surface in Fig. 6) facing the first surface (top surface in Fig. 6),
wherein the avalanche diode (21) includes:
a first semiconductor region (106) of a first conductivity type (N-type), which is arranged at a first depth,
an avalanche multiplication region (PN junction of 105 and 106) formed between the first semiconductor region (106) and a second semiconductor region (105) of a second conductivity type (P-type), which is arranged at a second depth deeper than the first depth with respect to the second surface (bottom surface in Fig. 6),
an electric field mitigation region surrounding the avalanche multiplication region (PN junction of 105 and 106) in a planar view from the second surface (bottom surface in Fig. 6),
a first wiring portion (121) electrically connected to the first semiconductor region (106) via a first contact plug (107), and
a second wiring portion (122) electrically connected to the second semiconductor region (105) via a second contact plug (108), and
wherein, in a planar view from the second surface (bottom surface in Fig. 6), a line dividing a distance equally between a boundary between the first wiring portion (121) and an insulating film (123), and a boundary between the second wiring portion (122) and the insulating film (123) overlaps the area between the first semiconductor region (106) and the second contact plug (108) and does not overlap the avalanche multiplication region (PN junction of 105 and 106).
Kawahara does not explicitly disclose an electric field mitigation region surrounding the avalanche multiplication region in a planar view from the second surface, between the first semiconductor region and the second contact plug.
In the similar field of endeavor of avalanche photodiodes, Figs. 1 and 4 of Kurata discloses an electric field mitigation region (Fig. 1, “the electric field relaxation effect between the first conductivity type region 211 and the anode 213P”, ¶ [0067]) surrounding the avalanche multiplication region (Fig. 1, “the second conductivity type region 212 where avalanche multiplication is to be performed”, ¶ [0083]) in a planar view from the second surface (In Fig. 4, the region 213 which contains the anode 213P surrounds both the first conductivity type region 211 and the second conductivity type region 212. Since the electric field mitigation region is between 211 and 213P, it must surround the avalanche multiplication region), between the first semiconductor region and the anode (Fig. 1, “the electric field relaxation effect between the first conductivity type region 211 and the anode 213P”, ¶ [0067]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photoelectric conversion apparatus disclosed by Kawahara to include the electric field mitigation region between the first semiconductor region and the anode as disclosed by Kurata, to reduce edge breakdown (see Kurata, ¶ [0087]).
Regarding claim 7, Kawahara and Kurata together disclose the photoelectric conversion apparatus according to claim 5 as applied above, and Fig. 6 of Kawahara further discloses wherein, in a planar view from the second surface (bottom surface in Fig. 6), an area of the first semiconductor region (106) is smaller than an area between the first semiconductor region (16) and the second contact plug (108), but fails to explicitly disclose that the area is an electric field mitigation region.
In the similar field of endeavor of avalanche photodiodes, Fig. 1 of Kurata discloses an electric field mitigation region between the first semiconductor region and the anode (Fig. 1, “the electric field relaxation effect between the first conductivity type region 211 and the anode 213P”, ¶ [0067]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photoelectric conversion apparatus disclosed by Kawahara to include the electric field mitigation region between the first semiconductor region and the anode as disclosed by Kurata, to reduce edge breakdown (see Kurata, ¶ [0087]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kawahara (US 20220157867 A1) in view of Hynecek (US 20180308881 A1).
Regarding claim 8, Figs. 2, 6, and 8 of Kawahara disclose the photoelectric conversion apparatus according to claim 1 as applied above, and Fig. 6 of Kawahara further discloses wherein the first wiring portion (121) and the second wiring portion (122) are formed in a plurality of wiring layers stacked on a side of the second surface (bottom surface in Fig. 6).
Kawahara fails to disclose wherein the second wiring portion is formed in a wiring layer that is a wiring layer farther from the second surface than the first contact plug connecting the first semiconductor region and the first wiring portion, and that is a wiring layer closest to the second surface among the plurality of wiring layers.
In the similar field of endeavor of avalanche photodiodes, Fig. 2 of Hynecek discloses wherein the second wiring portion (Fig. 2, bump pad 207, ¶ [0030]) is formed in a wiring layer that is a wiring layer farther from the second surface than the first contact plug (Fig. 2, regions 205, ¶ [0030]) connecting the first semiconductor region (Fig. 2, N+ contact junction 107, ¶ [0026]) and the first wiring portion (Fig. 2, regions 206, ¶ [0030]), and that is a wiring layer closest to the second surface among the plurality of wiring layers (Fig. 2, SOI circuit section 201, ¶ [0025]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photoelectric conversion apparatus disclosed by Kawahara to include separate wiring layers as disclosed by Hynecek, to reduce parasitic capacitance and improve performance (see Hynecek, ¶ [0024]).
Claims 13, and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Kawahara (US 20220157867 A1) in view of Matsumoto (US 20220163674 A1).
Regarding claim 13, Figs. 2, 6, and 8 of Kawahara disclose the photoelectric conversion apparatus according to claim 1 as applied above, but Kawahara fails to disclose wherein, in a planar view from the second surface, the first semiconductor region is encompassed by the second semiconductor region.
In the similar field of endeavor of avalanche photodiodes, Fig. 11 of Matsumoto discloses wherein, in a planar view from the second surface (Fig. 11, surface 10C, ¶ [0042]), the first semiconductor region (Fig. 1, cathode 16, ¶ [0044]) is encompassed by the second semiconductor region (Fig. 1, p-type semiconductor region 14¸¶ [0044]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photoelectric conversion apparatus disclosed by Kawahara to include the semiconductor regions arranged as disclosed by Matsumoto, to obtain the desired electric field properties (see Matsumoto, ¶ [0050]).
Regarding claim 19, Figs. 2, 6, and 8 of Kawahara disclose the photoelectric conversion apparatus according to claim 1 as applied above, but Kawahara fails to disclose wherein the semiconductor layer includes an oxidized film and a nitride film that are stacked on the second surface.
In the similar field of endeavor of avalanche photodiodes, Fig. 11 of Matsumoto discloses wherein the semiconductor layer (Fig. 11, semiconductor substrate 10, ¶ [0042]) includes an oxidized film (Fig. 11, “the passivation insulating film 23 includes a silicon oxide”, ¶ [0053]) and a nitride film (Fig. 11, “the sidewall insulating film 22 includes a silicon nitride”, ¶ [0053]) that are stacked on the second surface (10C).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photoelectric conversion apparatus disclosed by Kawahara to include oxide and nitride layers as disclosed by Matsumoto, to further electrically isolate the wiring layers (see Matsumoto, ¶ [0053]).
Regarding claim 20, Figs. 2, 6, and 8 of Kawahara disclose the photoelectric conversion apparatus according to claim 1 as applied above, but Kawahara fails to disclose wherein the semiconductor layer includes a plurality of recess and protrusion structures provided in the first surface.
In the similar field of endeavor of avalanche photodiodes, Fig. 11 of Matsumoto discloses wherein the semiconductor layer (10) includes a plurality of recess and protrusion structures provided in the first surface (Fig. 11, “first concave-convex section 10B is provided on the back surface (the light entering surface 10A of the SPAD 2)”, ¶ [0055]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photoelectric conversion apparatus disclosed by Kawahara to include recesses and protrusion as disclosed by Matsumoto, to obtain the desired diffraction properties (see Matsumoto, ¶ [0052]).
Regarding claim 21, Kawahara and Matsumoto together disclose the photoelectric conversion apparatus according to claim 20 as applied above, but Kawahara fails to disclose wherein at least part of a boundary of the second wiring portion that faces the first wiring portion is encompassed by a region in which the plurality of recess and protrusion structures is formed, in a planar view from the second surface.
In the similar field of endeavor of avalanche photodiodes, Fig. 11 of Matsumoto discloses wherein at least part of a boundary of the second wiring portion (25B) that faces the first wiring portion (25B) is encompassed by a region in which the plurality of recess and protrusion structures (10B) is formed, in a planar view from the second surface (10C).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photoelectric conversion apparatus disclosed by Kawahara to include recesses and protrusion as disclosed by Matsumoto, to obtain the desired diffraction properties (see Matsumoto, ¶ [0052]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kawahara (US 20220157867 A1) in view of Suzuki et al. (US 20240006445 A1) herein after “Suzuki”.
Regarding claim 18, Figs. 2 and 6 of Kawahara disclose the photoelectric conversion apparatus according to claim 17 as applied above, and Figs. 2 and 6 of Kawahara further disclose wherein the plurality of avalanche diodes (21) includes a third avalanche diode (21) adjacent to the second avalanche diode (21),
wherein a first pixel isolation portion (110) is included between the first avalanche diode (21) and the second avalanche diode (21),
wherein a second pixel isolation portion (110) is included between the second avalanche diode (21) and the third avalanche diode (21).
Kawahara fails to disclose wherein the second semiconductor region in the second avalanche diode extends up to the second pixel isolation portion from the first pixel isolation portion in a cross section vertical to the first surface.
In the similar field of endeavor of single photon avalanche diodes, Fig. 18 of Suzuki discloses the second semiconductor region (Fig. 18, p-type semiconductor region 102, ¶ [0140]) in the second avalanche diode (Fig. 18, pixel 10, ¶ [0140]) extends up to the second pixel isolation portion (Fig. 18, pixel isolation unit 110, ¶ [0140]) from the first pixel isolation portion (110) in a cross section vertical to the first surface.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photoelectric conversion apparatus disclosed by Kawahara to include the second semiconductor region as disclosed by Suzuki, to obtain the desired electric field (see Suzuki, ¶ [0187]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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