DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9,11,13,14,19,20 and 34-38 are rejected under 35 U.S.C. 103 as being unpatentable over Qi et al. (US20180358452A1) in view of Peng et al. (US20230066230A1).
Regarding claim 1, Fig. 33 of Qi teaches a vertical channel field-effect transistor (VCFET), comprising:
a substrate 401 (para.0077) comprising a substrate surface;
a channel 404 (para.0080), comprising:
a first channel portion 404a/404b (para.0080) comprising a first end surface,
the first end surface having a first width 492 (para.0091) in a first direction parallel to the substrate surface; and
a second channel portion 404c (para.0080) comprising
a fourth end surface 421 (para.0087),
the fourth end surface 421 having a second width 491 (para.0091) in the first direction greater than the first width 492;
a gate 410 (para.0084) adjacent to the first channel portion 404a/404b;
a source/drain 402 (para.0081) coupled to the first end surface of the first channel portion 404a/404b; and
a drain/source 416 (para.0087) coupled to the fourth end surface of the second channel portion 404c; a first spacer 408 (para.0082) adjacent to the gate 410 and the source/drain 402,
Qi does not teach wherein the first spacer comprising: a plurality of first dielectric layers each extending in the first direction and parallel to each other in the first direction; and one or more first air gaps each between two first dielectric layers that are adjacent to each other for each of the plurality of first dielectric layers.
Fig.1 of Peng teaches nanostructure transistors with spacer structures formed between source/drain epitaxial structures and metal gate structures; wherein each spacer structure 130 includes a spacer material 130a with an air gap or air cavity 130b (air gap 130b) (para.0018).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the spacer structures of Peng in the teachings of Qi because the spacer structures have air gaps which help to reduce the parasitic capacitance formed between gate structures and source/drain structures (Peng, [para.0069]).
Regarding claim 2, Qi further teaches the VCFET of claim 1, wherein the channel 404 (para.0080) is configured to transport charge in a second direction orthogonal to the substrate surface. It is disclosed in paragraph 0087 that for a P-type VFET, epitaxial semiconductor material of the upper and/or first source/drain regions can be silicon germanium (SiGe) in order to enhance majority charge carrier mobility within the P-type VFET's channel region and, thereby enhance performance.
Regarding claim 3, Qi further teaches the VCFET of claim 1, wherein a ratio of the second width 491 (para.0091) to the first width 492 (para.0091) is at least 1.1.
Regarding claim 4, Qi further teaches the VCFET of claim 1, wherein: the first width 492 (para.0092) is between one (1) nanometer (nm) and ten (10) nm (para.0092, wherein thickness 492 can be less than 6 nm); and the second width 491 (para.0091) is between one (1) nm and twenty (20) nm (para.0080, wherein thickness 491 can be at least 10 nm).
Regarding claim 5, Qi further teaches the VCFET of claim 1, wherein: the first channel portion 404a/404b (para.0080) has a first height in a second direction orthogonal to the substrate surface; the first width 492 (para.0092) is less than the first height; and the second channel portion 404c (para.0080) has a second height in the second direction.
Regarding claim 6, Fig.33 of Qi further teaches the VCFET of claim 1, wherein:
the first spacer 408 (para.0082) is adjacent to the first end surface of the first channel portion 404a/404b (para.0080) and the gate 410 (para.0084).
Regarding claim 7, Qi further teaches the VCFET of claim 1, further comprising:
a spacer sidewall 409 (para.0095) extending in a second direction orthogonal to the substrate surface and
along a first longitudinal axis orthogonal to the substrate surface; and the spacer sidewall 409 adjacent to the first spacer 408 (para.0082), and the gate 410 (para.0084).
Regarding claim 8, Peng further teaches the VCFET of claim 1, wherein:
each of the one or more first air gaps 130b (para.0018) has a first length extending in the first
direction and a first height extending in a second direction orthogonal to the substrate surface; and the first length is greater than the first height.
Regarding claim 9, Peng further teaches the VCFET of claim 1, wherein: the one or more first air gaps 130b (para.0018) comprise a plurality of first air gaps 130b.
Regarding claim 11, Peng further teaches the VCFET of claim 1, wherein: the plurality of first dielectric layers 130a (para.0018) comprises Silicon Nitride (SiN) (para.0018, wherein spacer material 130a is Silicon Nitride (SiN-based) material).
Regarding claim 13, Qi further teaches the VCFET of claim 1, wherein the first channel portion 404a/404b (para.0080) comprises a first sidewall 409 (para.0095); and wherein the gate 410 (para.0084) surrounds the first sidewall 409 of the first channel portion 404a/404b.
Regarding claim 14, Qi further teaches the VCFET of claim 1, wherein an effective length of the gate 410 (para.0084), Leff, is defined by a first height of the gate 410 in a second direction orthogonal to the substrate surface.
Regarding claim 19, Qi further teaches the VCFET of claim 1, wherein:
the source/drain 402 (para.0081) is comprised of a first material comprised of the group consisting of silicon and silicon germanium; and
the drain/source 416 (para.0087) is comprised of a second material comprised of the group consisting of silicon and silicon germanium.
Regarding claim 20, Qi further teaches the VCFET of claim 1, wherein:
the source/drain 402 (para.0081) is adjacent to the first end surface of the first channel portion 404a/404b (para.0080) adjacent to
the substrate surface; and the drain/source 416 (para.0087) is adjacent to the fourth end surface 421 (para.0087) of the second channel portion 404c (para.0080).
Regarding claim 34, Fig. 33 of Qi further teaches the VCFET of claim 1, wherein the first spacer 408 (para.0082) is further adjacent to the gate 410 (para.0084) and the first end surface of the first channel portion 404a/404b (para.0080).
Regarding claim 35, the combination of Qi and Peng teaches the VCFET of claim 1, wherein:
the plurality of first dielectric layers 130a (para.0018) comprises:
a first, first dielectric layer 130a;
a second, first dielectric layer 130a; and
a third, first dielectric layer 130a; and the one or more first air gaps 130b (para.0018) comprise:
a first, first air gap 130b (wherein the second, first air gap is the bottom air gap in Fig.33 of Peng) between the first, first dielectric layer and the second, first dielectric layer; and
a second, first air gap 130b (wherein the second, first air gap is the middle one in Fig.33 of Peng) between the second, first dielectric layer and the third, first dielectric layer.
Regarding claim 36, Qi further teaches the VCFET of claim 1, further comprising: a second spacer 415 (para.0084) adjacent to the gate 410 (para.0084) and the drain/source 416 (para.0087).
Qi does not teach wherein the second spacer comprising: a plurality of second dielectric layers each extending in the first direction and parallel to each other in the first direction; and one or more second air gaps each between two second dielectric layers that are adjacent to each other for each of the plurality of second dielectric layers.
Fig.1 of Peng teaches nanostructure transistors with spacer structures formed between source/drain epitaxial structures and metal gate structures; wherein each spacer structure 130 includes a spacer material 130a with an air gap or air cavity 130b (air gap 130b) (para.0018).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the spacer structures of Peng in the teachings of Qi because the spacer structures have air gaps which help to reduce the parasitic capacitance formed between gate structures and source/drain structures (Peng, [para.0069]).
Regarding claim 37, Qi further teaches the VCFET of claim 36, further comprising:
a spacer sidewall 409 (para.0095) extending in a second direction orthogonal to the substrate surface and
along a first longitudinal axis orthogonal to the substrate surface; and
the spacer sidewall 409 adjacent to the second spacer 415 (para.0084) and the gate 410 (para.0084).
Regarding claim 38, the combination of Qi and Peng further teaches the VCFET of claim 36, wherein:
each of the one or more second air gaps 130b (para.0018) has a second length extending in the first direction and
a second height extending in a second direction orthogonal to the substrate surface; and
the second length is greater than the second height.
Claims 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Qi et al. (US20180358452A1) in view of Peng et al. (US20230066230A1) and in further view of Yeh et al. (US20200303497A1).
Regarding claim 15, Qi does not teach wherein the VCFET of claim 1, further comprising a P semiconductor type (P-type) well adjacent to the substrate;
wherein:
the source/drain comprises an N-type source/drain;
the drain/source comprises an N-type drain/source; and
the N-type source/drain is disposed in the P-type well.
Fig.10 of Yeh teaches a P semiconductor type (P-type) well (see annotated Fig.10) adjacent to the substrate 10 (para.0024);
wherein:
the source/drain 16 (para.0045) comprises an N-type source/drain;
the drain/source 38 (para.0068) comprises an N-type drain/source; and
the N-type source/drain 16 (para.0045) is disposed in the P-type well.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include nFET source/drain structure nFET drain/source structure in the device of Qi, as taught by Yeh, in order to effectuate an n-type threshold voltage shift (Yeh, [para.0050]).
Regarding claim 17, Qi does not teach wherein the VCFET of claim 1, further comprising an N semiconductor type (N-type) well adjacent to the substrate;
wherein:
the source/drain comprises a P-type source/drain;
the drain/source comprises a P-type drain/source; and
the P-type source/drain is disposed in the N-type well.
Fig.10 of Yeh teaches wherein:
the source/drain 16 (para.0045) comprises a P-type source/drain;
the drain/source 38 (para.0068) comprises a P-type drain/source; and
the P-type source/drain is disposed in the N-type well.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include pFET source/drain and pFET drain/source in the device of Qi, as taught by Yeh, in order to effectuate a p-type threshold voltage shift (Yeh, [para.0052]).
Claims 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Qi et al. (US20180358452A1) in view of Peng et al. (US20230066230A1) and Yeh et al. (US20200303497A1) and in further view of Chu et al. (US20070148939A1).
Regarding claim 16, the combination of Qi and Yeh does not teach wherein a crystal structure for a channel sidewall of the channel is oriented in a <001> plane relative to the substrate surface.
Fig.8B of Chu teaches wherein the the n-channels on the four sidewalls of the mesa structure or vertical structure are in the (001), (010), (001) and (010) planes when mesa structure or vertical structure of the nMOSFET is rotated 45 degrees from the wafer notch line (para.0049).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to Chu’s rotated vertical structure of the nMOSFET in the teachings of Qi in order to achieve high hole-mobility and high electron-mobility simultaneously (Chu, [para.0049]).
Regarding claim 18, Qi does not teach wherein a crystal structure for a channel sidewall of the channel is oriented in a <011> plane relative to the substrate surface.
Fig.8B of Chu teaches wherein mesa structure or vertical structure of the pMOSFET has a sidewall aligned with the wafer notch line, and the p-channels on the sidewalls of the mesa structure or vertical structure are in the (011), (011), (011) and (011) planes.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to Chu’s rotated vertical structure of the nMOSFET in the teachings of Qi in order to achieve high hole-mobility and high electron-mobility simultaneously (Chu, [para.0049]).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Qi et al. (US20180358452A1) in view of Peng et al. (US20230066230A1) and in further view of Lu et al. (US20210280684A1).
Regarding claim 21, Qi does not teach wherein the VCFET of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
Lu teaches, in paragraph 0029, a transistor that is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the transistor into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle as taught by Lu in order to reduce parasitic capacitance and thus improve the overall performance and efficiency of the devices and no significant additional cost of manufacture (Lu, [para.0017]).
Claims 32,33,39 and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh et al. (US20200303497A1) in view of Peng et al. (US20230066230A1).
Regarding claim 32, Fig. 10 of Yeh teaches an integrated circuit (IC), comprising:
a substrate 10 (para.0021) comprising a substrate surface;
a plurality of field-effect transistors (FETs) on the substrate surface, the plurality of FETs (para.0033),
comprising:
a P-semiconductor type (P-type) FET (see annotated Fig.10), comprising:
a P-type channel 12 (para.0072), comprising:
a first P-type channel portion (see annotated Fig.10) comprising a first end surface (see annotated Fig.10),
the first end surface (see annotated Fig.10) having a first width in a first direction parallel to the substrate surface; and
a second P-type channel portion (see annotated Fig.10) comprising a fourth end surface (see annotated Fig.10), the fourth end surface having a second width in the first direction greater than the first width;
a first gate 24 (para.0072) adjacent to the first P-type channel portion (see annotated Fig.10); a P-type source/drain 16 (para.0046) coupled to the first end surface of the first P-type channel portion; a P-type drain/source 38 (para.0066) coupled to the fourth end surface of the second P-type channel portion 404c (para.0080);
a first spacer 35L (para.0063) adjacent to the first gate 24 and the P-type source/drain 16;
an N-semiconductor type (N-type) FET (see annotated Fig.10), comprising:
a N-type channel 12 (para.0072), comprising:
a first N-type channel portion (see annotated Fig.10) comprising a fifth end surface (see annotated Fig.10), the fifth end surface having a third width in the first direction parallel to the substrate surface; and
a second N-type channel portion (see annotated Fig.10) comprising an eighth end surface (see annotated Fig.10), the eighth end surface (see annotated Fig.10) having a fourth width in the first direction greater than the third width;
a second gate 24 (para.0072) adjacent to the first N-type channel portion; an N-type source/drain 16 (para.0046) coupled to the fifth end surface of the first N-type channel portion;
an N-type drain/source 38 (para.0066) coupled to the eighth end surface of the second N-type channel portion; and
a second spacer 35L (para.0063) adjacent to the second gate 24 and the N-type source/drain 16,
Annotated Fig.10
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media_image1.png
819
793
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Greyscale
Yeh does not teach wherein the first spacer comprising:
a plurality of first dielectric layers each extending in the first direction and parallel to each other in the first direction; and
one or more first air gaps each between two first dielectric layers that are adjacent to each other for each of the plurality of first dielectric layers; and the second spacer comprising:
a plurality of second dielectric layers each extending in the first direction and parallel to each other in the first direction; and
one or more second air gaps each between two second dielectric layers that are adjacent to each other for each of the plurality of second dielectric layers.
Fig.1 of Peng teaches nanostructure transistors with spacer structures formed between source/drain epitaxial structures and metal gate structures; wherein each spacer structure 130 includes a spacer material 130a with an air gap or air cavity 130b (air gap 130b) (para.0018).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the spacer structures of Peng in the teachings of Qi because the spacer structures have air gaps which help to reduce the parasitic capacitance formed between gate structures and source/drain structures (Peng, [para.0069]).
Regarding claim 33, Yeh further teaches the IC of claim 32, wherein:
the P-type channel 12 (para.0072) is configured to transport charge in a second direction orthogonal to the substrate surface; and
the N-type channel 12 (para.0072) is configured to transport charge in the second direction orthogonal to the substrate surface.
Regarding claim 39, Yeh further teaches the IC of claim 32, wherein:
the first spacer 35L (para.0063) is further adjacent to the first gate 24 (para.0072) and the first end surface of the first P- type channel portion (see annotated Fig.10); and
the second spacer 35L (para.0063) is further adjacent to the second gate 24 (para.0072) and the fifth end surface of the first N-type channel portion (see annotated Fig.10).
Regarding claim 40, the combination of Peng and Yeh teaches the IC of claim 32, wherein:
the plurality of first dielectric layers 130a (Peng, para.0018) comprises:
a first, first dielectric layer 130a;
a second, first dielectric layer 130a; and
a third, first dielectric layer 130a;
the one or more first air gaps 130b (Peng, para.0018) comprise:
a first, first air gap (wherein the first, first air gap is the bottom air gap in Fig.33 of Peng) between the first, first dielectric layer and the second, first dielectric layer; and
a second, first air gap (wherein the second, first air gap is the bottom air gap in Fig.33 of Peng) between the second, first dielectric layer and the third, first dielectric layer;
the plurality of second dielectric layers 130a (Peng, para.0018) comprises:
a first, second dielectric layer 130a;
a second, second dielectric layer 130a; and
a third, second dielectric layer 130a; and
the one or more second air gaps 130b (Peng, para.0018) comprise:
a first, second air gap 130b (wherein the first, second air gap is the bottom air gap in Fig.33 of Peng) between the first, second dielectric layer and the second, second dielectric layer; and
a second, second air gap 130b (wherein the second, second air gap is the middle air gap in Fig.33 of Peng) between the second, second dielectric layer and the third, second dielectric layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891