DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 17, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by PARK et al. (US 20160336327 A1, hereinafter Park)
With regards to claim 1, Park discloses an integrated circuit (IC) device, (FIGS. 5-14B) comprising:
a support; (substrate 200)
a first circuit (circuit of left region CLR, see FIGS. 5, 6, and 14) over a first portion (left region CLR) of the support;
a second circuit (circuit of left region CLR, see FIGS. 5, 6, and 14) over a second portion (right region CLR) of the support;
a scribe line (scribe line SCL) between the first circuit and the second circuit; and
one or more electrical traces (at least plate electrode 270 of devices 220a) extending over the scribe line. (See FIGS. 5 and 14B)
With regards to claim 2, Park discloses the IC device according to claim 1, wherein the scribe line is between at least a portion of the one or more electrical traces and the support, and wherein the one or more electrical traces couple one or more components of the first circuit with one or more components of the second circuit. (see FIGS. 5 and 14B, showing the scribe line SCL between the electrode 270 and the substrate 200, and electrode 270 physically couples the components)
With regards to claim 3, Park discloses the IC device according to claim 1, wherein:
the first circuit comprises transistors (left transistors comprising left bit lines 240 and active regions 205) of a first transistor architecture,
the second circuit comprises transistors (right transistors comprising right bit lines 240 and active regions 205) of a second transistor architecture, and
the first transistor architecture and the second transistor architecture are different transistor architectures of a set of a recess channel array transistor (RCAT) architecture, (See FIG. 14B, showing the recessed transistors) a fin-based transistor architecture, a nanoribbon-based transistor architecture, a nanosheet-based transistor architecture, and a nanowire-based transistor architecture.
With regards to claim 4, Park discloses the IC device according to claim 3, further comprising one or more layers of capacitors (capacitors CAP) over the first circuit, wherein individual transistors of the first circuit are coupled to individual capacitors of the one or more layers of capacitors forming a plurality of memory units. (See FIG. 14B)
With regards to claim 5, Park discloses the IC device according to claim 4, wherein an individual memory unit of the plurality of memory units includes one transistor of the transistors of the first circuit and a plurality of capacitors of the one or more layers of capacitors. (See FIG,. 14B, showing the multiple capacitors attached to the transistors)
With regards to claim 17, Park discloses an integrated circuit (IC) device, (FIGS. 5-14B) comprising:
a support; (substrate 200)
a memory array, comprising a first circuit (circuit of left region CLR, see FIGS. 5, 6, and 14) over a first portion (left region CLR) of the support and one or more layers of capacitors (left capacitors CAP) over the first circuit,
wherein the first circuit includes transistors of a first transistor architecture, (left transistors comprising left bit lines 240 and active regions 205) and
wherein an individual memory unit of the memory array includes one of the transistors of the first circuit coupled to one or more capacitors of the one or more layers of capacitors; (see FIG. 14B) and
a second circuit (circuit of left region CLR, see FIGS. 5, 6, and 14) over a second portion (right region CLR) of the support;
wherein the second circuit includes transistors of a second transistor architecture. (right transistors comprising right bit lines 240 and active regions 205, see FIG. 14B)
With regards to claim 19, Park discloses an integrated circuit (IC) device, comprising:
a support; (substrate 200)
a first memory array (memory array of left region CLR, see FIGS. 5, 6, and 14) over a first portion of the support; and
a second memory array (memory array of right region CLR, see FIGS. 5, 6, and 14) over a second portion of the support,
wherein the first memory array includes memory units of a first memory architecture, and the second memory array includes memory units of a second memory architecture. (see FIG. 14B, showing the memory architecture)
Allowable Subject Matter
Claims 6-16, 18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the cited references teach or suggest, either alone or in combination, at least “…includes a transistor Ti1 and N hysteretic capacitors coupled to the transistor Tij, wherein a capacitor CAPk is one of the N hysteretic capacitors where k is an integer between 1 and N, and a plateline PLk is a plateline of the P platelines that is coupled to the capacitor CAPk of the memory unit MUi; that is coupled to the bitline BLj.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. YANG et al (US 20220293546 A1) – Device having interconnects 108 in the scribe region 12.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812