DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/21/2022 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract and title are consistent with the requirements set forth in the MPEP 608.01(b) and 606, respectively.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation " the metal level" in line 3. There is insufficient antecedent basis for this limitation in the claim because there is no previous mention of a metal level in claim 1. For examination purposes, “the metal lever” is being interpreted as “the metal layer.” Appropriate correction is required. Claims 2-16 are also rejected under 112(b) for further limiting and dependent on indefinite claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-5 and 7-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seta et al. US PGPub. 2001/0029105. Regarding claim 1, Seta teaches a semiconductor device (fig. 16) [0066], comprising: a first via (68b examiner’s fig. 1; fig. 16) [0121] in a metal layer (65, fig. 16) [0121], wherein the first via (68b) is a single damascene structure (SDS, examiner’s fig. 1); and a second via (63’b, examiner’s fig. 1) [0121] in the metal level (65), wherein the second via (63’b) is a dual damascene structure (DDS, examiner’s fig. 1) [0119] (Seta et al., fig. 16). The metal layer (65) is a metallization level/layer formed of dielectric layer with metal layers/wirings [0121] as consistent with the definition of a metal layer in [0035] of the specification of the instant application.
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Examiner’s Fig. 1
Regarding claim 2, Seta teaches the semiconductor device of claim 1, further comprising: a first metal line (68t, examiner’s fig. 1) [0121] in the metal layer (65) wherein the first metal line (68t) is a single damascene structure (SDS, examiner’s fig. 1); and a second metal line (63’t, examiner’s fig. 1) [0121] in the metal layer (65), wherein the second metal line (63’t) is a dual damascene structure (DDS, examiner’s fig. 1)[0119] (Seta et al., fig. 16). Regarding claim 4, Seta teaches the semiconductor device of claim 1, wherein the first via (68b) is used to carry signals [0121] because the first via (68b) is made of conductive/metallic material [0121] that are capable of carrying signals (Seta et al., [0121]). Even further, a claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II). In this case, the required structural limitation for carrying a signal is simply a metal wiring/via (68b) which Set teaches.
Regarding claim 5, Seta teaches the semiconductor device of claim 1, wherein the second via (63’b) is used to carry power because the second via (63’b) is made of conductive/metallic material [0121] that are capable of carrying signals and power (Seta et al., [0121]). Even further, a claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II). In this case, the required structural limitation for carrying power is simply a metal wiring/via (63’b) which Set teaches. Regarding claim 7, Seta teaches the semiconductor device of claim 2, wherein the first metal line (68t) is used to carry signals [0121] because the first metal line (68t) is made of conductive/metallic material [0121] that are capable of carrying signals (Seta et al., [0121]). Even further, a claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II). In this case, the required structural limitation for carrying a signal is simply a metal wiring (68t) which Set teaches.
Regarding claim 8, Seta teaches the semiconductor device of claim 2, wherein the second metal line (63’t) is used to carry power because the second metal line (63’t) is made of conductive/metallic material [0121] that are capable of carrying signals and power (Seta et al., [0121]). Even further, a claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II). In this case, the required structural limitation for carrying power is simply a metal wiring/via (63’b) which Set teaches. Regarding claim 9, Seta teaches the semiconductor device of claim 2, wherein a liner (69, fig. 16) [0121] is formed along a bottom surface of the first metal line (68t), and further wherein the liner (69) is in contact with a top surface of the first via (68b) (Seta et al., fig. 16). Regarding claim 10, Seta teaches the semiconductor device of claim 2, wherein a liner (64, fig. 16) [0120] is not formed (see examiner’s fig. 1) along a bottom surface of the second metal line (63’t), and further wherein a bottom surface of the second metal line (63’t) is in contact with a top surface of the second via (63’b) (Seta et al., fig. 16).
Regarding claim 11, Seta teaches the semiconductor device of claim 1, wherein the first via (68b) (Al, [0121]) and the second via (63’b) [Al, [0120]) are formed from similar materials (Seta et al., [0120]-[0121]).
Regarding claim 12, Seta teaches the semiconductor device of claim 1, wherein the first via (68b) (Al, [0121]) and the second via (63’b) (Ag, [0120]) are formed from different materials (Seta et al., [0120]-[0121]).
Regarding claim 13, Seta teaches the semiconductor device of claim 2, wherein the first via (68b) (Al, [0121]) and the first metal line (68t) (Al, [0121]) are formed from similar materials (Seta et al., [0120]-[0121]).
Regarding claim 14, Seta teaches the semiconductor device of claim 2, wherein the first via (68b which is also 63, fig. 15B) (Ag, [0120]) and the first metal line (68t/68, fig. 16) (Al, [0121]) are formed from different materials (Seta et al., [0120]-[0121]).
Regarding claim 15, Seta teaches the semiconductor device of claim 2, wherein a bottom surface of the first via (68b) and a bottom surface of the second via (63’b) are at similar depths (both bottom surfaces at the same level in contact with 53, fig. 16) within the metal layer (65) (Seta et al., fig. 16).
Regarding claim 16, Seta teaches the semiconductor device of claim 2, wherein a bottom surface of the first via (68b) and a bottom surface of the second via (63’b) are at different depths (depth interpreted as the height from the top to the bottom of the vias, 63/68b being longer and hence deeper that 63’b) within the metal layer (65) (Seta et al., fig. 16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Seta et al. US PGPub. 2001/0029105 in view of Kim et al. US PGPub. 2024/0072117. Regarding claim 17, Seta teaches a method (fig. 12A-16) of forming a semiconductor device (fig. 16) [0066], comprising: forming a first via (68b/63, examiner’s fig. 1; fig. 16) [0121] in a metal layer (65, fig. 16) [0121]; and forming a second via (63’b, examiner’s fig. 1) [0121] in the metal layer (65) using a dual damascene process (DDS, examiner’s fig. 1) [0119] (Seta et al., fig. 16). The metal layer (65) is a metallization level/layer formed of dielectric layer with metal layers/wirings [0121] as consistent with the definition of a metal layer in [0035] of the specification of the instant application. But Seta fails to explicitly disclose that the first via (68b/63) is formed using single damascene process. However, Kim teaches a method of forming a semiconductor device (fig. 5A) [0026], comprising: forming a first via (VI1, fig. 5A) [0082] in a metal layer (M1, fig. 5A) [0082] using a single damascene process [0083]; and forming a second via (VI2, fig. 5A) [0085] in another metal layer (M2, fig. 5A) [0085] using a dual damascene process [0085] (Kim et al., 5A). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to use a single damascene process for forming the first via of Seta as taught by Kim because single damascene process is well known in the art and such process is art recognized and suitable for the intended purpose of forming interconnect lines and vias with reduced resistance of power interconnection lines and improved characteristics of the semiconductor device (Kim et al., [0087]) (see MPEP 2144.07).
Regarding claim 18, Seta in view of Kim teaches the method of claim 17, further comprising: forming a first metal line (M1_I, fig. 5A) [0083] in the metal layer (M1) using a single damascene process [0083]; and forming a second metal line (M2_I, fig. 5A) [0083] in the metal layer (M2) using a dual damascene process [0085] (Kim et al., [0083] and [0085]).
Regarding claim 19, Seta in view of Kim teaches the method of claim 18, wherein forming the first via (63/68b, fig. 13A-13B) in the metal layer (65) includes: forming a first via opening (61, fig. 13A) [0119] in a first dielectric layer (54, fig.13A) [0114]; depositing a first metal liner (64, fig. 14B) [0120] along a sidewall and bottom surface of the first via opening (61) (Fig. 13A-13B); and filling a remainder of the first via opening (61) with a metal (63, fig. 13B) (Seta et al., fig. 13A-13B).
Allowable Subject Matter
Claims 3 and 6 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a semiconductor device wherein “the first via is narrower than the second via” as recited in claim 3 in combination with the limitation wherein “the first via is a single damascene structure” and “the second via is a dual damascene structure” as recited in claim 1; and a semiconductor device wherein “the first metal line is narrower than the second metal line” as recited in claim 6 in combination with the limitation wherein “the first metal line is a single damascene structure” and “the second metal line is a dual damascene structure” as recited in claim 2.
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a method wherein “forming the first metal line, the second metal line, and the second via in the metal layer includes: depositing a second dielectric layer; simultaneously forming a first line opening and a second line opening in the second dielectric layer; forming a second via opening in the first dielectric layer after forming the second line opening; depositing a second metal liner along a sidewall and bottom surface of the first line opening, along a sidewall of the second line opening, and along a sidewall and a bottom surface of the second via opening; and filling a remainder of the first line opening and the second line opening with the metal” as recited in claim 20 in combination with the rest of the limitation of claim 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm..
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892