Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3, 6 and 9 rejected 35 U.S.C. 103 as being unpatentable over Lee (U.S. Patent Pub. No. 2003/0082875) of record, in view of Mariani (U.S. Patent Pub. No. 2022/0173135) of record, in view of Uchiyama (JP 2013168570, machine-translation provided).
Regarding Claim 1
FIG. 3 of Lee discloses a semiconductor structure, comprising: a substrate (40); a capacitive structure [0022], located on a top surface of the substrate and comprising a plurality of capacitors arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are each parallel to the top surface of the substrate, and the first direction intersects with the second direction; a transistor structure, located above the capacitive structure and comprising a plurality of active pillars (48) and a plurality of word lines (76), wherein ones of the plurality of active pillar is electrically connected to ones of the plurality of capacitor, and the word line extends along the second direction and continuously cover the active pillars arranged at intervals along the second direction; and a bit line structure, located above the transistor structure and comprising a plurality of bit lines (82), wherein the bit line extends along the first direction and are electrically connected to the active pillars arranged at intervals along the first direction [0027]; wherein the ones of the plurality of capacitor comprises: a bottom electrode (50), comprising a conductive pillar.
Lee is silent with respect to “a top surface of the conductive pillar is in contact with and electrically connected to the active pillar, and at least a sidewall portion of the conductive pillar comprises a silicide material doped with ions” and “a substrate isolation layer, located between the substrate and the plurality of capacitors, the substrate isolation layer includes a first substrate isolation sub-layer and a second substrate isolation sub-layer, the first substrate isolation sub-layer continuously distributed below the conductive pillar, and the second substrate isolation sub-layer covering a surface of the first substrate isolation sub-layer, wherein the first substrate isolation sub-layer was formed by oxidizing the substrate below the conductive pillar.
FIG. 23 (annotated below) of Mariani discloses a similar semiconductor structure, comprising a conductive pillar (25), wherein a top surface of the conductive pillar is in contact with and electrically connected to the active pillar (14), the conductive pillar and the active pillar form a continuous transition); and a substrate isolation layer (73, FIG. 18), located between the substrate (74) and the plurality of capacitors (42).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Mariani. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of forming an array of memory cells with vertical transistor stack ([0002] of Mariani).
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Lee as modified by Mariani is silent with respect to “the substrate isolation layer includes a first substrate isolation sub-layer and a second substrate isolation sub-layer, the first substrate isolation sub-layer continuously distributed below the conductive pillar, and the second substrate isolation sub-layer covering a surface of the first substrate isolation sub-layer, wherein the first substrate isolation sub-layer was formed by oxidizing the substrate below the conductive pillar”.
FIG. 53 of Uchiyama discloses a similar semiconductor structure, comprising a substrate isolation layer, located between the substrate (Si 101) and the plurality of capacitors (Cap), the substrate isolation layer includes a first substrate isolation sub-layer (201) and a second substrate isolation sub-layer (202), the first substrate isolation sub-layer continuously distributed below the conductive pillar (205), and the second substrate isolation sub-layer covering a surface of the first substrate isolation sub-layer, wherein the first substrate isolation sub-layer is silicon oxide [0040].
The limitation “was formed by oxidizing the substrate below the conductive pillar” is considered to be a process or functional limitation. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), MPEP 2113.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Uchiyama. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of forming an array of improving operation margin ([0033] of Uchiyama).
Regarding Claim 3
FIG. 3 of Lee discloses the bottom electrode, comprising a conductive layer (horizontal portion of 50) covering a surface of the conductive pillar; the capacitor comprises a dielectric layer (52), covering a surface of the conductive layer; and a top electrode (54), covering a surface of the dielectric layer.
Regarding Claim 6
FIG. 3 of Lee discloses the plurality of word lines are arranged at intervals along the first direction; and the transistor structure further comprises: a word line isolation layer (78), located between adjacent ones of the word lines.
Regarding Claim 9
FIG. 3 of Lee discloses the transistor structure further comprises a source electrode (60) located on a top surface of the active pillar (48); and the bit line structure further comprises: a bit line plug (80), wherein a bottom surface of the bit line plug is in contact with and connected to the source electrode, and a top surface of the bit line plug is electrically connected to the plurality of bit line (82).
Claim 5 rejected under 35 U.S.C. 103 as being unpatentable over Lee, Mariani and Uchiyama, in view of Hong (U.S. Patent Pub. No. 2022/0028859) of record, in view of Temmler (DE 102004019863) of record.
Regarding Claim 5
Lee as modified by Mariani and Uchiyama discloses Claim 3, wherein a material (204) of the conductive pillar is a silicide material (Uchiyama).
Lee as modified by Mariani and Uchiyama is silent with respect to “the dielectric layer is made of any one or more of strontium titanate, aluminum oxide, zirconium oxide, and hafnium oxide, and the conductive layer and the top electrode each are made of any one or more of titanium, ruthenium, ruthenium oxide, and titanium nitride; and a material of the conductive pillar is a silicide material comprising first dopant ions”.
FIG. 2 of Hong discloses a similar semiconductor structure, wherein the conductive layer and the top electrode each are made of any one or more of titanium, ruthenium, ruthenium oxide, and titanium nitride [0048]; and the dielectric layer is made of any one or more of strontium titanate, aluminum oxide, zirconium oxide, and hafnium oxide [0047].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Hong. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of isolating ground plate and substrate to provide highly integrated memory device including vertical transistor ([0004] of Hong).
Lee as modified by Mariani, Uchiyama and Hong is silent with respect to “a material of the conductive pillar is a silicide material comprising first dopant ions”.
Temmler discloses a similar semiconductor structure, wherein a material of the conductive pillar is a silicide material comprising first dopant ions (text: as a lower capacitor electrode, a silicide layer be used with an underlying doping layer).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Temmler. The ordinary artisan would have been motivated to modify Lee in the above manner, because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values, MPEP 2144.06.
Claim 7 rejected under 35 U.S.C. 103 as being unpatentable over Lee, Mariani and Uchiyama, in view of Wada (U.S. Patent Pub. No. 2021/0225847) of record.
Regarding Claim 7
Lee as modified by Mariani and Uchiyama discloses Claim 6. FIG. 3 of Lee further discloses each of the plurality of active pillars comprises a channel region (48), and a drain region (66) and a source region (60) that are arranged on two opposite sides of the channel region along a direction perpendicular to the top surface of the substrate; and along the first direction and the second direction [0027].
Lee as modified by Mariani and Uchiyama is silent with respect to “a width of the source region is greater than a width of the channel region, and a width of the drain region is greater than the width of the channel region”.
FIG. 5 of Wada discloses a similar semiconductor structure, wherein a width of the source region (41) is greater than a width of the channel region (501), and a width of the drain region (42) is greater than the width of the channel region.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Wada. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of reducing connection resistance and preventing malfunction ([0056] of Wada).
Claim 8 rejected under 35 U.S.C. 103 as being unpatentable over Lee, Mariani, Uchiyama and Wada, in view of Hong (U.S. Patent Pub. No. 2022/0028859) of record.
Regarding Claim 8
Lee as modified by Mariani, Uchiyama and Wada discloses Claim 7.
Lee as modified by Mariani, Uchiyama and Wada is silent with respect to “a protective layer, located between the word line isolation layer and the active pillar and covering a sidewall of the source region, and along the first direction, an edge of the protective layer is flush with an edge of the word line”.
FIG. 2 of Hong discloses a similar semiconductor structure, comprising a protective layer (171), located between the word line isolation layer and the active pillar (161) and covering a sidewall of the source region, and along the first direction, an edge of the protective layer is flush with an edge of the word line.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Hong. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of isolating ground plate and substrate to provide highly integrated memory device including vertical transistor ([0004] of Hong).
Claim 1 rejected 35 U.S.C. 103 as being unpatentable over Lee, in view of Rigano (U.S. Patent Pub. No. 2022/0173109) of record.
Regarding Claim 1
FIG. 3 of Lee discloses a semiconductor structure, comprising: a substrate (40), silicon [0021]; a capacitive structure [0022], located on a top surface of the substrate and comprising a plurality of capacitors arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are each parallel to the top surface of the substrate, and the first direction intersects with the second direction; a transistor structure, located above the capacitive structure and comprising a plurality of active pillars (48) and a plurality of word lines (76), wherein ones of the plurality of active pillar is electrically connected to ones of the plurality of capacitor, and the word line extends along the second direction and continuously cover the active pillars arranged at intervals along the second direction; and a bit line structure, located above the transistor structure and comprising a plurality of bit lines (82), wherein the bit line extends along the first direction and are electrically connected to the active pillars arranged at intervals along the first direction [0027]; wherein the ones of the plurality of capacitor comprises: a bottom electrode (50), comprising a conductive pillar.
Lee is silent with respect to “a top surface of the conductive pillar is in contact with and electrically connected to the active pillar, and at least a sidewall portion of the conductive pillar comprises a silicide material doped with ions” and “the substrate isolation layer includes a first substrate isolation sub-layer and a second substrate isolation sub-layer, the first substrate isolation sub-layer continuously distributed below the conductive pillar, and the second substrate isolation sub-layer covering a surface of the first substrate isolation sub-layer, wherein the first substrate isolation sub-layer was formed by oxidizing the substrate below the conductive pillar”.
FIG. 32 of Rigano discloses a similar semiconductor structure, comprising a conductive pillar (16), wherein a top surface of the conductive pillar is in contact with and electrically connected to the active pillar (13-17), the conductive pillar and the active pillar form a continuous transition; and a substrate isolation layer (21), located between the substrate (11) and the plurality of capacitors, the substrate isolation layer includes a first substrate isolation sub-layer (portion of 21 directly below 16) and a second substrate isolation sub-layer (portion of 21 directly below 34), the first substrate isolation sub-layer continuously distributed below the conductive pillar (16), and the second substrate isolation sub-layer covering a surface of the first substrate isolation sub-layer, wherein the first substrate isolation sub-layer is silicon oxide [0013]. The limitation “was formed by oxidizing the substrate below the conductive pillar” is considered to be a process or functional limitation. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), MPEP 2113.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Rigano. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of forming an array of vertical transistors and capacitors ([0001] of Rigano).
Pertinent Art
US 20150061069 discloses the lower electrode of the capacitor comprises silicide. Pertinent art also includes US 20220068924, 20220028862 and 20230225107.
Response to Arguments
Applicant’s arguments with respect to Claim 1 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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