Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/27/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claims 1-4, 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20200135677 A1) in view of Fan (US 7569935 B1).
Regarding claim 1, Chang discloses a circuit package (Fig. 23), comprising:
a first component (22) comprising a plurality of contact pads (42) on a first surface (See annotated figure);
a second component (71) comprising a plurality of bump interconnects (106 with 96, further citations are provided later in the claim) on a second surface (See annotated figure for surface designation),
wherein each of the plurality of bump interconnects is coupled (coupled at least by 112) to one of the plurality of contact pads on the first surface of the first component and comprises a side surface (See annotated figure for surface designation) extending in a first direction (See annotated figure for direction designation) between the first surface and the second surface (sandwiched between);
a polymer layer (110; [0031]: “formed of a polymer”; [0048]: “candidate materials”) disposed on the side surface of each of the plurality of bump interconnects (directly on) and on the second surface of the second component (“on” in the first direction), surrounding each of the plurality of bump interconnects (laterally surrounding, See annotated figure for direction designation); and
a passivation layer (98. Note: this layer is enclosing, and thereby protecting underlying structures. Thus, it is “a passivation layer”.) disposed between the polymer layer and the second surface of the second component (sandwiched between) around each the plurality of bump interconnects (laterally around, without any specific first direction configuration in relation to the bumps),
wherein each of the plurality of bump interconnects further comprises:
a contact pad (96) comprising a metal layer ([0045]: “seed metal layer…plating RDLs”) having a first diameter (lateral diameter) disposed on the second surface, the contact pad comprising a pad surface having a first area (lateral area) and the first diameter;
a pillar (106) comprising:
a base surface (See annotated figure for surface designation) coupled to the pad surface (directly coupled) in the first area (completely in the first area of 96);
the side surface extending from the pad surface (directly from, in the first direction); and
a contact end (See annotated figure for end designation); and
a solder tip (112) disposed on the contact end of the pillar and in direct contact with the one of the plurality of contact pads (indirect contact is shown); and
wherein the passivation layer does not extend onto the first area of the pad surface (passivation layer 98 is entirely laterally aside from pad 96 and does not cover any portion of pad 96 in the first direction).
Illustrated below is a marked and annotated figure of Fig. 23 of Chang.
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Chang discloses the solder tip, pillar, and contact pads on the first surface of the first component. However, Chang fails to teach the claimed “direct contact” configuration: “a solder tip disposed on the contact end of the pillar and in direct contact with the one of the plurality of contact pads”.
Fan discloses a solder tip (Fig. 2: tip 151; also shown in “tip” form during the earlier manufacturing step in Fig. 1) disposed on the contact end of the pillar (130) and in direct contact with the one of the plurality of contact pads (114).
Modifying the “solder tip” and “contact pads” configuration (of Chang) by choosing a “direct contact” configuration (of Fan) would arrive at the claimed solder tip and contact pad configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because: 1) Chang teaches a pillar/solder/pillar configuration (Fig. 23: 106/112/54); and Fan teaches a finite selection of known suitable pillar configurations (Fig. 4: pillar/solder/pillar 230/250/240; Fig. 2: pillar/solder/pad 120/151/114) that perform the same function of bonding components (components 110 and 120), and this selection overlaps the claimed configuration and the configuration disclosed by Chang. Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different solder and pad configuration. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP 2143 (1)(E).
Illustrated below are Figs. 2 and 4 of Fan.
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Regarding claim 2, Chang in view of Fan discloses the circuit package of claim 1 (Chang: Fig. 23), wherein: the polymer layer disposed on the second surface comprises a first thickness in the first direction (See annotated figure for measurement arrows); and the polymer layer disposed on the side surface of each of the plurality of bump interconnects extends farther in the first direction than the first thickness (See annotated figure for measurement arrows. Note: the gradually decreasing thickness of layer 110 includes a shape reasonably encompassed by the claim.).
Regarding claim 3, Chang in view of Fan discloses the circuit package of claim 2 (Chang: Fig. 23), wherein: the side surface of each of the plurality of bump interconnects extends in the first direction a first distance (the entire distance of the side surface) beyond the first thickness of the polymer layer ([0034]: “an intermediate height”; [0048]: “the candidate formation methods, and the candidate structures of protection layer 60”); and the polymer layer disposed on the side surface extends in the first direction at least half of the first distance ([0034]: “Ratio H2/H1 may be equal to 1.0, or in the range between 0.5 and about 1.0”).
Regarding claim 4, Chang in view of Fan discloses the circuit package of claim 1 (Chang: Fig. 23), wherein the polymer layer comprises a polyimide ([0031]: “polyimide”).
Regarding claim 9, Chang in view of Fan discloses the circuit package of claim 1 (Chang: Fig. 23), wherein, in each of the plurality of bump interconnects, the polymer layer is disposed directly on a second area of the pad surface of the contact pad (See annotated figure for area designation, layer 110 is directly on this area of pad 96) around the first area and not directly between the base surface and the contact pad in the first direction (polymer layer 110 is only laterally aside the base surface of 106).
Regarding claim 10, Chang in view of Fan discloses the circuit package of claim 1 (Chang: Fig. 23), wherein, in each of the plurality of bump interconnects, the passivation layer is not disposed directly between the polymer layer and a second area of the pad surface of the contact pad around the first area (See annotated figure for area designation, no portion of layer 98 is sandwiched between polymer 110 and the area of 96).
Regarding claim 15, Chang in view of Fan discloses the circuit package of claim 1 (Chang: Fig. 23), wherein: a first one of the first component and the second component comprises a semiconductor die (mapping “a semiconductor die” here to the first component; [0015]: “includes semiconductor substrate”; [0038]: “dies”); and the second one of the first component and the second component comprises one of a semiconductor die, an interposer, and a package substrate (mapping “a semiconductor die” here to the second component; [0040]: “a semiconductor substrate”; [0041]: “dies”).
Regarding claim 16, Chang in view of Fan discloses the circuit package of claim 1 (Chang: Fig. 23), wherein the plurality of bump interconnects comprise controller collapse chip connect (C4) bumps (the bump interconnects illustrated in the prior art are consistent with Applicant’s definition of C4 bumps in [0057] and Figs. 10-11 of the disclosure).
Regarding claim 17, Chang in view of Fan discloses the circuit package of claim 1 (Chang: Fig. 23), wherein the plurality of bump interconnects comprise a two-dimensional array of bump interconnects (at least a 1x2 array is illustrated with a 1-to-1 correspondence to pads 42; [0029]: “arranged as an array or allocated in other repeated patterns”).
Regarding claim 18, Chang in view of Fan discloses the circuit package of claim 1 (Chang: Fig. 23) integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter (selecting a computer; [0041]: “Central Computing Unit”).
Regarding independent claim 19, Chang discloses a method of fabricating a circuit package (Fig. 23), comprising:
forming a first component (22) comprising a plurality of contact pads (42) on a first surface (See annotated figure);
forming a second component (71) comprising a plurality of bump interconnects (106 with 96, further citations are provided later in the claim) on a second surface (See annotated figure for surface designation),
wherein each of the plurality of bump interconnects couples (couples at least by 112) to one of the plurality of contact pads on the first surface and comprises a side surface (See annotated figure for surface designation) extending in a first direction (See annotated figure for direction designation) between the first surface and the second surface (sandwiched between);
forming a polymer layer (110, [0031]: “formed of a polymer”; [0048]: “candidate materials”) disposed on the side surface of each of the plurality of bump interconnects (directly on) and on the second surface of the second component (“on” in the first direction), surrounding each of the plurality of bump interconnects (laterally surrounding, See annotated figure for direction designation); and
forming a passivation layer (98. Note: this layer is enclosing, and thereby protecting underlying structures. Thus, it is “a passivation layer”.) between the polymer layer and the second surface of the second component (sandwiched between) around each the plurality of bump interconnects (laterally around, without any specific first direction configuration in relation to the bumps),
wherein each of the plurality of bump interconnects further comprises:
a contact pad (96) comprising a metal layer ([0045]: “seed metal layer…plating RDLs”) having a first diameter (lateral diameter) on the second surface and comprising a pad surface having a first area (lateral area) and the first diameter;
a pillar (106) comprising:
a base surface (See annotated figure for surface designation) coupled to the pad surface (directly coupled) in the first area (completely in the first area of 96);
the side surface extending from the pad surface (directly from, in the first direction); and
a contact end (See annotated figure for end designation); and
a solder tip (112) disposed on the contact end of the pillar and in direct contact with the one of the plurality of contact pads (indirect contact is shown); and
wherein the passivation layer does not extend onto the first area of the pad surface (passivation layer 98 is entirely laterally aside from pad 96 and does not cover any portion of pad 96 in the first direction).
Chang discloses the solder tip, pillar, and contact pads on the first surface of the first component. However, Chang fails to teach the claimed “direct contact” configuration: “a solder tip disposed on the contact end of the pillar and in direct contact with the one of the plurality of contact pads”.
Fan discloses a solder tip (Fig. 2: tip 151; also shown in “tip” form during the earlier manufacturing step in Fig. 1) disposed on the contact end of the pillar (130) and in direct contact with the one of the plurality of contact pads (114).
Modifying the “solder tip” and “contact pads” configuration (of Chang) by choosing a “direct contact” configuration (of Fan) would arrive at the claimed solder tip and contact pad configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because: 1) Chang teaches a pillar/solder/pillar configuration (Fig. 23: 106/112/54); and Fan teaches a finite selection of known suitable pillar configurations (Fig. 4: pillar/solder/pillar 230/250/240; Fig. 2: pillar/solder/pad 120/151/114) that perform the same function of bonding components (components 110 and 120), and this selection overlaps the claimed configuration and the configuration disclosed by Chang. Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different solder and pad configuration. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP 2143 (1)(E).
Regarding claim 20, Chang in view of Fan discloses the method of claim 19 (Chang: Fig. 23), further comprising: employing thermal compression bonding to couple the plurality of bump interconnects on the second component to the plurality of contact pads on the first component ([0049]: “a reflow process”. Note: A reflow process necessarily includes a thermal component to wet the solder, and a compression component to bring 22 and 71 towards each other, thus, producing the resultant bulged 112 of Fig. 23).
Regarding claim 21, Chang in view of Fan discloses the method of claim 19 (Chang: Fig. 23), wherein forming the polymer layer further comprises: spin-coating the polymer layer ([0036]: “spin-on coating”; [0048]: “the formation method, and the structure of protection layer 110 may be selected from the candidate materials, the candidate formation methods, and the candidate structures of protection layer 60”) onto the second surface of the second component (“on” in the first direction) and the side surface (directly on) and an end surface of each of the plurality of bump interconnects (as shown in the method step of Fig. 7, which shows 60 completely covering all exposed surfaces); and etching the polymer layer from the end surface of each of the plurality of bump interconnects (as shown in the method step of Fig. 9; [0037]: “portions…are removed”).
Regarding independent claim 22, Chang discloses a semiconductor die (Fig. 23: 71) configured to be coupled in a circuit package (the package includes at least the collection of 22 and 71), the semiconductor die comprising:
a plurality of bump interconnects (106 with 96, further citations are provided later in the claim) on a surface of the semiconductor die (See annotated figure for surface designation), wherein:
each of the plurality of bump interconnects is configured to couple to a corresponding contact pad (42) on a surface (See annotated figure) of a circuit component (22) of the circuit package; and
each of the plurality of bump interconnects comprises a side surface (See annotated figure for surface designation) extending orthogonal to the surface of the semiconductor die (annotated as “First Direction”, See annotated figure for direction designation);
a polymer layer (110, [0031]: “formed of a polymer”; [0048]: “candidate materials”) disposed on the surface of the semiconductor die (“on” in the first direction) and on the side surface of each of the plurality of bump interconnects (directly on), surrounding each of the plurality of bump interconnects (laterally surrounding, See annotated figure for direction designation); and
a passivation layer (98. Note: this layer is enclosing, and thereby protecting underlying structures. Thus, it is “a passivation layer”.) disposed around each the plurality of bump interconnects (laterally around, without any specific first direction configuration in relation to the bumps),
wherein each of the plurality of bump interconnects further comprises:
a contact pad (96) comprising a metal layer ([0045]: “seed metal layer…plating RDLs”) having a first diameter (lateral diameter) disposed on the surface of the semiconductor die and comprising a pad surface having a first area (lateral area) and the first diameter;
a pillar (106) comprising:
a base surface (See annotated figure for surface designation) coupled (directly coupled) to the first area of the pad surface (completely in the first area of 96);
the side surface extending from the pad surface of the contact pad (directly from, in the first direction); and
a contact end (See annotated figure for end designation); and
a solder tip (112) disposed on the contact end of the pillar and in direct contact with the corresponding contact pad (indirect contact is shown); and
wherein the passivation layer does not extend onto the first area of the pad surface (passivation layer 98 is entirely laterally aside from pad 96 and does not cover any portion of pad 96 in the first direction).
Chang discloses the solder tip, pillar, and a contact pad on the surface of the semiconductor die. However, Chang fails to teach the claimed “direct contact” configuration: “a solder tip disposed on the contact end of the pillar and in direct contact with the corresponding contact pad”.
Fan discloses a solder tip (Fig. 2: tip 151; also shown in “tip” form during the earlier manufacturing step in Fig. 1) disposed on the contact end of the pillar (130) and in direct contact with the corresponding contact pad (114).
Modifying the “solder tip” and “contact pads” configuration (of Chang) by choosing a “direct contact” configuration (of Fan) would arrive at the claimed solder tip and contact pad configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because: 1) Chang teaches a pillar/solder/pillar configuration (Fig. 23: 106/112/54); and Fan teaches a finite selection of known suitable pillar configurations (Fig. 4: pillar/solder/pillar 230/250/240; Fig. 2: pillar/solder/pad 120/151/114) that perform the same function of bonding components (components 110 and 120), and this selection overlaps the claimed configuration and the configuration disclosed by Chang. Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different solder and pad configuration. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP 2143 (1)(E).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chang and Fan as applied to claim 4 above, and further in view of Lin (US 20130069225 A1)
Regarding claim 5, Chang in view of Fan discloses the circuit package of claim 4 (Chang: Fig. 23), however, fails to teach “wherein the polyimide does not comprise a photosensitive polymer” because Chang teaches the polyimide being photosensitive ([0037]: “photo resist”).
Lin discloses a polyimide in the same field of endeavor (170; [0048]: “polyimide”), wherein the polyimide is photosensitive, or does not comprise a photosensitive polymer ([0049]: “developing process” and “blanket etched”, respectively). Modifying the polyimide of Chang, by producing the same resultant structure using the alternative non-photosensitive polyimide method of Lin would arrive at the claimed polyimide configuration.
Since Lin and Chang in view of Fan each teach polyimide firstly conformally covering an entirety of a second component (Chang: as shown in Fig. 7; Lin: Fig. 3h: 170 covers 158 and 122); and secondly being removed from uppermost portions of bump interconnects (Chang: Fig. 9: removed from 56; Lin: 170 becoming 180 when removed from 158), a person having ordinary skill in the art before the effective filing date would have readily recognized the finite number of predictable solutions for polyimide configurations. These predictable solutions include photosensitive and non-photosensitive configurations as these may be chosen from a finite number of identified, predictable solutions useful for producing the same resultant patterned polyimide (Lin: [0037]). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation, the resultant polyimide is a patterned polyimide. Absent unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date to try using a different polyimide configuration. Thus, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1385 (Supreme Court 2007) (KSR). MPEP 2143 (1)(E).
Regarding claim 6, Chang in view of Fan and Lin discloses the circuit package of claim 5 (Chang: Fig. 23), further comprising an organic underfill (114; [0050]: “a polymer”) on the polymer layer between the first component and the second component around each of the plurality of bump interconnects.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chang and Fan as applied to claim 1 above, and further in view of Lee (US 20210225708 A1).
Regarding claim 13, Chang in view of Fan discloses the circuit package of claim 1 (Chang: Fig. 23), wherein:
each of the plurality of bump interconnects comprises a center axis extending in a longitudinal direction of the bump interconnect (a line running centrally through 106 in the first direction, See dashed reference line); and
a center-to-center pitch distance (See annotated figure for measurement markings) from a center axis of a first bump interconnect to a center axis of a nearest adjacent bump interconnect of the plurality of bump interconnects is between 20 and 30 microns.
Chang fails to teach specific range endpoints for the center-to-center pitch distance. Thus, Chang in view of Fan fails to teach “a center-to-center pitch distance […] is between 20 and 30 microns”.
Lee discloses bump interconnects (Fig. 6A: 34 including 32 and 33 therein; [0188]: “same specifications as…Fig. 1E”), and further teaches a known suitable range for a center-to-center pitch distance is between 20 and 30 microns ([0126]: “from 20 to 150 micrometers”).
Chang teaches having contact pads with high density (and necessarily the corresponding bump interconnects) is a design incentive that would enable packages with reduced size and increased function ([0001]: “smaller…more functions”). Lee teaches the pitch range is high density ([0013]: “fine pitch metal pads” is referring to analogous structures sharing the same specification; [0176]: “same specifications as…Fig. 1E”, thus each structure includes high density pitch range). A person of ordinary skill in the art before the effective filing date could have implemented the pitch range of Lee for the pitch of Chang because each pitch is high density. One of ordinary skill in the art before the effective filing date would have been motivated to include the pitch range of Lee with the bumps of Chang, because it would enable packages with reduced size and increased function (Chang: [0001]: “smaller…more functions”). Doing so would arrive at the claimed pitch configuration and would have had predictable results because each pitch (of Chang and Lee) is a high density pitch applied to similar bump interconnects. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have “a center-to-center pitch distance from a center axis of a first bump interconnect to a center axis of a nearest adjacent bump interconnect of the plurality of bump interconnects is between 20 and 30 microns” because it would enable small packages with increased function. MPEP 2143(I)(F).
Regarding claim 14, Chang in view of Fan and Lee discloses a circuit package (Chang: Fig. 23), wherein the center-to-center pitch distance is 25 microns (25 microns is squarely within the range of Lee; [0126]: “from 20 to 150 micrometers”).
Response to Arguments
Applicant's arguments filed 5/27/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claims 1, 19, and 22 that “Chang does not disclose or suggest “a solder tip disposed on the contact end of the pillar and in direct contact with the one of the plurality of contact pads” as recited in amended claim 1”. Remarks at pg. 10.
Examiner’s reply:
Applicant’s arguments, see pg. 10, filed 5/27/2026, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the newly found secondary reference (Fan), incorporated in the instant Office action as necessitated by claim amendment.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US 20210305114 A1) discloses a passivation layer (Fig. 3A: 109) disposed between the polymer layer (115) and the second surface of the second component around each the plurality of bump interconnects, wherein each of the plurality of bump interconnects further comprises: a pillar (pillar 118a): wherein the passivation layer does not extend onto the first area (an entirety of the exposed surface of pad 106) of the pad surface.
Lee discloses a pillar (Fig. 3A: pillar 118a): wherein the passivation layer (115) does not extend onto the first area (a portion of the exposed surface of pad 106) of the pad surface.
Lee discloses a pillar (Fig. 3B: pillar 118b): wherein the passivation layer (115) does not extend onto the first area (an entirety of the exposed surface of pad 106) of the pad surface.
Chen (US 20230082120 A1) discloses a pillar (Fig. 3: pillar 304a): wherein the passivation layer (105) does not extend onto the first area (a portion of the exposed surface of pad 107a) of the pad surface.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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