DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 35 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/26/2026 has been entered.
Remarks
The 02/26/2026 amendments of claims 1 and 16 have been noted and entered.
The 02/26/2026 addition of new claims 24-25 have been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 6-9, filed 02/26/2026, with respect to the rejection(s) of claim(s) 1, 5-9 and 13-23 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Hoentschel et al, US 20130095620 A1 (Hoentschel).
New Grounds of Rejection
New grounds of rejection, prior art reference Hoentschel et al, US 20130095620 A1 (Hoentschel) appears below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1, 5-9 and 13-25 are rejected under 35 U.S.C. 103 as being unpatentable over Abe et al, JP 2008244094 A (Abe) in view of Clifton et al, US 20200273991 A1 (Clifton) in further view of Hoentschel et al, US 20130095620 A1 (Hoentschel).
Regarding claim 1; Abe teaches an RF MOSFET (Abe: Annotated Fig (1) shared in this OA: 1), comprising
respective pluralities of gate fingers (12),
source fingers (14), and
drain fingers (13) formed on a semiconductor structure (4),
the gate fingers (12) being spaced apart from each other along a first direction (Y-direction), extending in a second, orthogonal direction (Z-direction), and electrically connected to one another through a gate mandrel (12A) that is electrically connected to a gate contact (7),
the source fingers (14) being spaced apart from each other along the first direction (Y-direction), extending in the second direction (Z-direction), and electrically connected to one another through a source mandrel (14A) that is electrically connected to a respective source contact (6), and
the drain fingers (13) being spaced apart from each other along the first direction (Y-direction), extending in the second direction (Z-direction), and electrically connected to one another through a drain mandrel (13A) that is electrically connected to a respective drain contact (5),
the respective source (14), gate (12), and drain (13) fingers further being interdigitated so that each gate finger (12) extends in the first direction (Y-direction) between a pair of adjacent source (14) and drain fingers (13),
the RF MOSFET electrically organized as a plurality of unit cell transistors (1) electrically connected with one another and adjacent unit cell transistors (1) of the RF MOSFET being separated from one another by a dummy gate (17) and trench (3) that extends into the semiconductor structure (4), wherein the semiconductor structure (4) includes a semiconductor substrate (4),
a buried stressor layer disposed over the semiconductor substrate, a BOX layer disposed over buried stressor layer, and a fully depleted semiconductor layer disposed over the BOX layer, and
a pitch of adjacent unit cell transistors of the RF MOSFET is approximately double a contacted-poly pitch (CPP) which would exist absent the dummy gate and trench.
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Abe does not teach a buried stressor layer disposed over the semiconductor substrate, a BOX layer disposed over buried stressor layer, and a fully depleted semiconductor layer disposed over the BOX layer.
However, Clifton teaches a buried stressor layer (Clifton: Fig (2): 14) disposed over the semiconductor substrate (12), a BOX layer (18) disposed over buried stressor layer (14), and a fully depleted semiconductor layer (20) disposed over the BOX layer (18).
Abe and Clifton are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Abe by using the multilayer structure disclosed in Clifton to improve the conductivity of the device leading to a more efficient and faster operating device.
Abe in view of Clifton does not teach a pitch of adjacent unit cell transistors of the RF MOSFET is approximately double a contacted-poly pitch (CPP) which would exist absent the dummy gate and trench.
However, Hoentschel teaches a pitch of adjacent unit cell transistors (Hoentschel: Fig (1H): 14C) of the RF MOSFET is approximately double a contacted-poly pitch (CPP) which would exist absent the dummy gate and trench ([0007]: “… and such transistors may be formed with a gate pitch that ranges from about 160-190 nm, depending upon the particular application." which matches the range of pitches in the instant application.).
Abe in view of Clifton and Hoentschel are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Abe in view of Clifton by constructing the pitches between the adjacent gates as disclosed in Hoentschel to ensure proper isolation of the gates leading to a better performing device.
Regarding claim 5; Abe in view of Clifton in further view of Hoentschel teaches all the limitations of the RF MOSFET of claim 1.
Further, Abe teaches wherein the dummy gates (Abe: Annotated Fig (1) shared in this OA: 17) are not electrically connected to the gate mandrel (12A).
Regarding claim 6; Abe in view of Clifton in further view of Hoentschel teaches all the limitations of the RF MOSFET of claim 1.
Further, Abe teaches wherein the gate (Abe: Annotated Fig (1) shared in this OA: 12), source (14) and drain (13) fingers are each made of a conductive material
Regarding claim 7; Abe in view of Clifton in further view of Hoentschel teaches all the limitations of the RF MOSFET of claim 1.
Further, Abe teaches wherein each unit cell transistor (Abe: Annotated Fig (1) shared in this OA: 1) includes one of the gate fingers (12), one of the source fingers (14), and one of the drain fingers (13), the included source (14) and drain (13) fingers being on opposed sides of the included gate finger (12), and a portion of the semiconductor structure (4) that underlies the included gate (12), source (14) and drain (13) fingers.
Regarding claim 8; Abe in view of Clifton in further view of Hoentschel teaches all the limitations of the RF MOSFET of claim 1.
Further, Abe teaches wherein the source fingers (Abe: Annotated Fig (1) shared in this OA: 14) and drain fingers (13) comprise elevated epitaxial silicon source/drain regions (6, 5) and a source/drain of each unit cell (1) transistor is located inside the included portion of the semiconductor structure (4) that underlies an adjacent a channel region (region below 7) below a respective included gate finger (12).
Regarding claim 9; Abe in view of Clifton in further view of Hoentschel teaches all the limitations of the RF MOSFET of claim 1.
However, Abe does not teach wherein the buried stressor layer comprises SiGe.
Clifton teaches wherein the buried stressor layer (Clifton: Fig (2): 14) comprises SiGe ([0027]: “…the BS layer 14 may be silicon germanium”).
Abe and Clifton are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Abe by using the buried stressor layer comprised of SiGe disclosed in Clifton to improve the conductivity of the device leading to a more efficient device with better performance.
Regarding claim 13; Abe in view of Clifton in further view of Hoentschel teaches all the limitations of the RF MOSFET of claim 1.
However, Abe does not teach wherein the trenches extend through the fully depleted semiconductor layer, the BOX layer, the buried stressor layer, and into the substrate.
Clifton teaches wherein the trenches (Clifton: Fig (2): 22) extend through the fully depleted semiconductor layer (20), the BOX layer (18), the buried stressor layer (14), and into the substrate (12).
Abe and Clifton are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Abe by using the trenches disclosed in Clifton to enhance the isolation between the different transistor units lowering the chances of interference between the units thus leading to a more reliable performance of the device.
Regarding claim 14; Abe in view of Clifton in further view of Hoentschel teaches all the limitations of the RF MOSFET of claim 1.
However, Abe does not teach wherein the fully depleted semiconductor layer is a silicon layer.
Clifton teaches wherein the fully depleted (Clifton: Fig (2): 20) semiconductor layer is a silicon layer ([0027]: “… a thin layer of silicon 20…”).
Abe and Clifton are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Abe by using silicon for the fully depleted semiconductor layer disclosed in Clifton to improve the conductivity of the device which leads to more efficient performance.
Regarding claim 15; Abe in view of Clifton in further view of Hoentschel teaches all the limitations of the RF MOSFET of claim 13.
However, Abe does not teach wherein the fully depleted semiconductor layer is a silicon layer.
Clifton teaches wherein the fully depleted (Clifton: Fig (2): 20) semiconductor layer is a silicon layer ([0027]: “… a thin layer of silicon 20…”).
Abe and Clifton are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Abe by using silicon for the fully depleted semiconductor layer disclosed in Clifton to improve the conductivity of the device which leads to more efficient performance.
Regarding claim 16; Abe teaches an RF MOSFET, comprising
respective pluralities of gate fingers (Abe: Annotated Fig (1) shared in this OA: 12),
source fingers (14), and
drain fingers (13) formed on a semiconductor structure (1),
the gate fingers (12) being spaced apart from each other along a first direction (Y-direction), extending in a second (Z-direction), orthogonal direction, and electrically connected to one another through a gate mandrel (12A) that is electrically connected to a gate contact (7),
the source fingers (14) being spaced apart from each other along the first direction (Y-direction), extending in the second direction (Z-direction), and electrically connected to one another through a source mandrel (14A) that is electrically connected to a respective source contact (6), and
the drain fingers (13) being spaced apart from each other along the first direction (Y-direction), extending in the second direction (Z-direction), and electrically connected to one another through a drain mandrel (13A) that is electrically connected to a respective drain contact (5),
the respective source (14), gate (12), and drain (13) fingers further being interdigitated so that each gate finger (12) extends in the first direction (Y-direction) between a pair of adjacent source (14) and drain (13) fingers,
the RF MOSFET electrically organized as a plurality of unit cell transistors (1) electrically connected with one another and adjacent unit cell transistors (1) of the RF MOSFET being separated from one another by a trench (3) that extends into the semiconductor structure (4), wherein the semiconductor structure (4) includes a semiconductor substrate (4),
a buried stressor layer disposed over the semiconductor substrate, a BOX layer disposed over buried stressor layer, and a fully depleted semiconductor layer disposed over the BOX layer, and
a pitch of adjacent unit cell transistors of the RF MOSFET is approximately double a contacted-poly pitch (CPP) which would exist absent the trench.
Abe does not teach a buried stressor layer disposed over the semiconductor substrate, a BOX layer disposed over buried stressor layer, and a fully depleted semiconductor layer disposed over the BOX layer.
However, Clifton teaches a buried stressor layer (Clifton: Fig (2): 14) disposed over the semiconductor substrate (12), a BOX layer (18) disposed over buried stressor layer (14), and a fully depleted semiconductor layer (20) disposed over the BOX layer (18).
Abe and Clifton are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Abe by using the multilayer structure disclosed in Clifton to improve the conductivity of the device leading to a more efficient and faster operating device.
Abe in view of Clifton does not teach a pitch of adjacent unit cell transistors of the RF MOSFET is approximately double a contacted-poly pitch (CPP) which would exist absent the trench.
However, Hoentschel teaches a pitch of adjacent unit cell transistors (Hoentschel: Fig (1H): 14C) of the RF MOSFET is approximately double a contacted-poly pitch (CPP) which would exist absent the dummy gate and trench ([0007]: “… and such transistors may be formed with a gate pitch that ranges from about 160-190 nm, depending upon the particular application." which matches the range of pitches in the instant application.).
Abe in view of Clifton and Hoentschel are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Abe in view of Clifton by constructing the pitches between the adjacent gates as disclosed in Hoentschel to ensure proper isolation of the gates leading to a better performing device.
Regarding claim 17; Abe in view of Clifton in further view of Hoentschel teaches all the limitations of the RF MOSFET of claim 16.
Further, Abe teaches wherein the gate (Abe: Annotated Fig (1) shared in this OA: 12), source (14) and drain (13) fingers are each made of a conductive material.
Regarding claim 18; Abe in view of Clifton in further view of Hoentschel teaches all the limitations of the RF MOSFET of claim 16.
Further, Abe teaches wherein each unit cell transistor (Abe: Annotated Fig (1) shared in this OA: 1) includes one of the gate fingers (12), one of the source fingers (14), and one of the drain fingers (13), the included source (14) and drain (13) fingers being on opposed sides of the included gate finger (12), and a portion of the semiconductor structure (1) that underlies the included gate (12), source (14) and drain (13) fingers.
Regarding claim 19; Abe in view of Clifton in further view of Hoentschel teaches all the limitations of the RF MOSFET of claim 16.
Further, Abe teaches wherein the source fingers (Abe: annotated Fig (1) shared in this OA: 14) and drain fingers (13) comprise elevated epitaxial silicon source/drain regions (6, 5) and a source/drain of each unit cell (1) transistor is located inside the included portion of the semiconductor structure (4) that underlies an adjacent a channel region (region below 7) below a respective included gate finger (12).
Regarding claim 20; Abe in view of Clifton in further view of Hoentschel teaches all the limitations of the RF MOSFET of claim 16.
However, Abe does not teach wherein the buried stressor layer comprises SiGe.
Clifton teaches wherein the buried stressor layer (Clifton: Fig (2): 14) comprises SiGe ([0027]: “…the BS layer 14 may be silicon germanium”).
Abe and Clifton are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Abe by using the buried stressor layer comprised of SiGe disclosed in Clifton to improve the conductivity of the device leading to a more efficient device with better performance.
Regarding claim 21; Abe in view of Clifton in further view of Hoentschel teaches all the limitations of the RF MOSFET of claim 16.
However, Abe does not teach wherein the trenches extend through the fully depleted semiconductor layer, the BOX layer, the buried stressor layer, and into the substrate.
Clifton teaches wherein the trenches (Clifton: Fig (2): 22) extend through the fully depleted semiconductor layer (20), the BOX layer (18), the buried stressor layer (14), and into the substrate (12).
Abe and Clifton are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Abe by using the trenches disclosed in Clifton to enhance the isolation between the different transistor units lowering the chances of interference between the units thus leading to a more reliable performance of the device.
Regarding claim 22; Abe in view of Clifton in further view of Hoentschel teaches all the limitations of the RF MOSFET of claim 16.
However, Abe does not teach wherein the fully depleted semiconductor layer is a silicon layer.
Clifton teaches wherein the fully depleted (Clifton: Fig (2): 20) semiconductor layer is a silicon layer ([0027]: “… a thin layer of silicon 20…”).
Abe and Clifton are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Abe by using silicon for the fully depleted semiconductor layer disclosed in Clifton to improve the conductivity of the device which leads to more efficient performance.
Regarding claim 23; Abe in view of Clifton in further view of Hoentschel teaches all the limitations of the RF MOSFET of claim 21.
However, Abe does not teach wherein the fully depleted semiconductor layer is a silicon layer.
Clifton teaches wherein the fully depleted (Clifton: Fig (2): 20) semiconductor layer is a silicon layer ([0027]: “… a thin layer of silicon 20…”).
Abe and Clifton are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Abe by using silicon for the fully depleted semiconductor layer disclosed in Clifton to improve the conductivity of the device which leads to more efficient performance.
Regarding claim 24; Abe in view of Clifton in further view of Hoentschel teaches all the limitations of the RF MOSFET of claim 1.
Abe in view of Clifton does not teach wherein the pitch of adjacent unit cell transistors of the RF MOSFET is approximately 200 nm.
Hoentschel teaches wherein the pitch of adjacent unit cell transistors (Hoentschel: Fig (1H): 14C) of the RF MOSFET is approximately 200 nm ([0007]: “… and such transistors may be formed with a gate pitch that ranges from about 160-190 nm, depending upon the particular application." which matches the range of pitches in the instant application.).
Abe in view of Clifton and Hoentschel are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Abe in view of Clifton by constructing the pitches between the adjacent gates as disclosed in Hoentschel to ensure proper isolation of the gates leading to a better performing device.
Regarding claim 25; Abe in view of Clifton in further view of Hoentschel teaches all the limitations of the RF MOSFET of claim 16.
Abe in view of Clifton does not teach wherein the pitch of adjacent unit cell transistors of the RF MOSFET is approximately 200 nm.
Hoentschel teaches wherein the pitch of adjacent unit cell transistors (Hoentschel: Fig (1H): 14C) of the RF MOSFET is approximately 200 nm ([0007]: “… and such transistors may be formed with a gate pitch that ranges from about 160-190 nm, depending upon the particular application." which matches the range of pitches in the instant application.).
Abe in view of Clifton and Hoentschel are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Abe in view of Clifton by constructing the pitches between the adjacent gates as disclosed in Hoentschel to ensure proper isolation of the gates leading to a better performing device.
Conclusion
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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