DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO ARGUMENTS
Applicant's arguments filed 2/27/2026 have been fully considered but they are not persuasive.
In response to applicant’s arguments with regard to the independent claims 1 and 24-25 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… wherein the processing circuitry is configured to download an update with support for the targeted unsupported instruction at the processor, with the instructions supported by the processor being extended based on the downloaded update. …” because Gschwind does not extend the processor’s capability after it has been shipped by downloading an update from an external source to a processor at runtime to extend its instruction set as Gschwind teaches a static, design-time hardware modification with the new instructions being built into the processor’s hardware logic; applicant's arguments have fully been considered, but are not found to be persuasive.
The examiner respectfully disagrees, and to further clarify, Gschwind does not appear to disclose a static, design-time hardware modification with the new instructions being built into the processor’s hardware logic as the examiner is uncertain where in Gschwind discloses applicant’s narrow interpretation. And as Gschwind does disclose new instruction and that update of ISA is needed for the new instruction, Gschwind would not disclose the static, design-time hardware modification and being built into the processor, as static and built in feature(s) would not be new that necessitate update.
Furthermore, considering Gschwind’s invention may be implemented as software/program code that may be executed partly on user’s computer and partly on remote computer/server ([0017]-[0024]; [0039]-[0040]; [0052]), Gschwind’s updating of ISA for supporting new instruction suggests the user’s computer would have receiving/download update from remote computer/server for supporting new instruction (i.e. the need to update ISA for new instruction suggests existing ISA on user’s computer do not support the new instruction and need to acquire new/updated ISA, wherein the new/updated ISA may be received from source outside of the user’s computer, such as the remote computer/server).
I. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-25 are rejected under 35 U.S.C. 103 as being unpatentable over WANG et al. (US Pub.: 2022/0206815) in view of Gschwind et al. (US Pub.: 2011/0296431).
As per claim 1, WANG teaches/suggests an apparatus for the instructions supported by a processor, the apparatus comprising interface circuitry and processing circuitry configured to: identify at least a part of a computer program targeting an instruction unsupported by the processor, operating, based on the targeted unsupported instruction, and execute the computer program (e.g. associated with identifying new instructions and executing the new instructions accordingly: [0037]-[0040]), wherein the processing circuitry is configured to operate with the target unsupported instruction at the processor (Fig. 3; [0037]-[0040]; and [0051]-[0062]).
WANG does not teach the apparatus configured to: operating with a pre-defined set of instructions of an Instruction Set Architecture (ISA) of the processor, extend the instructions supported by the processor, and download an update with support for unsupported instruction, with the instructions supported by the processor being extended based on the downloaded update.
Gschwind teaches/suggests an apparatus configured to: operating with a pre-defined set of instructions of an Instruction Set Architecture (ISA) of the processor, extend the instructions supported by the processor, and download an update with support for unsupported instruction, with the instructions supported by the processor being extended based on the downloaded update (e.g. associated with user’s computer updating ISA to support new instructions, wherein the updated/new ISA may be received/downloaded from remote computer/server: [0024]; [0039]-[0040]) ([0017]-[0024]; [0039]-[0040]; [0052]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Gschwind’s updating operations into WANG’s apparatus for the benefit of properly supporting new hardware instructions while improving performance of the processing architecture ([0021]; and [0024]) to obtain the invention as specified in claim 1.
As per claim 2, WANG and Gschwind teach/suggest all the claimed features of claim 1 above, where WANG and Gschwind further teach/suggest the apparatus comprising wherein extending the instructions supported by the processor comprises applying an update with support for the targeted unsupported instruction at the processor (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0017]-[0024]).
As per claim 3, WANG and Gschwind teach/suggest all the claimed features of claim 1 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein extending the instructions supported by the processor comprises applying a microcode update with support for the targeted unsupported instruction at the processor (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0017]-[0024]; [0036]).
As per claim 5, WANG and Gschwind teach/suggest all the claimed features of claim 2 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein the processing circuitry is configured to obtain the update with a secure authentication information, wherein extending the instructions supported by the processor is performed after secure authentication towards the processor (WANG, Fig. 3; [0037]-[0040]; [0051]-[0064]; and Gschwind, [0017]-[0024]; [0039]-[0040]; [0052]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as the new instruction(s) is properly executed.
As per claim 6, WANG and Gschwind teach/suggest all the claimed features of claim 5 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein the processing circuitry is configured to authenticate the update towards the processor based on cryptographic information contained in the secure authentication information (WANG, Fig. 3; [0037]-[0040]; [0051]-[0064]; and Gschwind, [0017]-[0024]; [0039]-[0040]; [0052]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as the new instruction(s) is properly executed.
As per claim 7, WANG and Gschwind teach/suggest all the claimed features of claim 1 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein extending the instructions supported by the processor is performed at runtime in preparation of the execution of the computer program (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0017]-[0024]).
As per claim 8, WANG and Gschwind teach/suggest all the claimed features of claim 1 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein extending the instructions supported by the processor is performed if the instructions supported by the processor do not allow for an optimized execution of the computer program (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0017]-[0024]).
As per claim 9, WANG and Gschwind teach/suggest all the claimed features of claim 1 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein extending the instructions supported by the processor is performed if execution of part of the computer program targeting an instruction unsupported by the set of instructions requires emulation or replacement of the instruction by two or more corresponding instructions of the set of instructions (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0017]-[0024]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as the new instruction(s) is properly executed.
As per claim 10, WANG and Gschwind teach/suggest all the claimed features of claim 1 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein extending the instructions supported by the processor adds at least one microinstruction or macroinstruction to the instructions supported by the processor (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0017]-[0024]; [0036]).
As per claim 11, WANG and Gschwind teach/suggest all the claimed features of claim 10 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein the added at least one microinstruction or macroinstruction is not publicly exposed as part of the instructions supported by the processor (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0017]-[0024]; [0036]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as the new instruction(s) is properly executed.
As per claim 12, WANG and Gschwind teach/suggest all the claimed features of claim 1 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein the computer program targeting an instruction unsupported by the set of instructions is an emulator for emulating a second ISA being different from the ISA of the processor (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0017]-[0024]; [0036]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as the new instruction(s) is properly executed.
As per claim 13, WANG and Gschwind teach/suggest all the claimed features of claim 1 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein the instruction unsupported by the set of instructions is an instruction of a second ISA being different from the ISA of the processor (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0017]-[0024]; [0036]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as the new instruction(s) is properly executed.
As per claim 14, WANG and Gschwind teach/suggest all the claimed features of claim 1 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein the computer program is based on a bytecode or an intermediate representation (IR) (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0017]-[0024]; [0036]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as the new instruction(s) is properly executed.
As per claim 15, WANG and Gschwind teach/suggest all the claimed features of claim 1 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein the processing circuitry is configured to process the computer program to identify the at least part of the computer program targeting an instruction unsupported by the set of instructions (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0017]-[0024]; [0036]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as the new instruction(s) is properly executed.
As per claim 16, WANG and Gschwind teach/suggest all the claimed features of claim 1 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein the processing circuitry is configured to monitor the execution of the program to identify at least a part of the computer program targeting an instruction unsupported by the set of instructions (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0017]-[0024]; [0036]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as the new instruction(s) is properly executed.
As per claim 17, WANG and Gschwind teach/suggest all the claimed features of claim 1 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein the processing circuitry is configured to execute a runtime or emulator, with the runtime or emulator performing the identification of the at least part of the computer program, the extending of the instructions supported by the processor and the execution of the computer program (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0017]-[0024]; [0036]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as the new instruction(s) is properly executed.
As per claim 18, WANG and Gschwind teach/suggest all the claimed features of claim 1 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein the ISA is of the processor is a Complex Instruction Set Computer (CISC)-based ISA (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0015]; [0017]-[0024]; [0036]), wherein it would have been obvious and/or well-known to one of ordinary skilled in the art to further implement CISC based architecture when properly processing the new instruction(s).
As per claim 19, WANG and Gschwind teach/suggest all the claimed features of claim 1 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein the instruction unsupported by the set of instructions is a Reduced Instruction Set Computer (RISC)-based instruction (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0015]; [0017]-[0024]; [0036]), wherein it would have been obvious and/or well-known to one of ordinary skilled in the art to further implement RISC based architecture when properly processing the new instruction(s).
As per claim 20, WANG and Gschwind teach/suggest all the claimed features of claim 19 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein the instruction unsupported by the set of instructions is Reduced Instruction Set Computer Five (RISC-V) based or ARM-based (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0015]; [0017]-[0024]; [0036]), wherein it would have been obvious and/or well-known to one of ordinary skilled in the art to further implement RISC-V/ARM based architecture when properly processing the new instruction(s).
As per claim 21, WANG and Gschwind teach/suggest all the claimed features of claim 1 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein the processor is a Central Processing Unit (CPU) (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0015]; [0017]-[0024]; [0036]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as the new instruction(s) is properly executed.
As per claim 22, WANG and Gschwind teach/suggest all the claimed features of claim 1 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein the processor is an XPU (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0015]; [0017]-[0024]; [0036]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as the new instruction(s) is properly executed.
As per claim 23, WANG and Gschwind teach/suggest all the claimed features of claim 22 above, where WANG and Gschwind further teach/suggest the apparatus comprising: wherein the XPU is one of a Central Processing Unit (CPU), Graphics Processing Unit (GPU), an Artificial Intelligence (AI) accelerator, an accelerator card and offloading circuitry (WANG, Fig. 3; [0037]-[0040]; [0051]-[0062]; and Gschwind, [0015]; [0017]-[0024]; [0036]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as the new instruction(s) is properly executed.
As per claims 24-25, claims 24-25 are rejected in accordance to the same rational and reasoning as the above rejection of claim 1.
II. PERTINENT RELATED PRIOR ART
FRAZIER et al. (US Pub.: 2017/0046163): discloses when new processors that support new instructions (i.e., newer generations of the ISA) become available, application programs written for older processors of the ISA may have to be updated to use the new instructions and thereby improve performance and decrease the application footprint.
III. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 April 21, 2026
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