DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/20/2025 has been entered.
Claim Objections
Claims 1-9 are objected to because of the following informalities:
Claim 1, line 8 recites “a plurality of spaces including a first spacer and a second spacer”. It is recommended to change the limitation to “a plurality of spacers including a first spacer and a second spacer” for consistency with the rest of the claim. Appropriate correction is required.
Claims 2-9 are objected to based on their dependence on claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in U.S. Patent Publication 2015/0061134 A1 (hereafter Lee) and in view of Ikeda in U.S. Patent 11,121,135 B1 (hereafter Ikeda).
Regarding claim 1, Lee teaches (Figs. 1A-1E and related text, also refer to annotated Fig. 1B below), a semiconductor device, comprising:
a conductive contact plug (DC, [0080], Fig. 1B) disposed on a substrate (100, [0070], Fig. 1B), wherein the conductive contact plug (DC, Fig. 1B) includes a lower portion and an upper portion thereon (annotated Fig. 1B below), wherein the lower portion has a first width and the upper portion has a second width less than the first width (annotated Fig. 1B);
a bit line structure (140, [0083], Fig. 1B) disposed on the conductive contact plug (DC, Fig. 1B), wherein the bit line structure (140, Fig. 1B) includes a conductive structure (BL, [0083], Fig. 1B) and an insulation structure (137, [0083], Fig. 1B) that are stacked in a vertical direction that is substantially perpendicular to an upper surface of the substrate (100, Fig. 1B);
a spacer (127, [0081], Fig. 1B) disposed on a sidewall of the lower portion of the conductive contact plug (DC, Fig. 1B); and
a capping pattern (143a/A1, [0084]/[0090], Fig. 1B and annotated Fig. 1B below) disposed on the spacer (127, Fig. 1B), wherein the capping pattern (143a/A1, Fig. 1B) covers a sidewall of the upper portion of the conductive contact plug (annotated Fig. 1B);
wherein the spacer (127) directly contacts the sidewall of the lower portion of the conductive contact plug (DC), and
wherein an uppermost surface of the capping pattern (143a/A1, see annotated FIG. 1B below) is lower than an upper surface of the upper portion of the conductive contact plug (DC; noting the indicated surface of capping pattern 143a/A1 in annotated FIG. 1B is an uppermost surface with respect to the west/east direction since the claim does not provide any orientation for upper/lower with respect to surfaces of the capping pattern; at least a portion of the uppermost surface is below an upper surface of the upper portion of the conductive contact plug).
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Annotated FIG. 1 (Lee)
Lee does not teach a plurality spacers of that include a first spacer and a second spacer, wherein the first spacer and second spacer are stacked on a sidewall of the lower portion of the conductive contact plug (DC) in a horizontal direction substantially parallel to the upper surface of the substrate (100); and
a capping pattern (143a/A1) disposed on the first and second spacers,
wherein the first spacer directly contacts the sidewall of the lower portion of the conductive contact plug (DC) and includes air.
Ikeda teaches (Figs. 7b, 3, and related text) a plurality of spacers that include a first spacer and a second spacer (170 and 270, [Col. 8 line 40], and [Col. 4 line 29], respectively, Fig. 7b) stacked on a sidewall of a lower portion of a conductive contact plug (154, [Col. 8, line 56], Fig. 7b) in a horizontal direction substantially parallel to the upper surface of a substrate (50, [Col. 3 lines 22-23], Fig. 3; wherein the embodiment of Fig. 3 is referenced only to indicate the disposition of substrate 50 with respect to other features); and
wherein the first spacer (170) directly contacts the sidewall of the lower portion of the conductive contact plug (154, Fig. 7b) and includes air ([Col. 8, lines 40-41]), in order to reduce parasitic capacitance ([Col. 8, lines 25-29]).
Lee and Ikeda are analogous art to the claimed invention because they both are directed to semiconductor memory devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify the Lee in view of Ikeda because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the spacer of Lee to have a plurality of spacers that include a first spacer and second spacer wherein the first spacer and second spacer are stacked on a sidewall of the lower portion of the conductive contact plug in a horizontal direction substantially parallel to the upper surface of the substrate, and wherein the first spacer directly contacts the sidewall of the lower portion of the conductive contact plug (DC) and includes air, as taught by Ikeda, with the purpose of reducing parasitic capacitance (Ikeda, [Col. 8, lines 25-29]), since Lee is also concerned with parasitic capacitance (Lee, [0101]).
Regarding claim 2, Lee as modified by Ikeda teaches the semiconductor device of claim 1. Lee further teaches wherein the conducive contact plug (DC, Fig. 1B) includes a doped semiconductor ([0081]).
Lee does not explicitly teach that the conductive contact plug includes doped polysilicon.
However, Ikeda teaches a conductive contact plug (154, [Col. 8, line 56]) includes polysilicon with phosphorus doping ([Col. 5, lines 27-28]), in order to reduce bit line resistance ([Col 2, lines 26-28]).
Lee and Ikeda are analogous art to the claimed invention because they both are directed to semiconductor memory devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify the Lee in view of Ikeda because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device as taught by Lee such that the conductive contact plug includes doped polysilicon, as taught by Ikeda, with the purpose of reducing bit line resistance (Ikeda, [Col 2, lines 26-28]), since Lee describes bit line resistance as a problem (Lee, [0157]).
Regarding claim 3, Lee as modified by Ikeda teaches the semiconductor device according to claim 1. Lee further teaches wherein the second width of the upper portion of the conductive contact plug (DC, see annotated Fig. 1B above in the rejection of claim 1) is substantially equal to a width of a portion of the bit line structure (140, Fig. 1B) on the upper portion of the conductive contact plug (DC, annotated Fig. 1B).
Regarding claim 4, Lee as modified by Ikeda teaches the semiconductor device according to claim 1. Lee teaches further comprising an active pattern (ACT, [0071], Fig. 1B) and an isolation pattern (102, [0071], Fig. 1B) disposed on the substrate (100, Fig. 1B), wherein the isolation pattern (102, Fig. 1B) covers a sidewall of the active pattern (ACT, Fig. 1B),
wherein the conductive contact plug (DC, Fig. 1B) contacts a central upper surface of the active pattern (ACT, Fig. 1B).
Regarding claim 5, Lee as modified by Ikeda teaches the semiconductor device of claim 4. Lee teaches further comprising a conductive pad (XP, [0078], Fig. 1B) disposed on the active pattern (ACT, Fig. 1B) and the isolation pattern (102, Fig. 1B), wherein the conductive pad (XP, Fig. 1B) overlaps at least a portion of the conductive contact plug (DC, Fig. 1B) in the horizontal direction (see Fig. 1B).
Regarding claim 6, Lee as modified by Ikeda teaches the semiconductor device of claim 5. Lee teaches wherein the conductive pad (XP, Fig. 1B) overlaps an upper portion of a spacer (127, Fig. 1B) in the horizontal direction (see Fig. 1B).
Ikeda further teaches a plurality of spacers (170/270) that include a first spacer (170) and a second spacer (270) stacked on a sidewall of the lower portion of a conductive contact plug (154) in a horizontal direction substantially parallel to the upper surface of a substrate (50), in order to reduce parasitic capacitance ([Col. 8, lines 25-29]).
Lee and Ikeda are analogous art to the claimed invention because they both are directed to semiconductor memory devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify the Lee in view of Ikeda because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the spacer of Lee to have a plurality of spacers that include a first spacer and second spacer wherein the first spacer and second spacer are stacked on a sidewall of the lower portion of the conductive contact plug in a horizontal direction substantially parallel to the upper surface of the substrate, as taught by Ikeda, with the purpose of reducing parasitic capacitance (Ikeda, [Col. 8, lines 25-29]), since Lee is also concerned with parasitic capacitance (Lee, [0101]).
Regarding claim 7, Lee as modified by Ikeda teaches the semiconductor device of claim 5. Lee further teaches wherein a lower surface of the conductive pad (XP, Fig. 1B) is lower than a lower surface of the upper portion of the conductive contact plug (horizontal surface of DC in contact with 143a, Fig. 1B and annotated Fig. 1B above).
Regarding claim 8, Lee as modified by Ikeda teaches the semiconductor device according to claim 1. Lee teaches further comprising:
an insulation pattern (3a, FIG. 1B, [0085]) disposed on and in direct contact with the capping pattern (143a/A1), wherein the insulation pattern (3a) includes a nitride ([0096]); and
a spacer structure (7a/3b, [0084]/[0085], Fig. 1B) disposed on the capping pattern (143a/A1, Fig. 1B) and the insulation pattern (3a, Fig. 1B), wherein the spacer structure (7a/3b, Fig. 1B) covers a sidewall of the bit line structure (140, Fig. 1B).
wherein an upper surface of the insulation pattern (3a) is substantially coplanar with an upper surface of the capping pattern (143a/A1, annotated FIG. 1B below, again noting the claim does not provide an orientation for “upper” with respect to the capping pattern or insulation layer).
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Annotated FIG. 1B (Lee)
Regarding claim 9, Lee teaches (Figs. 1A-1E and related text, also refer to annotated Fig. 1B) a semiconductor device, comprising:
a conductive contact plug (DC, [0080], Fig. 1B) disposed on a substrate (100, [0070], Fig. 1B), wherein the conductive contact plug (DC, Fig. 1B) includes a lower portion and an upper portion thereon (see annotated Fig. 1B related in the rejection of claim 1 above), wherein the lower portion has a first width and the upper portion has a second width narrower than the first width (annotated Fig. 1B);
a bit line structure (140, [0083], Fig. 1B) disposed on the conductive contact plug (DC, Fig. 1B), wherein the bit line structure (140, Fig. 1B) includes a conductive structure (BL, [0083], Fig. 1B) and an insulation structure (137, [0083], Fig. 1B) stacked in a vertical direction that is substantially perpendicular to an upper surface of the substrate (100, Fig. 1B);
a spacer (127, [0081], Fig. 1B) that directly contacts a sidewall of the lower portion of the conductive contact plug (DC, Fig. 1B);
an active pattern (ACT, [0070], Fig. 1B) and an isolation pattern (102, [0070], FIG. 1B) disposed on the substrate; and
a capping pattern (143a/A1, [0084]), Fig. 1B) disposed on a top end of the spacer (127, Fig. 1B).
wherein an uppermost surface of the capping pattern (143a/A1, see annotated FIG. 1B in the rejection of claim 1) is lower than an upper surface of the upper portion of the conductive contact plug (DC; noting the indicated surface of capping pattern 143a/A1 in annotated FIG. 1B is an uppermost surface with respect to the west/east direction since the claim does not provide any orientation for upper/lower with respect to surfaces of the capping pattern; at least a portion of the uppermost surface is below an upper surface of the upper portion of the conductive contact plug).
Lee does not teach: an air spacer that directly contacts a sidewall of the lower portion of the conductive contact plug (XP) and that includes air;
wherein the conductive pad (5a) overlaps an uppermost surface of the air spacer in the horizontal direction; and
a capping pattern (143a/A1) disposed on a top end of the air spacer.
Ikeda teaches in Fig. 7b and related text: an air spacer (170, [Col. 8 line 40]) that directly contacts the sidewall of the lower portion of a conductive contact plug (154, [Col. 8, line 56]) and that includes air ([Col. 8, lines 40-41]), in order to reduce parasitic capacitance ([Col. 8, lines 25-29]).
Lee and Ikeda are analogous art to the claimed invention because they both are directed to semiconductor memory devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify the Lee in view of Ikeda because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the spacer of Lee to have an air spacer that directly contacts the sidewall of the lower portion of a conductive contact plug and that includes air, as taught by Ikeda, with the purpose of reducing parasitic capacitance (Ikeda, [Col. 8, lines 25-29]), since Lee is also concerned with parasitic capacitance (Lee, [0101]).
Regarding claim 10, Lee as modified by Ikeda teaches the semiconductor device according to claim 9. Lee teaches wherein the isolation pattern (102, Fig. 1B) covers a sidewall of the active pattern (ACT, Fig. 1B),
wherein the conductive contact plug (DC, Fig. 1B) contacts a central upper surface of the active pattern (ACT, Fig. 1B).
Regarding claim 11, Lee as modified by Ikeda teaches the semiconductor device of claim 10. Lee teaches further comprising a conductive pad (5a, [0087], Fig. 1B) overlapping at least a portion of the conductive contact plug (DC, Fig. 1B) in the horizontal direction.
Regarding claim 12, Lee as modified by Ikeda teaches the semiconductor device of claim 11. Lee teaches wherein the conductive pad (5a, Fig. 1B) overlaps an upper portion of the spacer (127, Fig. 1B) in the horizontal direction.
Ikeda further teaches in Fig. 7b and related text, an air spacer (170) that directly contacts the sidewall of the lower portion of a conductive contact plug (154) and that includes air ([Col. 8, lines 40-41]), in order to reduce parasitic capacitance ([Col. 8, lines 25-29]).
Lee and Ikeda are analogous art to the claimed invention because they both are directed to semiconductor memory devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify the Lee in view of Ikeda because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the spacer of Lee to have an air spacer that directly contacts the sidewall of the lower portion of a conductive contact plug and that includes air, as taught by Ikeda, with the purpose of reducing parasitic capacitance (Ikeda, [Col. 8, lines 25-29]), since Lee is also concerned with parasitic capacitance (Lee, [0101]).
Regarding claim 13, Lee as modified by Ikeda teaches the semiconductor device of claim 11. Lee teaches wherein a sidewall of the conductive pad (5a, Fig. 1B) directly contacts the spacer (127, Fig. 1B).
Ikeda further teaches in Fig. 7b and related text, an air spacer (170) that directly contacts the sidewall of the lower portion of a conductive contact plug (154) and that includes air ([Col. 8, lines 40-41]), in order to reduce parasitic capacitance ([Col. 8, lines 25-29]).
Lee and Ikeda are analogous art to the claimed invention because they both are directed to semiconductor memory devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify the Lee in view of Ikeda because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the spacer of Lee to have an air spacer that directly contacts the sidewall of the lower portion of a conductive contact plug and that includes air, as taught by Ikeda, with the purpose of reducing parasitic capacitance (Ikeda, [Col. 8, lines 25-29]), since Lee is also concerned with parasitic capacitance (Lee, [0101]).
Regarding claim 14, Lee as modified by Ikeda teaches the semiconductor device of claim 11. Lee teaches wherein the spacer (127, Fig. 1B) is surrounded by the conductive contact plug (XP, Fig. 1B), the active pattern (ACT, Fig. 1B), the isolation pattern (102, Fig. 1B) and the capping pattern (143a, Fig. 1B).
Ikeda further teaches in Fig. 7b and related text: an air spacer (170) that directly contacts the sidewall of the lower portion of a conductive contact plug (154) and that includes air ([Col. 8, lines 40-41]), in order to reduce parasitic capacitance ([Col. 8, lines 25-29]).
Lee and Ikeda are analogous art to the claimed invention because they both are directed to semiconductor memory devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify the Lee in view of Ikeda because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the spacer of Lee to have an air spacer that directly contacts the sidewall of the lower portion of a conductive contact plug and that includes air, as taught by Ikeda, with the purpose of reducing parasitic capacitance (Ikeda, [Col. 8, lines 25-29]), since Lee is also concerned with parasitic capacitance (Lee, [0101]).
Regarding claim 15, Lee teaches (Figs. 1A-1E, 8A, and related text) a semiconductor device, comprising:
an active pattern (ACT, [0070], Fig. 1B) disposed on a substrate (100, [0070], Fig. 1B);
an isolation pattern (102, [0070], Fig. 1B) disposed on the substrate (100, Fig. 1B), wherein the isolation pattern (102, Fig. 1B) covers a sidewall of the active pattern (ACT, Fig. 1B);
a gate structure (WL, 107, [0073]-[0075], Fig. 1E) that extends in a first direction (D2, Fig 1a) substantially parallel to an upper surface of the substrate (100, FIG. 1E), wherein the gate structure (WL) is disposed in upper portions of the active pattern (ACT, Fig. 1E) and the isolation pattern (102, Fig. 1E);
a conductive pad (XP, [0078], Fig. 1B) disposed on the active pattern (ACT, Fig. 1B) and the isolation pattern (102, Fig. 1B);
a conductive contact plug (DC, [0080], Fig. 1B) that extends through the conductive pad (XP; Fig. 1B viewed in conjunction with Fig. 8A depicts DC extending through XP) and contacts a central upper surface of the active pattern (ACT, Fig. 1B), wherein the conductive contact plug (DC, Fig. 1B) includes a lower portion and an upper portion thereon, and the lower portion has a first width and the upper portion has a second width that is narrower than the first width (refer to annotated Fig. 1B above in the rejection of claim 1);
a bit line structure (140, [0083], Fig. 1B) disposed on the conductive contact plug (DC, Fig. 1B) and the conductive pad (XP, Fig. 1B), wherein the bit line structure (140, Fig. 1B) extends in a second direction (D3, Fig. 1A, also refer to Fig. 1C) substantially parallel to the upper surface of the substrate (100, Fig. 1C) and substantially perpendicular to the first direction (D3 direction in Fig. 1A, which is perpendicular to D2 direction);
a spacer (127, [0081], Fig. 1B) disposed on a sidewall of the lower portion of the conductive contact plug (DC, Fig. 1B);
a capping pattern (143a/A1, [0084], Fig. 1B) disposed on the spacer (127, Fig. 1B), wherein the capping pattern (143a/A1, Fig. 1B) covers a sidewall of the upper portion of the conductive contact plug (annotated Fig. 1B);
an insulation pattern (3a, [0085], Fig. 1B) disposed on and in direct contact with the capping pattern, wherein the insulation pattern includes a nitride ([0096]);
a spacer structure (7a/3b, [0084]/[0085], Fig. 1B) disposed on the capping pattern (143a/A1, Fig. 1B) and the insulation pattern (3a, Fig. 1B), wherein the spacer structure (7a/3b) is disposed on a sidewall of the bit line structure (140, Fig. 1B);
a contact plug structure (BC, [0084], Fig. 1B) disposed on the conductive pad (XP, Fig. 1B);
a capacitor (DSP, [0107], Fig. 1B) disposed on the contact plug structure (BC, Fig. 1B),
wherein the spacer (127, FIG. 1B) directly contacts the sidewall of the lower portion of the conductive contact plug (DC); and
wherein an uppermost surface of the capping pattern (143a/A1, see annotated FIG. 1B in the rejection of claim 1) is lower than an upper surface of the upper portion of the conductive contact plug (DC; noting the indicated surface of capping pattern 143a/A1 in annotated FIG. 1B is an uppermost surface with respect to the west/east direction since the claim does not provide any orientation for upper/lower with respect to surfaces of the capping pattern; at least a portion of the uppermost surface is below an upper surface of the upper portion of the conductive contact plug).
Lee does not teach a plurality spacers of that include a first spacer and a second spacer, wherein the first spacer and second spacer are stacked on a sidewall of the lower portion of the conductive contact plug (DC) in a horizontal direction substantially parallel to the upper surface of the substrate (100); and
a capping pattern (143a/A1) disposed on the first and second spacers,
wherein the first spacer directly contacts the sidewall of the lower portion of the conductive contact plug (DC) and includes air.
Ikeda teaches (Figs. 7b, 3, and related text) a plurality of spacers that include a first spacer and a second spacer (170 and 270, [Col. 8 line 40] and [Col. 4 line 29], respectively, Fig. 7b) stacked on a sidewall of the lower portion of a conductive contact plug (154, [Col. 8, line 56], Fig. 7b) in a horizontal direction substantially parallel to the upper surface of a substrate (50, [Col. 3 lines 22-23], Fig. 3; wherein the embodiment of Fig. 3 is referenced only to indicate the disposition of substrate 50 with respect to other features); and
wherein the first spacer (170) directly contacts the sidewall of the lower portion of the conductive contact plug (154, Fig. 7b) and includes air ([Col. 8, lines 40-41]), in order to reduce parasitic capacitance ([Col. 8, lines 25-29]).
Lee and Ikeda are analogous art to the claimed invention because they both are directed to semiconductor memory devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify the Lee in view of Ikeda because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the spacer of Lee to have a plurality of spacers that include a first spacer and second spacer wherein the first spacer and second spacer are stacked on a sidewall of the lower portion of the conductive contact plug in a horizontal direction substantially parallel to the upper surface of the substrate, and wherein the first spacer directly contacts the sidewall of the lower portion of the conductive contact plug (DC) and includes air, as taught by Ikeda, with the purpose of reducing parasitic capacitance (Ikeda, [Col. 8, lines 25-29]), since Lee is also concerned with parasitic capacitance (Lee, [0101]).
Regarding claim 16, Lee as modified by Ikeda teaches the semiconductor device according to claim 16. Lee teaches further comprising
a first insulation pad (123, [0079], Fig. 1B) interposed between the conductive pad (XP, Fig. 1B) and the bit line structure (140, Fig. 1B).
Regarding claim 17, Lee as modified by Ikeda teaches the semiconductor device according to claim 16. Lee teaches further comprising
a second insulation pad (117, [0079], Fig. 1B) disposed on the active pattern (ACT, Fig. 1B) and the isolation pattern (102, Fig. 1B), wherein the second insulation pad (117, Fig. 1B) covers a sidewall of the conductive pad (XP, Fig. 1B),
wherein the first insulation pad (123, Fig. 1B) is disposed on the conductive pad (XP, Fig. 1B) and the second insulation pad (117, Fig. 1B).
Regarding claim 19, Lee as modified by Ikeda teaches the semiconductor device according to claim 15. Lee further teaches wherein:
the active pattern (ACT, Fig. 1B) extends in a third direction (D1, Fig. 1A) substantially parallel to the upper surface of the substrate (100, Figs. 1B-1D) and having an acute angle with the first and second directions (D1 has an acute angle with respect to directions D2 and D3, Fig. 1A),
the conductive pad (XP, Fig. 1B) is disposed on a central upper surface of the active pattern (Fig. 1B) and each of opposite end portions in the third direction (D1, Fig. 1A) of the active pattern (Fig. 8A shows XP overlapping with opposite end portions in direction D1 of ACT), and
the contact plug (BC, Fig. 1B) is disposed on a portion of the conductive pad (XP, Fig. 1B) on each of opposite end portions in the third direction (D1, Fig. 1) of the active pattern (ACT; Fig. 1A depicts BC overlapping with opposite end portions in D1 direction of ACT, and Fig. 1B depicts BC disposed on a portion of XP).
Regarding claim 20, Lee as modified by Ikeda teaches the semiconductor device according to claim 15. Lee teaches wherein the conductive pad (XP, Fig. 1B) overlaps an upper portion of the spacer (127, Fig. 1B) in the horizontal direction (Fig. 1B).
Ikeda further teaches in Figs. 7b and related text, a plurality of spacers that include a first spacer and a second spacer (170, and 270, respectively), wherein the first spacer (170) and second spacer (270) are stacked on a sidewall of the lower portion of a conductive contact plug (154), in order to reduce parasitic capacitance ([Col. 8, lines 25-29]).
Lee and Ikeda are analogous art to the claimed invention because they both are directed to semiconductor memory devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify the Lee in view of Ikeda because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the spacer of Lee to have a plurality of spacers that include a first spacer and second spacer wherein the first spacer and second spacer are stacked on a sidewall of the lower portion of the conductive contact plug, as taught by Ikeda, with the purpose of reducing parasitic capacitance (Ikeda, [Col. 8, lines 25-29]), since Lee is also concerned with parasitic capacitance (Lee, [0101]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in U.S. Patent Publication 2015/0061134 A1 (hereafter Lee) in view of Ikeda in U.S. Patent 11,121,135 B1 (hereafter Ikeda) and further in view of Kim in U.S. Patent Application Publication US 2013/0320550 A1 (hereinafter Kim) .
Regarding claim 18, Lee as modified by Ikeda teaches the semiconductor device according to claim 15.
Lee does not teach wherein spacer structure (7a/3b, Fig. 1B) includes third, fourth and fifth spacers that are sequentially stacked on the sidewall of the bit line structure (140, Fig. 1B), and
wherein the fourth spacer includes air.
Kim teaches in FIG. 11 and related text, a spacer structure that includes third (36A, [1024]), fourth (41, [1025]) and fifth spacers (38A, [1024]) that are sequentially stacked on the sidewall of a bit line structure (34/35, [0122]), and
wherein the fourth spacer (41, [0125]) includes air, in order to reduce parasitic capacitance between bit lines and storage node contact plugs ([0127]).
Lee, Ikeda and Kim are analogous art to the claimed invention because they are directed to semiconductor memory devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined structure of Lee and Ikeda in view of Kim because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device as taught by Lee and Ikeda such that the spacer structure includes third, fourth and fifth spacers that are sequentially stacked on the sidewall of the bit line structure, and wherein the fourth spacer includes air, as taught by Kim, with the purpose of reducing parasitic capacitance (Kim, [0127]), since Lee is also concerned with parasitic capacitance (Lee, [0101]).
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda in US 11,121,135 B1 (hereinafter Ikeda).
Regarding claim 1, Ikeda teaches in the embodiment of FIG. 4 and related text, a semiconductor device, comprising:
a conductive contact plug (154, [col. 4, lines 8-24]) disposed on a substrate (50, [col. 4, lines 8-24]), wherein the conductive contact plug (154) includes a lower portion and an upper portion thereon, wherein the lower portion has a first width and the upper portion has a second width less than the first width (see annotated FIG. 4 below);
a bit line structure (152/156/158, [col. 4, lines 40-53]) disposed on the conductive contact plug (154), wherein the bit line structure (152/156/158) includes a conductive structure (152/158) and an insulation structure (158) that are stacked in a vertical direction that is substantially perpendicular to an upper surface of the substrate (50);
a plurality of spaces (170/172, [col. 4, lines 50-58]) including a first spacer (170) and a second spacer (172), wherein the first spacer (170) and second spacer (172) are stacked on a sidewall of the lower portion of the conductive contact plug (154) in a horizontal direction substantially parallel to the upper surface of the substrate (50);
a capping pattern (179 as shown in FIG. 5F and annotated FIG. 4 below, [col. 5, lines [43-50]) disposed on the first and second spacers (170 and 172), wherein the capping pattern (179) covers a sidewall of the upper portion of the conductive contact plug (154); and
wherein the first spacer (170) directly contacts the sidewall of the lower portion of the conductive contact plug (154), and
wherein an uppermost surface of the capping pattern (179) is lower than an upper surface of the upper portion of the conductive contact plug (154).
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Annotated FIG. 4 (Ikeda)
Ikeda does not explicitly state in the embodiment of FIG. 4, wherein the first spacer includes air.
However, Ikeda states in [col. 4, lines 57-58], the first spacer 170 may be an air gap, and further teaches in the embodiment of FIG. 7B wherein the first spacer 170 includes air ([col. 8, lines 40-41]), in order to reduce parasitic capacitance ([col. 8, lines 25-29]).
It would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first spacer of Ikeda such that it includes air, as taught by Ikeda in the embodiment of FIG. 7B, in order to reduce parasitic capacitance ([col. 8, lines 25-29]).
Regarding claim 2, Ikeda teaches the semiconductor device according to claim 1. Ikeda further teaches in the embodiment of FIG. 4 wherein the conductive contact plug (154) includes doped polysilicon ([Col. 5, lines 27-28]).
Regarding claim 3, Ikeda teaches the semiconductor device according to claim 1. Ikeda further teaches in the embodiment of FIG. 4 wherein the second width of the upper portion of the conductive contact plug (154; see annotated FIG. 4 in the rejection of claim 1) is substantially equal to a width of a portion of the bit line structure (152/156/158) on the upper portion of the conductive contact plug (154).
Regarding claim 4, Ikeda teaches the semiconductor device according to claim 1. Ikeda teaches in the embodiment of FIG. 4 further comprising an active pattern (52a/b, [col. 4, lines 8-24]) and an isolation pattern (54a/b, [col. 4, lines 8-24]) disposed on the substrate (50), wherein the isolation pattern (54a/b) covers a sidewall of the active pattern (52a/b),
wherein the conductive contact plug (154) contacts a central upper surface of the active pattern (52a, FIG. 4).
Regarding claim 5, Ikeda teaches the semiconductor device according to claim 4. Ikeda teaches in the embodiment of FIG. 4 further comprising a conductive pad (180, FIG. 4, [col. 4, lines 8-24]) disposed on the active pattern and the isolation pattern (52a/b), wherein the conductive pad (180) overlaps at least a portion of the conductive contact plug (154) in the horizontal direction.
Regarding claim 6, Ikeda teaches the semiconductor device according to claim 5. Ikeda further teaches in the embodiment of FIG. 4 wherein the conductive pad (180) overlaps an upper portion of the first spacer (170) in the horizontal direction.
Regarding claim 7, Ikeda teaches the semiconductor device according to claim 5. Ikeda further teaches in the embodiment of FIG. 4 wherein a lower surface of the conductive pad (bottom surface of 180) is lower than a lower surface of the upper portion of the conductive contact plug (a sidewall of the upper portion of 154 in the annotated FIG. 4 is a lower surface).
Regarding claim 8, Ikeda teaches the semiconductor device according to claim 1. Ikeda teaches in the embodiment of FIG. 4 further comprising:
an insulation pattern (176, FIG. 4, [col. 5, lines 55-56]) disposed on and in direct contact with the capping pattern (179), wherein the insulation pattern (176) includes a nitride ([col. 5, lines 55-56]); and
a spacer structure (174, FIG. 4, [col. 51-52]) disposed on the capping pattern (179) and the insulation pattern (176), wherein the spacer structure (174) covers a sidewall of the bit line structure (152/156/158),
wherein an upper surface of the insulation pattern (176) is substantially coplanar with an upper surface of the capping pattern (179; see annotated FIG. 4 below – the sidewalls of 176 and 179 are upper surfaces and are substantially coplanar).
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Annotated FIG. 4 (Ikeda)
Regarding claim 9, Ikeda teaches in the embodiment of FIG. 3 and related text, a semiconductor device, comprising:
a conductive contact plug (60, [col. 3, lines 18-36]) disposed on a substrate (50, [col. 3, lines 18-36]), wherein the conductive contact plug (60) includes a lower portion and an upper portion thereon, wherein the lower portion has a first width and the upper portion has a second width narrower than the first width (see annotated FIG. 3 below);
a bit line structure (74/66/72, [col. 3, lines 37-58]) disposed on the conductive contact plug (60), wherein the bit line structure (74/66/72) includes a conductive structure (74/66 and an insulation structure (72) stacked in a vertical direction that is substantially perpendicular to an upper surface of the substrate (50);
a spacer (66, [col. 3, lines 37-58]) that directly contacts a sidewall of the lower portion of the conductive contact plug (60);
an active pattern (52, [col. 3, lines 18-36]) and an isolation pattern (54, [col. 3, lines 18-36]) disposed on the substrate (50); and
a capping pattern (24, [col. 3, lines 37-58]) disposed on a top end of the spacer (66),
wherein an uppermost surface of the capping pattern (24) is lower than an upper surface of the upper portion of the conductive contact plug (60).
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Annotated FIG. 3 (Ikeda)
Ikeda does not explicitly state in the embodiment of FIG. 3 that the spacer 66 is an air spacer that includes air.
However, Ikeda teaches in the embodiment of FIG. 7B, an air spacer (170, [col. 8, lines 40-41]) that directly contacts a sidewall of the lower portion of a conductive contact plug (154) reduces parasitic capacitance ([col. 8, lines 25-29]).
It would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the spacer in the embodiment of FIG. 3 of Ikeda such that it is an air spacer that includes air, as taught by Ikeda in the embodiment of FIG. 7B, in order to reduce parasitic capacitance ([col. 8, lines 25-29]).
Regarding claim 10, Ikeda teaches the semiconductor device according to claim 9. Ikeda further teaches in the embodiment of FIG. 3 wherein the isolation pattern (54) covers a sidewall of the active pattern (52), wherein the conductive contact plug (60) contacts a central upper surface of the active pattern (52).
Regarding claim 11, Ikeda teaches the semiconductor device according to claim 10. Ikeda teaches in the embodiment of FIG. 3 further comprising a conductive pad (62, [col. 3, lines 18-36]) overlapping at least a portion of the conductive contact plug (60) in the horizontal direction.
Regarding claim 12, Ikeda teaches the semiconductor device according to claim 11. Ikeda further teaches in the embodiment of FIG. 3 wherein the conductive pad (62) overlaps an upper portion of the spacer (66) in the horizontal direction.
Ikeda teaches in the embodiment of FIG. 7B the spacer 66 may be an air spacer in order to reduce parasitic capacitance.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the spacer in the embodiment of FIG. 3 of Ikeda such that it is an air spacer, as taught by Ikeda in the embodiment of FIG. 7B, in order to reduce parasitic capacitance ([col. 8, lines 25-29]).
Regarding claim 13, Ikeda teaches the semiconductor device according to claim 11. Ikeda further teaches in the embodiment FIG. 3 wherein a sidewall of the conductive pad (62) directly contacts the spacer (66).
Ikeda teaches in the embodiment of FIG. 7B the spacer 66 may be an air spacer in order to reduce parasitic capacitance.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the spacer in the embodiment of FIG. 3 of Ikeda such that it is an air spacer, as taught by Ikeda in the embodiment of FIG. 7B, in order to reduce parasitic capacitance ([col. 8, lines 25-29]).
Regarding claim 14, Ikeda teaches the semiconductor device according to claim 11. Ikeda further teaches in the embodiment of FIG. 3 wherein the spacer (66) is surrounded by the conductive contact plug (74), the active pattern (52), the isolation pattern (54) and the capping pattern (24).
Ikeda teaches in the embodiment of FIG. 7B the spacer 66 may be an air spacer in order to reduce parasitic capacitance.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the spacer in the embodiment of FIG. 3 of Ikeda such that it is an air spacer, as taught by Ikeda in the embodiment of FIG. 7B, in order to reduce parasitic capacitance ([col. 8, lines 25-29]).
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda in US 11,121,135 B1 (hereinafter Ikeda), in view of Lee et al. in US 2015/0061134 A1 (hereinafter Lee).
Regarding claim 15, Ikeda teaches in the embodiment of FIG. 4 and related text, A semiconductor device, comprising:
an active pattern (52a/b, [col. 4, lines 8-24]) disposed on a substrate (50, [col. 4, lines 8-24]);
an isolation pattern (54a/b, [col. 4, lines 8-24]) disposed on the substrate (50), wherein the isolation pattern (54a/b) covers a sidewall of the active pattern (52a/b);
a gate structure (word line, FIG. 2, [col. 3, lines 2-3]) that extends in a first direction (north/south direction of line I-I in FIG. 2, [col. 3, lines 2-3]) substantially parallel to an upper surface of the substrate (50);
a conductive pad (180, [col. 4, lines 8-24]) disposed on the active pattern (52a/b) and the isolation pattern (54a/b);
a conductive contact plug (154, [col. 4, lines 8-24]) that extends through the conductive pad (180; FIG. 2 combined with FIG. 4 shows 154 extends through 180 inasmuch as Applicant’s FIGS. 24 does) and contacts a central upper surface of the active pattern (52a), wherein the conductive contact plug (154) includes a lower portion and an upper portion thereon, and the lower portion has a first width and the upper portion has a second width that is narrower than the first width (see annotated FIG. 4 below);
a bit line structure (152/156/158, [col. 4, lines 40-53]) disposed on the conductive contact plug (154) and the conductive pad (180), wherein the bit line structure (152/156/158) extends in a second direction (east/west, FIG. 2, [col. 3, lines 2-3]) substantially parallel to the upper surface of the substrate (50) and substantially perpendicular to the first direction (north/south, FIG. 2, [col. 2, [lines 61-17] – [col. 3, lines 1-7]);
a plurality of spacers (170/172, [col. 4, lines 50-58]) including a first spacer (170) and a second spacer (172), wherein the first spacer (170) and second spacer (172) are stacked on a sidewall of the lower portion of the conductive contact plug (154) in a horizontal direction substantially parallel to the upper surface of the substrate (50);
a capping pattern (179 as shown in FIG. 5F and annotated FIG. 1 below, [col. 5, lines [43-50]) disposed on the first and second spacers (170 and 172), wherein the capping pattern (179) covers a sidewall of the upper portion of the conductive contact plug (154);
an insulation pattern (176, [col. 5, lines 55-56]) disposed on and in direct contact with the capping pattern (179), wherein the insulation pattern (176) includes a nitride ([col. 5, lines 55-56]);
a spacer structure (174, [col. 51-52]) disposed on the capping pattern (179) and the insulation pattern (176), wherein the spacer structure (174) is disposed on a sidewall of the bit line structure (152/156/158);
a contact plug structure (182/184/186, [col. 6, lines 17-25]) disposed on the conductive pad (180); and
wherein the first spacer (170) directly contacts the sidewall of the lower portion of the conductive contact plug (154), and
wherein an uppermost surface of the capping pattern (179) is lower than an upper surface of the upper portion of the conductive contact plug (154).
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Annotated FIG. 4 (Ikeda)
Ikeda does not explicitly state in the embodiment in FIG. 4 wherein the gate structure is disposed in upper portions of the active pattern and the isolation pattern; a capacitor disposed on the contact plug structure, and wherein the first spacer includes air.
However, Ikeda states in [col. 4, lines 57-58], the first spacer 170 may be an air gap, and further teaches in the embodiment of FIG. 7B wherein the first spacer 170 includes air ([col. 8, lines 40-41]), in order to reduce parasitic capacitance ([col. 8, lines 25-29]).
Lee teaches in FIG. 1E wherein a gate structure (WL, [0075]) is disposed in upper portions of an active pattern (ACT, [0075]) and an isolation pattern (102, [0075]), in order to improve a short channel effect in a transistor ([0075]). Lee teaches in FIG. 3A a capacitor (DSP, [0107]) disposed on a contact plug structure (175/LP, [0107], in order to provide a data storage part for storing logic data in a memory device ([0103]).
Ikeda and Lee are analogous art to the claimed invention because they are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ikeda in view of Lee because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ikeda such that:
the gate structure is disposed in upper portions of the active pattern and the isolation pattern, as taught by Lee, in order to improve a short channel effect in a transistor (Lee, [0075]);
a capacitor disposed on the contact plug structure, as taught by Lee, in order to provide a data storage part for storing logic data in a memory device (Lee, [0103]); and
the first spacer includes air, as taught by Ikeda in the embodiment of FIG. 7B, in order to reduce parasitic capacitance (Ikeda, [col. 8, lines 25-29]).
Regarding claim 16, Ikeda as modified by Lee teaches the semiconductor device according to claim 15. Ikeda teaches in the embodiment of FIG. 4 further comprising a first insulation pad (middle layer of 152a, [col. 4, line 21], noting 152a is an insulating layer comprised of three separate layers) interposed between the conductive pad (180) and the bit line structure (152/156/158).
Regarding claim 17, Ikeda as modified by Lee teaches the semiconductor device according to claim 16. Ikeda teaches in the embodiment of FIG. 4 further comprising a second insulation pad (bottom layer of 152a) disposed on the active pattern (52a/b) and the isolation pattern (54a/b), wherein the second insulation pad (bottom layer of 152a) covers a sidewall of the conductive pad (180), wherein the first insulation pad (middle layer of 152a) is disposed on the conductive pad (180) and the second insulation pad (bottom layer of 152a).
Regarding claim 18, Ikeda as modified by Lee teaches the semiconductor device according to claim 15. Ikeda does not explicitly state in the embodiment of FIG. 4 wherein the spacer structure (174) includes third, fourth and fifth spacers that are sequentially stacked on the sidewall of the bit line structure, and wherein the fourth spacer includes air.
Lee teaches in FIG. 1B, a spacer structure includes third (143a, [0084]), fourth (AG, [0091]) and fifth (7a, [0145]) spacers that are sequentially stacked on a sidewall of a bit line structure (BL, [0084]) and wherein the fourth spacer (AG) includes air ([0084]), in order to reduce parasitic capacitance ([0161]).
Ikeda and Lee are analogous art to the claimed invention because they are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ikeda in view of Lee because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the spacer structure in the embodiment of FIG. 4 of Ikeda to include third, fourth and fifth spacers that are sequentially stacked on the sidewall of the bit line structure, and wherein the fourth spacer includes air, as taught by Lee, in order to reduce parasitic capacitance (Lee, [0161]), since Ikeda is also concerned with parasitic capacitance (Ikeda, [col. 8, lines 25-29]).
Regarding claim 19, Ikeda as modified by Lee teaches the semiconductor device according to claim 15. Ikeda further teaches in the embodiment of FIG. 4 wherein: the active pattern (52a/b) extends in a third direction (“slant direction”, FIG. 1, [col. 2, line 56]) substantially parallel to the upper surface of the substrate (50) and having an acute angle with the first (north/south, FIG. 2) and second directions (east/west, FIG. 2),
the conductive pad (180, which is part of capacitor contact structure 62 in FIG. 2, [col. 4, lines 37-38]) is disposed on a central upper surface of the active pattern (52a/b) and each of opposite end portions in the third direction (“slant direction”, FIGS. 1/2) of the active pattern (52a/b; see FIG. 2) , and
the contact plug structure (154, which is part of bit line contact structure 60 in FIG. 2, [col. 4, line 26]) is disposed on a portion of the conductive pad (180) on each of opposite end portions in the third direction (slant direction, FIG. 2) of the active pattern (52a/b; FIGS. 2 and 4 show this inasmuch as Applicant’s FIG. 24 does).
Regarding claim 20, Ikeda as modified by Lee teaches the semiconductor device according to claim 15. Ikeda further teaches in the embodiment of FIG. 4 wherein the conductive pad (180) overlaps an upper portion of the first spacer (170) in the horizontal direction.
Response to Arguments
Applicant’s remarks on page 7 regarding the status of the claims are acknowledged.
Applicant’s remarks on page 7 regarding the interview conducted on 08/04/2025 are acknowledged. The Examiner likewise thanks Applicant’s representative for time and courtesy in the interview. The Examiner notes, as does Applicant, no agreement was reached during the interview.
Applicant’s remarks on page 7 regarding the claim objections made in the Final Office Action mailed on 06/20/2025 (hereinafter previous Office Action) are acknowledged.
In response, the Examiner finds the amendments to claims 1 and 15 overcome the claim objections and hereby withdraws the objections in this instant Office Action.
Applicant’s remarks on page 7 regarding the rejection of claims 9-14 under 35 U.S.C. 112(b) in the previous Office Action are acknowledged.
In response, the Examiner finds the amendment to claim 9 regarding “an active pattern” sufficient to overcome the rejections, and hereby withdraws those rejections in the instant Office Action.
Applicant’s arguments on pages 7-10 regarding the rejections made under U.S.C. 103 in the previous Office Action are acknowledged. Applicant traverses the rejections in light of the present amendments. Applicant specifically argues on pages 8-9 Lee fails to teach “an uppermost surface of the capping pattern is lower than an upper surface of the upper portion of the conductive contact plug”.
In response, the Examiner finds this argument non persuasive. As explained in the 103 rejections made over Lee in view of Ikeda in the instant Office Action, the claims do not provide any directional orientation for “upper” with respect to the capping pattern. Therefore, the Examiner has interpreted “an uppermost surface of the capping pattern (143a/A1)” as shown below in the annotated FIG. 1B of Lee. When viewed from the direction of west/east (or left to right), the surface as indicated in the annotated FIG. 1B is an uppermost surface of 143a/A1. At least a portion of the uppermost surface of 143/A1 is lower than an upper surface of the upper portion of the conductive contact plug (DC). The rejections made under 35 U.S.C. 103 of independent claims 1, 9, and 15 made in the previous Office Action are therefore maintained.
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Additionally, the Examiner finds new grounds for rejections of claims 1-20 in light of Applicant’s amendments. Applicant’s arguments with respect to the rejections made in the previous Office Actions regarding these rejections have been considered, but are moot because the new ground of rejection does not rely on the Lee reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues on page 9, third paragraph, “Applicant believes that the other references do not cure the deficiencies of Lee”.
In response, the Examiner finds this argument non-persuasive for two reasons. 1) The Examiner does not find Lee has the alleged deficiencies (as explained above). 2) As explained in the new grounds of rejections of claims 1, 9 and 15, Ikeda teaches “an uppermost surface of the capping pattern is lower than an upper surface of the upper portion of the conductive contact plug”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN LEE JOHNSON JR whose telephone number is (571)270-3217. The examiner can normally be reached Mon-Fri: 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571)272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.L.J./Examiner, Art Unit 2811
/LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811
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