Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/ Restrictions
Applicant's election of group II: claims 8-20, in the “Response to Election / Restriction Filed - 12/01/2025”, withdrawal of non-elected claim(s) 1-7 is/are acknowledged. This office action considers claims 1-20, in “Claims - 09/27/2022”, pending for prosecution, of which claim(s) 1-7 is/are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(2):
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 8-9, 13-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Preston et al. (US 20220328399 A1 – hereinafter Preston).
Regarding Claim 8, Preston teaches a semiconductor device (see the entire document; Fig. 2; specifically, [0021], and as cited below), comprising:
a front side (Frontside Metal Routing 214 – Fig. 2) comprising a metal wire M2 (M0 – [0021]), and a plurality of power rails (fsv – [0021]) coupled to the M2 (M0);
a back side (Backside Metal Routing 218) comprising a metal wire M1(BM0 – [0021]) and a power delivery network (BM1 – (cell output) – [0043] teaches that backside of the wafer maybe connected to provide power); and
a through silicon via (TSV) (TSV – [0021]) connecting a first power rail (right fav) from the plurality of power rails of the front side with the M1 (BM0) on the back side, the TSV providing power from the power delivery network to the front side (therefore, power from BM1 (cell output) can be provided the backside to Frontside via BV0 to BM0 to bsv to TSV to fav to M0 as shown in Fig. 2).
Regarding Claim 9, Preston teaches the semiconductor device of claim 8, wherein a first set of power rails (top fsv in the Frontside Metal Routing 214 in Fig. 2) from the plurality of power rails is electrically connected directly to a device region of the front side (M2 cell input).
Regarding Claim 13, Preston teaches the semiconductor device of claim 8, wherein the plurality of power rails comprises power supply (VDD) and ground (VSS) terminals (that is, left fsv may be connected to VSS and right fsv may be connected to VDD).
Regarding Claim 14, Preston teaches the semiconductor device of claim 8, wherein the metal wire M2 is discontinuous (Fig. 2 shows M0 is discontinuous).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 10-12, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Preston in view of Chiu et al. (US 20220115324 A1 - hereinafter Chiu).
Regarding Claim 10, Preston teaches claim 8 from which claim 10 depends. But, Preston does not expressly disclose wherein, the first power rail from the plurality of power rails of the front side is wider than a second power rail from the plurality of power rails of the front side.
However, it is well known in the art to have power rails having different widths as is also taught by Chiu (Chiu – Fig. 1 teaches that BM0_VDD 102b is wider than BM0_VSS 102a – [0038]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming wherein, the first power rail from the plurality of power rails of the front side is wider than a second power rail from the plurality of power rails of the front side as taught by Chiu into Preston.
An ordinary artisan would have been motivated to integrate Chiu structure into Preston structure in the manner set forth above for, at least, for the obvious benefit of sufficiently distributing power as needed.
Regarding Claim 11, the combination of Preston and Chiu teaches the semiconductor device of claim 10, wherein the first power rail is a power supply (VDD) (Chiu – Fig.1 shows 102b is BM0_VDD).
Regarding Claim 12, the combination of Preston and Chiu teaches wherein the first power rail comprises a pair of adjacent power rails from the plurality of power rails (Chiu – Fig. 1 shows 102a and 102b are adjacent power rails).
Regarding Claim 15, Preston teaches an electronic device (see the entire document; Fig. 2; specifically, [0021], and as cited below), comprising:
a semiconductor device comprising a front side (Frontside Metal Routing 214 – Fig. 2) comprising a plurality of power rails (fsv – [0021]), wherein the power rails comprise two types of power rails (left fsv and right fsv).
But, Preston does not expressly disclose a first type of power rails that is wider than a second type of power rails.
However, it is well known in the art to have power rails having different widths as is also taught by Chiu (Chiu – Fig. 1 teaches that BM0_VDD 102b is wider than BM0_VSS 102a – [0038]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming wherein, the first power rail from the plurality of power rails of the front side is wider than a second power rail from the plurality of power rails of the front side as taught by Chiu into Preston.
An ordinary artisan would have been motivated to integrate Chiu structure into Preston structure in the manner set forth above for, at least, for the obvious benefit of sufficiently distributing power as needed.
Regarding Claim 16, the combination of Preston and Chiu teaches the electronic device of claim 15, wherein the front side further comprises a metal wire M2 (Preston - M0 – [0021]), wherein the power rails (Preston - fsv – [0021]) are coupled with the metal wire M2 (M0).
Regarding Claim 17, the combination of Preston and Chiu teaches the electronic device of claim 15, wherein the semiconductor device further comprises a back side (Preston - Backside Metal Routing 218) comprising a metal wire M1 (Preston - BM0 – [0021]) and a power delivery network (Preston - BM1 – (cell output) – [0043] teaches that backside of the wafer maybe connected to provide power).
Regarding Claim 18, the combination of Preston and Chiu teaches the electronic device of claim 17, wherein the semiconductor device further comprises a through silicon via (TSV) (Preston - TSV – [0021]) connecting a first type of power rail front side with to the metal wire M1 on the back side (Preston: therefore, power from BM1 (cell output) can be provided the backside to Frontside via BV0 to BM0 to bsv to TSV to fav to M0 as shown in Fig. 2).
Regarding Claim 19, the combination of Preston and Chiu teaches the electronic device of claim 18, wherein the TSV provides power from the power delivery network to the front side (Preston – Fig. 2 teaches TSV provides from BM1 (cell output) to M0 of the Frontside).
Regarding Claim 20, the combination of Preston and Chiu teaches the electronic device of claim 16, wherein the metal wire M2 is discontinuous (Fig. 2 shows M0 is discontinuous).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898