DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed 1/8/2026 have been entered and considered. The amendments to claims 1, 7, and 9 and the cancellation of claim 20 are acknowledged.
In view of the cancellation of claim 20, the rejection under U.S.C. 35 112 is witdrawn.
Response to Arguments
Applicant’s arguments filed 1/8/2026, with respect to the rejection(s) of claim 1 under U.S.C. 35 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yu et al. US 20150287797 A1 and Takami US 20070069285 A1. Yu teaches a first insulator covering a source region, a source sub-region, a drain region, and a drain sub-region. Takami teaches the doping of a channel region with a second doping type.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5-8, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. US 20150287797 A1 (hereinafter referred to as Yu), in view of Takami US 20070069285 A1 (hereinafter referred to as Takami).
Regarding claim 1, Yu teaches
A semiconductor structure (“HVMOS transistor” para. 0027 FIG. 8), comprising:
a substrate (“substrate 300” para. 0020), wherein the substrate comprises an active region (region with “source and drain region 360” and “first doped region 320s”, para. 0022 and 0026), and the active region is provided with a source region of a first doping type and a drain region of the first doping type (“self-aligned source and drain region 360 embedded in the substrate 300 at two sides of the gate structure 340” and are doped with either n-type or p-type, para. 0026);
the substrate further comprises at least one of a first source sub-region of the first doping type or a first drain sub-region of the first doping type (“first doped region 320 in the substrate 300 at two sides of the channel region 310, wherein the first doped region 320 includes a dopant of a first conductive type” para. 0022. “The source and drain region 360 and the first doped region can be the same conductive type” para. 0026. The examiner understands one “first doped region 320” corresponds to a source sub-region or extension and the other to a drain sub-region or extension.);
a first dielectric layer (protruding portion of “gate dielectric layer 342” analogous to the “protruded portion 500a” in FIG. 5, para. 0027 FIG. 8), wherein the first dielectric layer is at least partially provided on the substrate (protruding portion of “gate dielectric layer 342” is on “substrate 300”), and at least part of the first dielectric layer covers a part of the source region and at least part of the first source sub-region, and/or, at least part of the first dielectric layer covers a part of the drain region and at least part of the first drain sub-region (“protruded portion 500a of the gate dielectric layer 500 overlaps the first doped region 320 in the horizontal direction” and is not patterned, leaving a “side wall 342b” of “gate dielectric layer 342” over the “source and drain region 360” formed thereafter, para. 0023 and 0027);
a second dielectric layer (recessed portion of “gate dielectric layer 342” analogous to “recessed portion 500b” in FIG. 5, para. 0027 FIG. 8), wherein the second dielectric layer is provided on the substrate (recessed portion of “gate dielectric layer 342” in on “substrate 300”), the first dielectric layer is connected to the second dielectric layer (recessed portion and protruding portion of “gate dielectric layer 342” are connected), and a thickness of the second dielectric layer is less than a thickness of the first dielectric layer (“recessed portion has a thickness T2 between about 65 and 75 angstroms”, corresponding to the recessed portion of “gate dielectric layer 342”, and “protruded portion 500a has thickness T1, between around 85 and 95 angstroms”, corresponding to the protruding portion of “gate dielectric layer 342”); and
a gate structure (“gate structure 340” para. 0025), wherein orthographic projection of the gate structure on the substrate covers orthographic projection of the second dielectric layer and orthographic projection of the first dielectric layer on the substrate (“gate structure 340” is formed over the protruding and recessed portions of “gate dielectric layer 342”, para. 0027),
However, Yu fails to teach the substrate further comprises a channel region of a second doping type, the channel region is provided below the gate structure and is connected to the source region and the drain region.
Nevertheless, Takami teaches
the substrate (“semiconductor substrate 1” para. 0058 FIG. 1) further comprises a channel region of a second doping type (“P-type channel region 10”, para. 0058), the channel region is provided below the gate structure (structure comprising “gate electrode 5”, “sidewalls 7”, and “third dielectric films 6”, para. 0064) and is connected to the source region and the drain region (arsenic is implanted into “semiconductor substrate 1” around the “gate electrode 5” to form “extension regions 8a and 9a” and “source region 8” and “drain region 9” electrically connected to “P-type channel region 10”, para. 0063-0064).
Yu and Takami teach transistors with insulated gates. While the channel in Yu is not doped, the “channel 10” in Takami is doped with P-type impurities to adjust the threshold voltage of the transistor (Takami para. 0058). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that doping “channel 10” with impurities opposite to the drain and source will raise the threshold voltage of the transistor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure taught in Yu with the channel region of a second doping type as taught in Takami. The doping of the channel adjusts the threshold voltage.
Regarding claim 5, Yu, modified by Takami, teach the semiconductor structure according to claim 1, wherein the gate structure comprises a gate layer (“gate electrode 344” para. 0025) and a protective structure (“spacer 346” para. 0026);
the gate layer is provided on the second dielectric layer (“gate electrode 344” is on the recessed portion of “gate dielectric layer 342”, para. 0024 and 0027), and projection of the gate layer on the substrate has an overlapping region with projection of the first dielectric layer on the substrate (at least “spacer 346” is formed on the protruding portion of “gate dielectric layer 342”, para. 0027); and the protective structure is provided on both sides of the gate layer and covers side surfaces of the gate layer (“spacer 346” covers “side wall 344b” of “gate electrode 344”, para. 0027).
Regarding claim 6, Yu, modified by Takami, teaches the semiconductor structure according to claim 5. Yu fails to teach wherein the protective structure comprises an isolation layer and a protective layer; the isolation layer is provided on a sidewall of the gate layer; and the protective layer is provided on a sidewall of the isolation layer and is away from the gate layer.
Nvertheless, Takami further teaches
wherein the protective structure comprises an isolation layer (“third dielectric film 6” para. 0064 FIG. 1) and a protective layer (“sidewalls 7” para. 0064); the isolation layer is provided on a sidewall of the gate layer (“third dielectric film 6” covers side walls of “gate electrode 5”, para. 0063); and the protective layer is provided on a sidewall of the isolation layer and is away from the gate layer (“I-shaped third dielectric films 6 serving as spacer films are formed between the gate electrode 5 and the sidewalls 7” para. 0064).
Yu and Takami teach insulated gate transistors. The “gate electrode 5” in Takami is covered by “third dielectric film 6” and “sidewalls 7” while the “gate electrode 344” in Yu is covered by “spacer 346”. “Spacer 346” may be a multilayer structure and the examiner understands it may be a multilayer structure similar to that in Takami. The additional layer of dielectric material increases the insulation around the gate electrode, increasing the protection from adjacent conductors. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a multilayer “spacer 346” or an additional insulating layer further isolates the “gate electrode 344”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the semiconductor device taught between Yu and Takami. The layered protective structure improves the insulation around the gate electrode.
Regarding claim 7, Yu, modified by Takami, teach semiconductor structure according to claim 1, wherein the second dielectric layer covers the channel region (the recessed portion of “gate dielectric layer 342” covers “channel region 310” in “substrate 300”, para. 0023).
Regarding claim 8, Yu, modified by Takami, teach the semiconductor structure according to claim 1, wherein the first source sub-region is located at a side of the source region and is close to the drain region (a “first doped region 320” is at a side of a “source and drain region 360” and close to the “source and drain region 360” on the other side of the channel region), the first drain sub-region is located at a side of the drain region and is close to the source region (the other “first doped region 320” is at a side of the other “source and drain region 360” and close to the “source and drain region 360” on the other side of the channel region), a dopant ion concentration of the first source sub-region is less than a dopant ion concentration of the source region, and a dopant ion concentration of the first drain sub- region is less than a dopant ion concentration of the drain region (“a doped concentration of the source and drain region 360 is higher than the doped concentration of the first doped region 320” Yu para. 0026).
Regarding claim 19, Yu, modified by Takami, teach the semiconductor structure according to claim 7, wherein the first dielectric layer is disposed on both sides of the channel region (protruding portion of “gate dielectric layer 342” is formed on both sides of “channel region 310” overlapping the “first doped region 320”, para. 0023 and 0027), the bottom of the first dielectric layer is higher than the bottom of the channel region (the bottom of the protruding portion of “gate dielectric layer 342” is formed over “substrate 300” while the “channel region 10”, as modified by Takami, is formed in the “substrate 300” such that a bottom of “channel region 10” is below the surface of “substrate 300”).
Allowable Subject Matter
Claims 3-4, 18, and 21-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the most relevant prior art Krivokapic fails to teach wherein the first dielectric layer is partially provided on the substrate, a top of the first dielectric layer is flush with a top of the second dielectric layer, and a bottom of the first dielectric layer is lower than a bottom of the second dielectric layer. Therefore, claim 3 is considered to contain allowable subject matter.
Claims 18, 21, and 22 are objected based on their dependency on claim 3.
Regarding claim 4, Yu teaches the “gate dielectric layer 342” of a same material and having a protruded portion with a greater thickness than the recessed portion. The greater thickness of the protruded portion that surrounds the recessed portion enables a higher sustained breakdown voltage and prevention of gate induced drain leakage (Yu para. 0029). On the other hand, Pan et al. US 6297106 B1 teaches the formation of a low-K dielectric on the edges of the gate structure so that overlap capacitance is reduced (Pan col 7 lines 47-50). Although the specific material of “gate dielectric layer 342” in Yu is not specified, it is understood that the material of the recessed and protruding portions are the same oxide, nitride, or high-K dielectric (Yu para. 0023). A reduction in the dielectric constant of the protruding portion of “gate dielectric layer 342” may affect the desired ability to sustain a high breakdown voltage and gate induced drain leakage prevention. It would not have been obvious to apply the teachings of Pan into the device of Yu. Claim 4 is considered to contain allowable subject matter.
Conclusion
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898