Attorney Docket Number: AE0681-US
Filing Date: 9/27/2022
Inventors: Sharma et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendments filed 1/20/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first
inventor to file provisions of the AIA . In the event the determination of the status of the application as
subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing
from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art
relied upon, and the rationale supporting the rejection, would be the same under either status.
Acknowledgement
The Amendments filed on 1/20/2026, responding to the Office action mailed 10/27/2025,
has been entered. Applicant amended claims 1-9, 11, 17, and 20. Applicant cancelled claim 10 and added claim 21. The present Office action is made with all the suggested amendments being fully
considered.
Response to Amendment
Applicant’s amendments to the claims have overcome the respective claim objections and claim
rejections under 35 U.S.C. 103, as previously formulated in the Non-Final Office action mailed on 10/27/2025. Accordingly, all previous specification objections and claim rejections are hereby withdrawn. Accordingly, pending in this application are claims 1-9 and 11-21. New grounds of rejections are presented below, however, as necessitated by applicant’s amendments to the claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites the limitation "third interconnect region" in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “third interconnect region” will be construed to recite “interconnect transition region”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-9, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20220093540 A1) in view of Mahnkopf (US 20190393130 A1).
Regarding claim 1, Zhang (see, e.g., fig. 8) shows most aspects of the instant invention, including an integrated circuit device comprising:
a first interconnect region (e.g., plurality of second auxiliary straight wire portion 3003) comprising:
a first plurality of metal lines (e.g., plurality of second auxiliary straight wires 3003) arranged at a first pitch (see, e.g., distance between individual second auxiliary straight wires 3003) and the metal lines (e.g., second auxiliary straight wires 3003) extending in a first direction (e.g., y-direction);
a second interconnect region (e.g., plurality of first auxiliary connection wires 3001) comprising:
a second plurality of metal lines (e.g., first auxiliary connection wires 3001) arranged at a second pitch (see, e.g., distance between individual first auxiliary connection wires 3001), the second pitch (e.g., pitch between first auxiliary connection wires 3001) less than the first pitch (e.g., pitch between second auxiliary straight wires 3003);
an interconnect transition region (e.g., plurality of auxiliary oblique wires 3002)
comprising:
a plurality of angled metal lines (e.g., plurality of auxiliary oblique wires 3002), wherein one of the angled metal lines (e.g., plurality of auxiliary oblique wires 3002) is coupled to one of the first plurality of metal lines (e.g., plurality of second auxiliary straight wires 3003) and to one of the second plurality of metal lines (e.g., plurality of second auxiliary straight wires 3003), the one of the angled metal lines (e.g., plurality of auxiliary oblique wires 3002) extends in a second direction (e.g., diagonal direction, see fig. 8).
Zhang (see, e.g., fig. 8), however, fails to explicitly show an angle between the first direction and the second direction is between 10 degrees and 80 degrees.
However, Zhang (see, e.g., fig. 8) shows the mid-region metal lines are angled substantially distinct from 0 or 90 degrees (the diagonal shape is very pronounced, thus substantially close to 45 degrees). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to adopt this approximate 45 degree angle within the substantially diagonal configuration, as the magnitude of the angle becomes a design choice based on the layout and connectivity requirements.
Zhang (see, e.g., fig. 8), however, fails to explicitly teach the first interconnect region, the second interconnect region, and the interconnect transition region are of a metal layer of a metallization stack comprising a plurality of metal layers.
Mahnkopf (see, e.g., fig. 1A), in a similar device to Zhang, teaches a first interconnect region (e.g., interconnect layer 110) of a metal layer (e.g., metallization stack 119) of a metallization stack (e.g., metallization stack 119 + contacts 124), a second interconnect region (e.g., interconnect layer 106) of the metal layer (e.g., metallization stack 119), and a interconnect transition region (e.g., interconnect layer 108) of the metal layer (e.g., metallization stack 119).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the interconnect-metallization configuration of Mahnkopf onto the interconnect setup of Zhang, in order to achieve the expected result of providing a metallization interface for the interconnection setup to be utilized within a larger integrated circuit configuration.
Regarding claim 2, Zhang (see, e.g., fig. 8) shows the interconnect transition region (e.g., plurality of auxiliary oblique wires 3002) comprising a second angled metal line (e.g., rightmost auxiliary oblique wire 3002) coupled to a second (e.g., rightmost second auxiliary straight wire 3003) of the first plurality of metal lines (e.g., plurality of second auxiliary straight wires 3003) and a second (e.g., rightmost first auxiliary connection wires 3001) of the second plurality of metal lines (e.g., plurality of first auxiliary connection wires 3001), the second angled metal line (e.g., rightmost auxiliary oblique wire 3002) extending in a third direction (e.g., substantial diagonal direction of rightmost oblique wire 3002, see fig. 8), and a second angle (e.g., angle between first direction) between the first direction (e.g., y-direction) and the third direction (e.g., substantial diagonal direction of rightmost oblique wire 3002, see fig. 8) is different (note that the pitches between the wires 3001 and 3003 differ, so the angular difference between the wires must be at least slightly different) from the first angle (e.g., substantially diagonal angle, approximately 45 degrees, see fig. 8).
Regarding claim 3, Zhang (see, e.g., fig. 8) doesn’t explicitly show a difference between the first angle and the second angle is at least 1°.
However, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to adopt a difference of at least 1°, as the magnitude of the angle becomes a design choice based on the layout and connectivity requirements, and the difference between the angles decides the difference in pitch size between the top and bottom of the plurality of metal line arrangements.
Regarding claim 4, Zhang (see, e.g., fig. 8) doesn’t explicitly show a difference between the first angle and the second angle is less than 30°.
However, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to adopt a difference of less than 30°, as the magnitude of the angle becomes a design choice based on the layout and connectivity requirements, and the difference between the angles decides the difference in pitch size between the top and bottom of the plurality of metal line arrangements.
Regarding claim 5, Zhang (see, e.g., fig. 8) doesn’t explicitly show wherein the first pitch is at least twice the second pitch.
However, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to adopt a ratio between pitches of at least 2:1, as this pitch depends on the angle magnitudes between different individual angled metal lines, and the magnitude of each angle becomes a design choice based on the layout and connectivity requirements.
Regarding claim 8, Mahnkopf (see, e.g., fig. 1A) teaches a plurality of metal lines (e.g., metal structure of interconnect layer 108) not coupled to a metal line (e.g., note the interconnect structures 128 within 108 that aren’t coupled to additional circuitry).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the non-coupled metal line configuration of Mahnkopf onto at least one metal line within the setup of Zhang, in order to achieve the expected result of providing additional available interconnect structures for future modification or fabrication as desired.
Additionally, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to duplicate at least one of the second plurality of metal lines of Zhang free from directly coupling to an angled metal line, to achieve the expected result of providing additional available interconnect structures on the second substrate for potential connectivity in order to connect with any other dies or boards formed later within the fabrication process, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. In re Harza 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04
Regarding claim 9, Zhang (see, e.g., fig. 8) shows the first plurality of metal lines (e.g., plurality of second auxiliary straight wires 3003) have a first width (e.g., width of plurality of second auxiliary straight wires 3003) and the second plurality of metal lines (e.g., first auxiliary connection wires 3001) have a second width (e.g., width of plurality of first auxiliary connection wires 3001), the second width (e.g., width of plurality of first auxiliary connection wires 3001) less (note that the second pitch size is less than the first pitch size, but there are no new wires in the arrangement, so the width in the second plurality has decreased) than the first width (e.g., width of plurality of second auxiliary straight wires 3003).
Regarding claim 21, Mahnkopf (see, e.g., fig. 1A) teaches wherein the metal layer (e.g., metallization stack 119) across a plane parallel to a support structure (e.g., substrate 102), and the first interconnect region (e.g., interconnect layer 110), the second interconnect region (e.g., interconnect layer 106), and the interconnect transition region (e.g., interconnect layer 106) are within the plane of the metal layer (e.g., metallization stack 119).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the support structure of Mahnkopf parallel to the metal layer plane of Zhang in view of Mahnkopf, in order to achieve the expected result of providing a physical support foundation/structure beneath the metal layer and interconnect configuration makeup as desired.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Mahnkopf further in view of Sun (US 20220270976 A1).
Regarding claim 6, Zhang in view of Mahnkopf fails to teach a device layer having a plurality of semiconductor devices, wherein one of the semiconductor devices is coupled to one of the second plurality of metal lines.
Sun (see, e.g., fig. 39), in a similar device to Zhang in view of Mahnkopf, teaches a device layer (e.g., device layer 1604) having a plurality of semiconductor devices (see, e.g., paragraphs 91-95), wherein one (e.g., transistor 1640) of the semiconductor devices (see, e.g., paragraphs 91-95) is coupled to a plurality of metal lines (e.g., interconnect layers 1628).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the device layer of Sun within the device of Zhang in view of Mahnkopf coupled to the second plurality metal lines, in order to achieve the expected result of providing individual components, like transistors, an electrical pathway configuration.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Mahnkopf further in view of Sun and Brun (US 20170186707 A1).
Regarding claim 7, Zhang in view of Mahnkopf further in view of Sun fails to teach wherein the second interconnect region comprises a dummy metal line, the dummy metal line not coupled to a semiconductor device.
Brun (see, e.g., fig. 2), in a similar device to Zhang in view of Mahnkopf further in view of Sun, teaches an interconnect region (e.g., interconnect structure 254 + dummy structures 256) comprises a dummy metal line (e.g., dummy structure 256) not coupled to a semiconductor device (see, e.g., paragraph 30 “…as well as dummy structures 256 electrically decoupled from any such vias…).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dummy structure of Brun within the interconnect setup of Zhang in view of Mahnkopf further in view of Sun, in order to achieve the expected result of improving the uniform metal density across the chip during manufacturing.
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Tadayon (US 20190212366 A1) in view of Mahnkopf.
Regarding claim 11, Tadayon (see, e.g., fig. 1B) shows most aspects of the instant invention including a device comprising:
A first interconnect region (e.g., plurality of interconnect structures 140) comprising:
a first plurality of metal lines (e.g., interconnect structures 140a + 140b + 140c) arranged at a pitch (e.g., pitch between structures 140a, 140b, and 140c) and the metal lines (e.g., interconnect structures 140a + 140b + 140c) extending in a first direction (e.g., vertical direction);
A second interconnect region (e.g., plurality of vias 208 + terminals 210) comprising:
a second plurality of metal lines (e.g., vias 208 and terminals 210 coupled with the interconnect structures 140a + 140b + 140c) arranged at the pitch (e.g., note that the test probes/tester interconnect structures 214 are angled diagonally but straight and parallel (see paragraph 19) to one another, so the pitch between the sets of vias 208 and terminals 210 is equal to the pitch of the interconnect structures they’re respectively coupled to…), the second plurality of metal lines (e.g., vias 208 and terminals 210 coupled with the interconnect structures 140a + 140b + 140c) extending in the first direction (e.g., vertical direction);
A third interconnect region (e.g., test probes 214) comprising a plurality of angled metal lines (e.g., test probe 214a + test probe 214b), wherein one of the angled metal lines (e.g., test probe 214a) is coupled (e.g., via the contact tips 226 + paragraph 29 “…the contact tips 226 comprise conductive material…”) to one (e.g., interconnect structure 140a) of the first plurality of metal lines (e.g., interconnect structures 140a + 140b + 140c) and to one (e.g., terminal 210a) of the second plurality of metal lines (e.g., vias 208 and terminals 210 coupled with the interconnect structures 140a + 140b + 140c), the one of the angled metal lines (e.g., test probe 214a) extends in a second direction (e.g., diagonal direction, see fig. 1B);
Tadayon (see, e.g., fig. 1B), however, fails to explicitly show an angle between the first direction and the second direction is between 10 degrees and 80 degrees.
However, Tadayon (see, e.g., fig. 1B) shows the mid-region metal lines are angled substantially distinct from 0 or 90 degrees (the diagonal shape is very pronounced, thus substantially close to 45 degrees). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to adopt this approximate 45 degree angle within the substantially diagonal configuration, as the magnitude of the angle becomes a design choice based on the layout and connectivity requirements.
Tadayon (see, e.g., fig. 8), however, fails to explicitly teach the first interconnect region, the second interconnect region, and the third transition region are of a metal layer of a metallization stack comprising a plurality of metal layers.
Mahnkopf (see, e.g., fig. 1A), in a similar device to Zhang, teaches a first interconnect region (e.g., interconnect layer 110) of a metal layer (e.g., metallization stack 119) of a metallization stack (e.g., metallization stack 119 + contacts 124), a second interconnect region (e.g., interconnect layer 106) of the metal layer (e.g., metallization stack 119), and a third transition region (e.g., interconnect layer 108) of the metal layer (e.g., metallization stack 119).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the interconnect-metallization configuration of Mahnkopf onto the interconnect setup of Tadayon, in order to achieve the expected result of providing a metallization interface for the interconnection setup to be utilized within a larger integrated circuit configuration.
Regarding claim 12, Tadayon (see, e.g., fig. 1B) shows the third interconnect region (e.g., test probes 214) comprising a second angled metal line (e.g., test probe 214b) coupled to a second (e.g., interconnect structure 140b) of the first plurality of metal lines (e.g., interconnect structures 140a + 140b + 140c) and a second (e.g., via 208a) of the second plurality of metal lines (e.g., vias 208 and terminals 210 coupled with the interconnect structures 140a + 140b + 140c), the second angled metal line (e.g., test probe 214b) extending in the second direction (e.g., diagonal direction, see fig. 1B).
Regarding claim 13, Tadayon (see, e.g., fig. 1B) doesn’t explicitly show the angle between the first direction and the second direction is between 20 degrees and 50 degrees.
However, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to adopt the approximate 45 degree angle of Tadayon, as the magnitude of the angle becomes a design choice based on the layout and connectivity requirements.
Regarding claim 14, Tadayon (see, e.g., fig. 1B) doesn’t explicitly show wherein the one of the first plurality of metal lines and the one of the second plurality of metal lines are offset by the pitch.
However, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to increase the angle of magnitude of the angled metal line of Tadayon, as the magnitude of the angle becomes a design choice based on the layout and connectivity requirements, and adjusting the angle would couple the first plurality of metal lines and the second plurality of metal lines at an offset distance of the pitch.
Regarding claim 15, Tadayon (see, e.g., fig. 1B) doesn’t explicitly show wherein the one of the first plurality of metal lines and the one of the second plurality of metal lines are offset by twice the pitch.
However, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to increase the angle of magnitude of the angled metal line of Tadayon, as the magnitude of the angle becomes a design choice based on the layout and connectivity requirements, and adjusting the angle would couple the first plurality of metal lines and the second plurality of metal lines at an offset distance of twice the pitch.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Tadayon in view of Mahnkopf further in view of Sun.
Regarding claim 16, Tadayon in view of Mahnkopf fails to teach a device layer having a plurality of semiconductor devices, wherein one of the semiconductor devices is coupled to one of the second plurality of metal lines.
Sun (see, e.g., fig. 39), in a similar device to Tadayon in view of Mahnkopf, teaches a device layer (e.g., device layer 1604) having a plurality of semiconductor devices (see, e.g., paragraphs 91-95), wherein one (e.g., transistor 1640) of the semiconductor devices (see, e.g., paragraphs 91-95) is coupled to a plurality of metal lines (e.g., interconnect layers 1628).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the device layer of Sun within the device of Tadayon in view of Mahnkopf coupled to the second plurality of metal lines, in order to achieve the expected result of providing individual components, like transistors, an electrical pathway configuration.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tadayon in view of Liu (US 20210384134 A1) further in view of Elsherbini (US 20200273840 A1).
Regarding claim 17, Tadayon (see, e.g., fig. 1B) shows most aspects of the instant invention including an integrated circuit (IC) package comprising:
A first die (e.g., DUT 101 + paragraph 41 “The DUT 101 may be…a IC die or chip…”) having an edge (e.g., sidewall of DUT 101, see annotated fig. 1 below) and a stack of interconnect layers (e.g., plurality of interconnect layers 140); and
A substrate (e.g., substrate 202) coupled (e.g., via the test probes 214 and vias 208) to the first die (e.g., DUT 101 + paragraph 41 “The DUT 101 may be…a IC die or chip…”).
A third substrate (e.g., space transformer 236) coupled (e.g., via the terminals 230) to the first die (e.g., DUT 101 + paragraph 41 “The DUT 101 may be…a IC die or chip…”)
Wherein an interconnect layer (e.g., selected interconnect plurality of greater interconnect plurality 140, see annotated fig. 1) of the stack of interconnect layers (e.g., plurality of interconnect layers 140) of the first die (e.g., DUT 101 + paragraph 41 “The DUT 101 may be…a IC die or chip…”), the interconnect layer (e.g., selected interconnect plurality of greater interconnect plurality 140, see annotated fig. 1) comprising:
A first interconnect portion (e.g., interconnect structures 140a + 140b + 140c) extending in a first direction (e.g., vertical direction), the first direction (e.g., vertical direction) parallel to the edge (e.g., sidewall of DUT 101, see annotated fig. 1 below) of the first die (e.g., DUT 101 + paragraph 41 “The DUT 101 may be…a IC die or chip…”);
a second interconnect portion (e.g., test probes 214) coupled (e.g., via the contact tips 226 + paragraph 29 “…the contact tips 226 comprise conductive material…”) to the first interconnect portion (e.g., interconnect structures 140a + 140b + 140c), the second interconnect portion (e.g., test probes 214) extending in a second direction (e.g., diagonal direction, see fig. 1B).
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Annotated Fig. 1
Tadayon (see, e.g., fig. 1B), however, fails to explicitly show an angle between the first direction and the second direction is between 10 degrees and 80 degrees.
However, Tadayon (see, e.g., fig. 1B) shows the mid-region metal lines are angled substantially distinct from 0 or 90 degrees (the diagonal shape is very pronounced, thus substantially close to 45 degrees). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to adopt this approximate 45 degree angle within the substantially diagonal configuration, as the magnitude of the angle becomes a design choice based on the layout and connectivity requirements.
Tadayon (see, e.g., fig. 1B), however, fails to show the second substrate is a die and the third substrate is a die, while it also fails to show the interconnect layer is in the first die (as opposed to on the first die).
Liu (see, e.g., fig. 9), in a similar device to Tadayon, teaches a substrate (e.g., semiconductor die 1302) can be a logic die (see, e.g., paragraph 18 “…semiconductor dies 1302…can be logic dies…”), while it also teaches an interconnect (e.g., tall interconnect 104) in a RDL (e.g., RDL 103).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the interconnect configuration of Liu within the die of Tadayon, in order to allow the easier and more accessible contact between the interconnect and other circuits or components of the die. It also would have been obvious to one of ordinary skill in the art to include the logic die (hereinafter second die 202) of Liu within the second substrate of Tadayon, in order to achieve the expected result of providing device data processing capabilities electrically coupled with the first die.
Tadayon in view of Liu, however, fails to teach the third substrate is a die.
Elsherbini (see, e.g., figs. 12-16), in a similar device to Tadayon in view of Liu, teaches a substrate (e.g., dies 114) can be an input/output die (see, e.g., paragraph 123 “…the different dies 114 may include any suitable circuitry (e.g., the dies 114A may be active or passive dies, and the dies 114B may include input/output circuitry (e.g., in-package input/output circuitry or external input/output circuitry, such as Double Data Rate or Peripheral Component Interconnect Express circuitry), high bandwidth memory, and/or enhanced dynamic random access memory (EDRAM)). In some embodiments, one or more of the dies 114 may include memory devices (e.g., random access memory), I/O drivers, high bandwidth memory, accelerator circuitry (e.g., artificial intelligence accelerator circuitry), an application-specific integrated circuit (e.g., an artificial intelligence application-specific integrated circuit), a field programmable gate array, a processor core, a central processing unit, a graphics processing unit, or any suitable circuitry.”)
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the input/output die (hereinafter third die 236) of Elsherbini within the third substrate of Tadayon in view of Liu, in order to achieve the expected result of providing memory control and express circuitry electrically coupled with the second die and the first die.
Regarding claim 18, Tadayon (see, e.g., fig. 1B) shows an interposer (e.g., interconnect levels 109 + paragraph 32 “The interconnect levels 109 include, for example, traces, routing structures, redistribution layers, etc. The interconnect levels 109 include conductive material, such as copper, nickel, etc”) between the first die (e.g., DUT 101 + paragraph 41 “The DUT 101 may be…a IC die or chip…”) and the second die (e.g., second die 202).
Regarding claim 19, Liu teaches a die (e.g., semiconductor die 1302) can be a logic device (see, e.g., paragraph 18 “…semiconductor dies 1302…can be logic dies…”).
Accordingly, would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the logic die of Liu within the second die of Tadayon, in order to achieve the expected result of providing device data processing capabilities electrically coupled with the first die.
Regarding claim 20, Elsherbini (see, e.g., figs. 12-16) teaches a die (e.g., dies 114) can be an input/output die (see, e.g., paragraph 123 “…the different dies 114 may include any suitable circuitry (e.g., the dies 114A may be active or passive dies, and the dies 114B may include input/output circuitry (e.g., in-package input/output circuitry or external input/output circuitry, such as Double Data Rate or Peripheral Component Interconnect Express circuitry), high bandwidth memory, and/or enhanced dynamic random access memory (EDRAM)). In some embodiments, one or more of the dies 114 may include memory devices (e.g., random access memory), I/O drivers, high bandwidth memory, accelerator circuitry (e.g., artificial intelligence accelerator circuitry), an application-specific integrated circuit (e.g., an artificial intelligence application-specific integrated circuit), a field programmable gate array, a processor core, a central processing unit, a graphics processing unit, or any suitable circuitry.”)
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the input/output die of Elsherbini within the third die of Tadayon in view of Liu, in order to achieve the expected result of providing memory control and express circuitry electrically coupled with the second die and the first die.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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