DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 04/27/2026 amendments of claims 1 and 12 have been noted and entered.
The 04/27/2026 addition of new claims 21-24 has been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 6-7, filed 04/27/2026, with respect to the rejection(s) of claim(s) 1-4 and 12-14 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Poechmueller, US 20050007804 A1 (Poechmueller).
New Grounds of Rejection
New grounds of rejection, prior art reference Poechmueller, US 20050007804 A1 (Poechmueller) appears below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Poechmueller, US 20050007804 A1 (Poechmueller) in view of Dokania et al, US 11696451 B1 (Dokania).
Regarding claim 1; Poechmueller teaches an integrated circuit (IC) device comprising:
a device layer (Poechmueller: Annotated Fig (2B) shared in this OA: device layer containing the transistors 24 and capacitors 22 and bitline contacts 23) comprising an access transistor (24) comprising a source (28) or drain (38),
the source (28) coupled to a first conductive structure (21) over the source (28) or drain and a second conductive structure (23) under the source or drain (38);
a first plurality of capacitor layers (22) over the device layer (device layer containing the transistors 24 and capacitors 22 and bitline contacts 23), the first plurality of capacitor layers (22) comprising a first plurality of capacitors (22),
each of the first plurality of capacitors (22) coupled to the first conductive structure (21); and
a second plurality of capacitor layers under the device layer, the second plurality of capacitor layers comprising a second plurality of capacitors, each of the second plurality of capacitors coupled to the second conductive structure (23).
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Poechmueller does not teach a second plurality of capacitor layers under the device layer, the second plurality of capacitor layers comprising a second plurality of capacitors, each of the second plurality of capacitors coupled to the second conductive structure.
Dokania teaches a second plurality of capacitor layers (Dokania: Annotated Fig (7A) shared in this OA: capacitor layers containing capacitors Cfe1…Cfe3) under the device layer (layer containing the transistors MN1), the second plurality of capacitor layers (capacitor layers containing capacitors Cfe1…Cfe3) comprising a second plurality of capacitors (Cfe1… Cfe3), each of the second plurality of capacitors (Cfe1… Cfe3) coupled to the second conductive structure (sn1+M2).
Poechmueller and Dokania are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Poechmueller by using the capacitor layers below the device layer as disclosed in Dokania to improve the performance of the transistors in the memory device by providing more stable biasing and faster switching times for the transistor thus leading to a more reliable device with faster performance characteristics which are vital for memory devices.
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Regarding claim 2; Poechmueller in view of Dokania teaches all the limitations of the IC device of claim 1.
However, Poechmueller does not teach wherein a first via is coupled to a first capacitor layer of the second plurality of capacitor layers, and a second via is coupled to a second capacitor layer of the second plurality of capacitor layers.
Dokania teaches wherein a first via (Dokania: Annotated Fig (7A) shared in this OA: sn3, Via1) is coupled to a first capacitor layer (capacitor layer containing capacitors (Cfe1)) of the second plurality of capacitor layers (capacitor layers containing capacitors (Cfe1… Cfe3) under the transistor layer), and a second via (Via2) is coupled to a second capacitor layer (capacitor layer containing capacitors (Cfe2)) of the second plurality of capacitor layers (capacitor layers containing capacitors (Cfe1… Cfe3) under the transistor layer).
Poechmueller and Dokania are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Poechmueller by using the vias connecting the different capacitor layers as disclosed in Dokania to make establishing electrical connections in the device easier leading to a more efficient device production process.
Claims 12-14, 21 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Poechmueller, US 20050007804 A1 (Poechmueller) in view of Dokania et al, US 11696451 B1 (Dokania) in further view of Haratipour et al, US 20220208778 A1 (Haratipour).
Regarding claim 12; Poechmueller teaches a memory device comprising:
an access transistor (Poechmueller: Annotated Fig (2B) shared in this OA:24);
a first conductive structure (21) over the access transistor (24) and coupled to a terminal (28) of the access transistor (24);
a second conductive structure (23) under the access transistor (24) and coupled to the terminal (38) of the access transistor (24);
a first plurality of capacitors (22) over the access transistor (24), the first plurality of capacitors coupled to the first conductive structure (21), and
each of the first plurality of capacitors coupled to a respective one of a first plurality of platelines; and
a second plurality of capacitors under the access transistor, the second plurality of capacitors coupled to the second conductive structure, and
each of the second plurality of capacitors coupled to a respective one of a second plurality of platelines
Poechmueller does not teach a second plurality of capacitors under the access transistor, the second plurality of capacitors coupled to the second conductive structure, and each of the second plurality of capacitors coupled to a respective one of a second plurality of platelines.
Dokania teaches a second plurality of capacitors (Poechmueller: Annotated Fig (7A): layers of capacitors Cfe1… Cfe3) under the access transistor (MN1), the second plurality of capacitors (Cfe1… Cfe3) coupled to the second conductive structure (sn1), and each of the second plurality of capacitors (Cfe1… Cfe3) coupled to a respective one of a second plurality of platelines (PL0_1… PL0_4).
Poechmueller and Dokania are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Poechmueller by using the extra layers of capacitors as disclosed in Dokania to improve the stability of biasing for the transistors leading to faster switching times and thus a better performing memory device.
Poechmueller in view of Dokania does not teach each of the first plurality of capacitors coupled to a respective one of a first plurality of platelines.
Haratipour teaches each of the first plurality of capacitors (Haratipour: Annotated Fig (2) shared in this OA: 202) coupled to a respective one of a first plurality of platelines (PL1… PL4).
Poechmueller in view of Dokania and Haratipour are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Poechmueller in view of Dokania by using the second plurality of platelines below the access transistor as disclosed by Haratipour to improve the performance and reliability of the memory device.
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Regarding claim 13; Poechmueller in view of Dokania in further view of Haratipour teaches all the limitations of the IC device of claim 12.
Poechmueller in view of Dokania does not teach wherein a first plateline of the second plurality of platelines is coupled to a first via, and a second plateline of the second plurality of platelines is coupled to a second via.
Haratipour teaches wherein a first plateline (Haratipour: Annotated Fig (1) shared in this OA: PL1) of the second plurality of platelines (PL1… PL4) is coupled to a first via (126), and a second plateline (PL2) of the second plurality of platelines (PL1… PL4) is coupled to a second via (126).
Poechmueller in view of Dokania and Haratipour are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Poechmueller in view of Dokania by using the vias connected to the second plurality of platelines as disclosed in Haratipour to make establishing electrical connections within the device easier thus leading to a more efficient device manufacturing process.
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Regarding claim 14; Poechmueller in view of Dokania in further view of Haratipour teaches all the limitations of the IC device of claim 13.
However, Poechmueller in view of Dokania does not teach wherein the first via extends through a layer of the memory device comprising the access transistor, and the second via extends through the layer of the memory device comprising the access transistor.
Haratipour teaches wherein the first via (Haratipour: Annotated Fig (1) shared in this OA: 126) extends through a layer of the memory device (Layer of the memory device) comprising the access transistor (106), and the second via (126) extends through the layer of the memory device (Layer of the memory device) comprising the access transistor (126).
Poechmueller in view of Dokania and Haratipour are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Poechmueller in view of Dokania by using the vias going through the device layer as disclosed in Haratipour to make establishing electrical connections within the device easier thus leading to a more efficient device manufacturing process.
Regarding claim 21; Poechmueller in view of Dokania teaches all the limitations of The IC device of claim 1.
Poechmueller teaches wherein the first conductive structure (Poechmueller: Annotated Fig (2B) shared in this OA: 21) extends through the first plurality of capacitor layers (22), and the second conductive structure extends through the second plurality of capacitor layers.
Poechmueller in view of Dokania does not teach the second conductive structure extends through the second plurality of capacitor layers.
Haratipour teaches the second conductive structure (Haratipour: Fig (1): 120) extends through the second plurality of capacitor layers (102).
Poechmueller in view of Dokania and Haratipour are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Poechmueller in view of Dokania by extending the second conductive structure through the second plurality of capacitor layers as disclosed in Haratipour to synchronize the control of the capacitors leading to shorter processing times and thus a better performing device.
Regarding claim 24; Poechmueller in view of Dokania in further view of Haratipour teaches all the limitations of the memory device of claim 12.
Further, Poechmueller teaches wherein the terminal (Poechmueller: Annotated Fig (7A) shared in this OA: 28) of the access transistor (24) is a source or drain terminal, the first conductive structure (21) is in contact with a first source (28) or drain contact (28) of the access transistor (24) on an upper side of the access transistor (24), and the second conductive structure (23) is in contact with a second source or drain (38) contact of the access transistor (24) on a lower side of the access transistor (24).
Claims 3-4 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Poechmueller, US 20050007804 A1 (Poechmueller) in view of Dokania et al, US 11696451 B1 (Dokania) in further view of Onuki et al, US 20220093600 A1 (Onuki).
Regarding claim 3; Poechmueller in view of Dokania teaches all the limitations of the IC device of claim 2.
However, Poechmueller in view of Dokania does not teach wherein the first via extends through the first plurality of capacitor layers and through the device layer.
Onuki teaches wherein the first via (Onuki: Fig (13): 426) extends through the first plurality of capacitor layers (layers containing capacitors (292)) and through the device layer (the layer containing the transistor (413_1)).
Poechmueller in view of Dokania and Onuki are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Poechmueller in view of Dokania in view of Haratipour by using the first via which extends through the first plurality of the capacitor layers and the device layer as disclosed in Onuki to make establishing electrical connections in the device easier leading to a more efficient device production process.
Regarding claim 4; Poechmueller in view of Dokania in further view of Onuki teach all the limitations of the IC device of claim 3.
However, Poechmueller in view of Dokania does not teach wherein the second via extends through the first plurality of capacitor layers, through the device layer, and through the first capacitor layer.
Onuki teaches wherein the second via (Onuki: Fig (13): 430) extends through the first plurality of capacitor layers (layers containing capacitors (292)), through the device layer (413_1), and through the first capacitor layer (415_1).
Poechmueller in view of Dokania and Onuki are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Poechmueller in view of Dokania in further view of Haratipour by using the second via which extends through the first plurality of the capacitor layers and the device layer and the first capacitor layer as disclosed in Onuki to make establishing electrical connections in the device easier leading to a more efficient device production process.
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Regarding claim 23; Poechmueller in view of Dokania in further view of Onuki teaches all the limitations of the IC device of claim 3.
Poechmueller in view of Dokania does not teach wherein the first via tapers from a first end over the device layer to a second end under the device layer.
Onuki teaches wherein the first via (Onuki: Fig (13): 424) tapers from a first end over the device layer (415_1) to a second end under the device layer (415_1).
Poechmueller in view of Dokania and Onuki are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Poechmueller in view of Dokania by constructing the first via such that it tapers as disclosed in Onuki to free more space in the device layers for more components and connections leading to a better performing and faster device.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Poechmueller, US 20050007804 A1 (Poechmueller) in view of Dokania et al, US 11696451 B1 (Dokania) in further view of Onuki et al, US 20220093600 A1 (Onuki) in further view of Haratipour et al, US 20220208778 A1 (Haratipour).
Regarding claim 22; Poechmeuller in view of Dokania in further view of Onuki teaches all the limitations of The IC device of claim 3.
Poechmueller in view of Dokania in further view of Onuki does not teach wherein the first via is in contact with a plateline of a plurality of capacitors in the first capacitor layer.
Haratipour teaches wherein the first via (Haratipour: Fig (2): 226) is in contact with a plateline (PL1) of a plurality of capacitors (202) in the first capacitor layer (layer containing capacitors 202).
Poechmueller in view of Dokania in further view of Onuki and Haratipour are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Poechmueller in view of Dokania by constructing the first via in contact with a plateline as disclosed in Haratipour to make establishing electrical connections within the device easier leading to more efficient and reliable device manufacturing process.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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