DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 drawn to Figure (7) in the reply filed on 01/08/2026 is acknowledged.
Claims 5-11 and 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/08/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Dokania et al, US 11696451 B1 (Dokania) in view of Haratipour et al, US 20220208778 A1 (Haratipour).
Regarding claim 1; Dokania teaches an integrated circuit (IC) device comprising: a device layer (device layer containing the transistor MN1 – see Fig (7A) of Dokania shared in this OA for convenience) comprising an access transistor (MN1); a first plurality of capacitor layers (capacitor layers containing capacitors (Cfe1)…(Cfe3)) over the device layer (device layer containing the transistor MN1 – see Fig (7A) of Dokania shared in this OA), the first plurality of capacitor layers (capacitor layers containing capacitors (Cfe1)…(Cfe3)) comprising a first plurality of capacitors ((Cfe1)…(Cfe3)), each of the first plurality of capacitors ((Cfe1)…(Cfe3)) coupled to a source (Source contact – see Fig (7A) of Dokania shared in this OA) or drain of the access transistor (MN1).
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Dokania does not teach a second plurality of capacitor layers under the device layer, the second plurality of capacitor layers comprising a second plurality of capacitors, each of the second plurality of capacitors coupled to the source or drain of the access transistor.
However, Haratipour teaches a second plurality of capacitor layers (layers containing capacitors (202) under the device layer (layer containing transistor (206) – see Fig (2) of Haratipour shared in this OA), the second plurality of capacitor layers (layer containing transistor (206) – see Fig (2) of Haratipour shared in this OA) comprising a second plurality of capacitors (202), each of the second plurality of capacitors (202) coupled to the source or drain (208A) of the access transistor (206). Dokania and Haratipour are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Dokania by using the capacitor layers below the device layer as disclosed in Haratipour to improve the performance of the transistors in the memory device thus leading to a more reliable device.
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Regarding claim 2; Dokania in view of Haratipour teaches all the limitations of claim 1.
However, Dokania does not teach wherein a first via is coupled to a first capacitor layer of the second plurality of capacitor layers, and a second via is coupled to a second capacitor layer of the second plurality of capacitor layers.
Haratipour teaches wherein a first via (226) is coupled to a first capacitor layer (capacitor layer containing capacitors (202)) of the second plurality of capacitor layers (capacitor layers containing capacitors (202) below the device layer), and a second via (226) is coupled to a second capacitor layer (capacitor layer containing capacitors (202)) of the second plurality of capacitor layers (capacitor layers containing capacitors (202) below the device layer). Dokania and Haratipour are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Dokania by using the vias connecting the different capacitor layers as disclosed in Haratipour to make establishing electrical connections in the device easier leading to a more efficient device production process.
Regarding claim 12; Dokania teaches a memory device comprising: an access transistor (MN1); a first plurality of capacitors ((Cfe1)…(Cfe3)) over the access transistor (MN1), the first plurality of capacitors ((Cfe1)…(Cfe3)) coupled to a source (Source contact – see Fig (7A) of Dokania shared in this OA) or drain of the access transistor (MN1), and each of the first plurality of capacitors ((Cfe1)…(Cfe3)) coupled to a respective one of a first plurality of platelines ((PL0_1), (PL0_2), (PL0_3)…).
Dokania does not teach a second plurality of capacitors under the access transistor, the second plurality of capacitors coupled to the source or drain of the access transistor, and each of the second plurality of capacitors coupled to a respective one of a second plurality of platelines.
Haratipour teaches a second plurality of capacitors (202) under the access transistor (206), the second plurality of capacitors (202) coupled to the source or drain (208A) of the access transistor (206), and each of the second plurality of capacitors (202) coupled to a respective one of a second plurality of platelines ((PL1)…(PL4)). Dokania and Haratipour are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Dokania by using the second plurality of capacitors below the access transistor as disclosed by Haratipour to improve the performance and reliability of the memory device.
Regarding claim 13; Dokania in view of Haratipour teaches all the limitations of claim 12.
Dokania does not teach wherein a first plateline of the second plurality of platelines is coupled to a first via, and a second plateline of the second plurality of platelines is coupled to a second via.
However, Haratipour teaches wherein a first plateline (PL1) of the second plurality of platelines ((PL1)…(PL4)) is coupled to a first via (226), and a second plateline (PL2) of the second plurality of platelines ((PL1)…(PL4)) is coupled to a second via (226). Dokania and Haratipour are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Dokania by using the vias connected to the second plurality of platelines as disclosed in Haratipour to make establishing electrical connections within the device easier thus leading to a more efficient device manufacturing process.
Regarding claim 14; Dokania in view of Haratipour teaches all the limitations of claim 13.
However, Dokania does not teach wherein the first via extends through a layer of the memory device comprising the access transistor, and the second via extends through the layer of the memory device comprising the access transistor.
Haratipour teaches wherein the first via (226) extends through a layer of the memory device comprising the access transistor (the layer containing transistor (206) – see Fig (2) of Haratipour shared in this OA), and the second via (226) extends through the layer of the memory device comprising the access transistor (the layer containing transistor (206) – see Fig (2) of Haratipour shared in this OA). Dokania and Haratipour are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Dokania by using the vias going through the device layer as disclosed in Haratipour to make establishing electrical connections within the device easier thus leading to a more efficient device manufacturing process.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Dokania et al, US 11696451 B1 (Dokania) in view of Haratipour et al, US 20220208778 A1 (Haratipour) in further view of Onuki et al, US 20220093600 A1 (Onuki).
Regarding claim 3; Dokania in view of Haratipour teaches all the limitations of claim 2.
However, Dokania in view of Haratipour does not teach wherein the first via extends through the first plurality of capacitor layers and through the device layer.
Onuki teaches wherein the first via (426) extends through the first plurality of capacitor layers (layers containing capacitors (292) – see Fig (13) of Onuki shared in this OA) and through the device layer (the layer containing the transistor (413_1)). Dokania in view of Haratipour and Onuki are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Dokania in view of Haratipour by using the first via which extends through the first plurality of the capacitor layers and the device layer as disclosed in Onuki to make establishing electrical connections in the device easier leading to a more efficient device production process.
Regarding claim 4; Dokania in view of Haratipour in further view of Onuki teach all the limitations of claim 3.
However, Dokania in view of Haratipour does not teach wherein the second via extends through the first plurality of capacitor layers, through the device layer, and through the first capacitor layer.
Onuki teaches wherein the second via (430) extends through the first plurality of capacitor layers (layers containg capacitors (292) – see Fig (13) of Onuki shared in this OA), through the device layer (413_1), and through the first capacitor layer (415_1). Dokania in view of Haratipour and Onuki are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Dokania in view of Haratipour by using the second via which extends through the first plurality of the capacitor layers and the device layer and the first capacitor layer as disclosed in Onuki to make establishing electrical connections in the device easier leading to a more efficient device production process.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
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/MOATAZ KHALIFA/Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815