Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-10 in the reply filed on 12/19/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park et al.(US 20220384345 A1, hereafter Park).
Regarding Claim 1, Park discloses:
A semiconductor device(Fig. 5) comprising:
A wafer(Fig. 5 [100]) having at least two source/drain(S/D) epi regions(Fig. 5 [60]);
A power rail(Fig. 5 [20]) arranged on a backside of the wafer(fig. 5 [100]);
A backside contact(BSCA)(Fig. 5 [90]) having a first portion comprising a backside local interconnect with a recessed surface and is configured to connect the at least two S/D epi regions(Fig. 5 [60]) together; and
A plurality of frontside signal wires(Fig. 5 [80]) connected to the backside local interconnect(Fig. 5 [90]) through a first front side contact(fig. 5 [70]).
Regarding Claim 2, Park further discloses:
The BSCA(Fig. 5 [90]) comprises a second portion(Fig. 5 [30]) connected to the power rail(Fig. 5 [20]).
Regarding Claim 3, Park further discloses:
The recessed surface of the backside local interconnect(Fig. 5 [90]) is lower than a surface of the second portion(Fig. 5 [30]) of the BSCA(Fig. 5 [90/30]) to insulate the backside local interconnect(Fig. 5 [90]) from the power rail(Fig. 5 [20]).
Regarding Claim 4, Park further discloses:
A height of the recessed surface of the backside local interconnect(Fig. 5 [90]) is lower than a surface of a buried oxide(BOX) layer(Fig. 5 [10]) adjoining a side of the BSCA(Fig. 5 [90/30]).
Regarding Claim 5, Park further discloses:
The recessed surface of the backside local interconnect(fig. 5 [90]) has a backside interlayer dielectric(BILD)(Fig. 5 See figure below) formed thereon.
Claim(s) 1, 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsao(US 20190080969 A1, hereafter Tsao).
Regarding Claim 1, Tsao discloses:
A semiconductor device(Fig. 2) comprising:
A wafer(Fig. 2 See figure below) having at least two source/drain(S/D) epi regions(Fig. 2 [27_1/27_2]);
A power rail(Fig. 2 [40_2]) arranged on a backside of the wafer(Fig. 2 See figure below);
A backside contact(BSCA)(Fig. 2 [50_7]) having a first portion(Fig. 2 See figure below) comprising a backside local interconnect with a recessed surface and is configured to connect the at least two S/D epi regions(Fig. 2 [27_1/27_2]) together; and
A plurality of frontside signal wires(Fig. 2 [60_5]) connected to the backside local interconnect(Fig. 2 [50_7]) through a first front side contact(Fig. 2 [65_6]).
Regarding Claim 6, Tsao further discloses:
At least one S/D epi region(Fig. 2 [27_1]) connected to the backside local interconnect(Fig. 2 [50_7]) is overlapped with a second frontside contact extension(Fig. 2 [60_4]) of a device from a neighboring cell(Fig. 1C [N3]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsao in view of Park.
Regarding Claim 7,
Tsao discloses a frontside contact extension(Fig. 2 [60_4]).
Tsao does not teach or disclose the second frontside contact extension is wired to signal tracks over the at least one S/D epi region with the backside local interconnect.
In the same field of endeavor, Park discloses an S/D epi region(Fig. 5 [60]) wherein at a frontside contact extension(Fig. 5 See figure below) is wired to signal tracks(Fig. 5 [80]) over the at least one S/D epi region(Fig. 5 [60]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Tsao along the lines of Park. One might have been motivated to wire a contact extension to a signal track in order to maintain the packing efficiency of the device, as each of the S/D and gate terminals of an integrated circuit would require the provision of signal lines in order to operate each cell. Performing this modification would have generated a predictable result in the creation of Tsao’s device with an overlapping contact/wiring structure as disclosed by Park.
Regarding Claim 8,
Claim 6 is rejected under 35 U.S.C. 102(See above rejection).
Tsao does not teach or disclose a backside power distribution network(BSPDN) connected to the power rail.
In the same field of endeavor, Park discloses a backside power distribution network(Fig. 5 [200b]) connected to a power rail(Fig. 5 [20]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Tsao along the lines of Park. One might have been motivated to add the BSPDN in order to power Tsao’s device. Performing this modification would have generated a predictable result in the creation of Tsao’s device with a BSPDN on one side as disclosed by Park.
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsao in view of Zhang et al.(US 20210210413 A1, hereafter Zhang).
Regarding Claim 9,
Claim 6 is rejected under 35 U.S.C. 102(See above rejection).
Tsao does not teach or disclose the at least one S/D epi region connected to the backside local interconnect comprises an S/D P-epi region and an S/D N-epi region.
In the same field of endeavor, Zhang discloses:
The at least one S/D epi region(Fig. 10 [16/18]) connected to the backside local interconnect(Fig. 10 [70]) comprises an S/D P-epi region(Fig. 10 [16]) and an S/D N-epi region(Fig. 10 [18]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Tsao along the lines of Zhang. One might have been motivated to include the S/D regions of different conductivity types in order to produce a CMOS circuit or various integrated circuits involving a plurality of transistors of different conductivity types. Performing this modification would have generated a predictable result in the creation of Tsao’s device with a set of transistors of different conductivity.
Regarding Claim 10, Zhang further discloses:
The S/D N-epi region or the S/D P-epi region(Fig. 2 [27_1/27_2]) is electrically connected to the frontside contact(Fig. 2 [65_6]).
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Above: Fig. 5 of Park with frontside contact extension and backside interlayer dielectric denoted by examiner.
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Above: Fig. 2 of Tsao with wafer and first portion of the interconnect denoted by examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Huang et al.(US 20230197815 A1) discloses a wrap-around contact on both an N-type and P-type S/D region. Shin et al.(US 20220254928 A1) discloses a single contact that contacts a plurality of S/D structures. Seo et al.(US 20220037236 A1) discloses a back side power rail and a plurality of front side contacts.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARSHALL MU-NUO HATFIELD whose telephone number is (703)756-1506. The examiner can normally be reached Mon-Thus 11:00 AM-9:00PM EST.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/MARSHALL MU-NUO HATFIELD/Examiner, Art Unit 2897