DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims Status
Claims 1, 4, 6-8, 10-11, 13-16 and 18-20 are currently pending and being examined. No claims have been amended. Claims 2-3, 5, 9, 12 and 17 have been canceled.
Response to Arguments
Applicant’s arguments, see Remarks, filed 7, with respect to the rejection(s) of claim(s) 1, 4, 6-8, under U.S.C. §102 and U.S.C. §103 have been fully considered and are not persuasive.
Regarding Applicant’s arguments to the objection to the specification, Examiner respectfully will not withdraw the objection. While the specification describing the maintaining of the SiGe nanosheets for Figs. 12-14 and the matching Figs. are consistent, the labeling for said nanosheets 110 is inconsistent within the specification. Element 110 is introduced as a sacrificial nanosheet in [0056] of the specification. The common use of a sacrificial nanosheet is to be removed in future steps, as a placeholder in manufacturing. Element 112 is used as the active nanosheet, which is accepted to be maintained during manufacturing steps. This appears to be in direct opposition with the description of Figs. 12-14 in which element 110 is now being utilized as the nanosheet layer being maintained, while nanosheet 112 is utilized as the sacrificial. As the specification remains unclear to the Examiner, the objection is maintained.
Regarding Applicant’s arguments towards the objection to the drawings on page 8 of Remarks, Examiner agrees the newly submitted Drawings rectify the issues and the Drawing objection is withdrawn.
Regarding Applicant’s argument regarding the claim rejections under 35 U.S.C. §102 for claims 1, 6-8, 13-16, 18, and 20, Examiner respectfully disagrees. On page 11 of the Remarks, Applicant points out that Li refers to elements 27 and 28 as “gate dielectric layers”. Examiner respectfully points out, that while Li may name elements 27 and 28 “gate dielectric layers”, they are analogous to Applicant’s own elements 126 and 126’ in Fig. 14 of the present application. All of 27 and 28 of Li and 126 and 126’ of the present application are high-k dielectric layers, just of differing names in the written specification. These layers are functionally and materially indistinct from one another. Examiner respectfully argues that if Li teaches a gate dielectric in both device regions, Applicant has failed to teach a gate dielectric included in the first device region and excluded in the second device region, as layer 126 and 126’ are equivalent to the layers 27 and 28 of Li. For these reasons, the rejections of claims 1, 6-8, 13-16, 18, and 20 in the Non-Final of 4/20/2026 are upheld and will be repeated below.
Regarding Applicant’s argument against the rejection under 35 U.S.C. §103 for claims 4, 10-11, and 19, as they all rely upon the argument for independent claims 1 and 8, Examiner refers Applicant to the reasoning above, which will not be repeated here. The rejections of claims 4, 10-11, and 19 in the Non-Final of 4/20/2026 are upheld and will be repeated below.
Specification
The disclosure is objected to because of the following informalities: The phrase “sacrificial layer” doesn’t appear to be clear, more specifically in reference to element 110. 110 is introduced as the sacrificial layer and comprising SiGe. Later in the specification, layers 110 appear to act as the active layers, contradictory to their original depiction. The descriptions related to Figs. 12-14 also do not appear consistent, in part to the issue of the layers 110.
Appropriate correction is required.
Claim Objections
Claim 18 is objected to because of the following informalities: the preamble lists claim 18 as depending on canceled claim 17. For the purposes of examination, claim 18 will be interpreted to depend on claim 16. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8, 10-11, and rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation ”the second semiconductor device” in line 9. It is unclear if the “the second semiconductor device” recited in line 9 is the same as the “a nanosheet transistor” in line 8. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, “the second semiconductor device” in line 9 is being interpreted as, “the nanosheet transistor.” Appropriate action is required.
Claim 8 recites the limitation “a nanosheet transistor” in lines 10-11. It is unclear if the nanosheet transistor recited in lines 10-11 is the same as the “a nanosheet transistor” in line 8. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, “a nanosheet transistor” in lines 10-11 is being interpreted as, “the nanosheet transistor.” Appropriate action is required.
Claims 10-11 and 13-14 are also rejected under 35 U.S.C. 112(b) as being indefinite for further limiting and being dependent on indefinite claim 8.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6-8, 13-16, 18, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (CN 114678329 A, hereafter Li).
Regarding claim 1, Li discloses a method of fabricating a semiconductor device, the method comprising:
designating on a substrate (11, [0035]) a first region (see annotated Fig. 21) and a second region (see annotated Fig. 21) separated from the first region by distance to define a space therebetween;
forming a first semiconductor device (31, [0035]) on the first region, the first semiconductor device (31) including a gate dielectric (19, [0035]), wherein forming the first semiconductor device (31) comprises forming one or more semiconductor fins (see annotated Fig. 21) of a fin field-effect transistor (FinFET) (31, [0035]) in the first region; and
forming a second semiconductor device (32, [0035]) on the second region, the second semiconductor device excluding a gate dielectric (element 19 is not in this region), wherein forming the second semiconductor device comprises selectively removing at least one sacrificial nanosheet (channel forming region 15, [0035], contains the sacrificial layer, [0060], 15 will be reference number hereafter) to form at least one void (see annotated Fig. 21) between one or more semiconductor nanosheets (26, [0035]) of a nanosheet transistor in the second region (shown in Figs. 17 and 18);
forming an oxide layer (19 is deposited in Fig. 16, stated to be an oxide in [0065]) on the one or more semiconductor fins and the one or more semiconductor nanosheets (26);
removing the oxide layer (19) from the one or more semiconductor nanosheets (26) while maintaining the oxide layer (19) on the one or more semiconductor fins to form the gate dielectric (19) of the FinFET (depicted between Figs. 16 and 17); and
depositing a high-k dielectric layer (27 and 28, [0035], described as a high-k dielectric in [0098]) on the one or more semiconductor fins and the one or more semiconductor nanosheets (26) after removing the oxide layer (19) from the one or more semiconductor nanosheets (26) and maintaining the at least one void to form a gate-all-around (GAA) semiconductor device in the second region (shown between Figs. 19 and 20).
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Regarding claim 6, in Fig 21 Li teaches the method of claim 1, wherein the oxide layer (19, [0065]) is interposed between the one or more semiconductor fins (see annotated Fig. 21) and the high-k dielectric layer (27, [0035]).
Regarding claim 7, in Fig. 21 Li teaches the method of claim 6, wherein the high-k dielectric layer (27, [0035]) included in the FinFET (31, [0035]) is formed directly on the oxide layer (19, [0065]), and the high-k dielectric layer (28, [0035]) included in the nanosheet transistor (32, [0035]) is formed directly on the one or more semiconductor nanosheets (26, [0035]).
Regarding claim 8, Li discloses a method of fabricating a hybrid transistor device, the method comprising:
designating on a substrate (11, [0035]) a first region (see annotated Fig. 21) and a second region (see annotated Fig. 21) separated from the first region by distance to define a space therebetween (see annotated Fig. 21);
forming on the first region a fin field-effect transistor (FinFET) (31, [0035]) including a gate dielectric (19, [0035]), wherein forming the FinFET (31) comprises forming one or more semiconductor fins in the first region (see annotated Fig. 21);
forming on the second region a nanosheet transistor (32, [0035]) excluding a gate dielectric (19 does not exist on the device), wherein forming the nanosheet transistor (32) comprises selectively removing at least one sacrificial nanosheet (15, [0035], Figs. 17 and 18) to form at least one void (see annotated Fig. 18) between one or more semiconductor nanosheets (26, [0035]) of the nanosheet transistor (32) in the second region;
forming an oxide layer (19 is deposited in Fig. 16, stated to be an oxide in [0065]) on the one or more semiconductor fins and the one or more semiconductor nanosheets (26);
removing the oxide layer (19) from the one or more semiconductor nanosheets (26) while maintaining the oxide layer (19) on the one or more semiconductor fins to form the gate dielectric (19); and
depositing a high-k dielectric layer (27 and 28, [0035], described as a high-k dielectric in [0098], Figs. 17 and 18) on the one or more semiconductor fins and the one or more semiconductor nanosheets (26) after removing the oxide layer (19) from the one or more semiconductor nanosheets (26) and maintaining the at least one void to form a gate-all-around (GAA) semiconductor device in the second region (the device in the second region, is by definition a GAA semiconductor device as the gate is fully surrounding each nanosheet).
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Regarding claim 13, Li teaches the method of claim 8, wherein the gate dielectric (19, [0035]) is interposed between the one or more semiconductor fins (see annotated Fig. 21) and the high-k dielectric layer (27, [0035]).
Regarding claim 14, Li teaches the method of claim 13, wherein the high-k dielectric layer (27, [0035]) included in the FinFET (31, [0035]) is formed directly on the gate dielectric (19, [0035]), and the high-k dielectric layer (28, [0035]) included in the nanosheet transistor (32, [0035]) is formed directly on the one or more semiconductor nanosheets (26, [0035]).
Regarding claim 15, Fig. 21 of Li teaches a semiconductor device comprising:
a substrate (11, [0035]) including a first region (see annotated Fig. 21) and a second region (see annotated Fig. 21) separated from the first region by distance to define a space therebetween (see annotated Fig. 21);
a first semiconductor device (31, [0035]) on the first region, the first semiconductor device (31) including a gate dielectric (19, [0035]); and
a second semiconductor device (32, [0035]) on the second region, the second semiconductor device (32) excluding a gate dielectric (19 does not exist on this device),
wherein the first semiconductor device is a fin field-effect transistor (FinFET) (31, [0035]) including one or more semiconductor fins (see annotated Fig. 21) and a first high-k dielectric layer (27, [0035], described as a high-k dielectric in [0098]) on the one or more semiconductor fins,
wherein the second semiconductor device (32) is a gate-all-around (GAA) nanosheet transistor (the device is referred to as a gate ring transistor, which is a GAA transistor [0035]) including at least one void (see annotated Fig. 18) between one or more semiconductor nanosheets (26, [0035]) and a second high-k dielectric layer (28, [0035], described as a high-k dielectric in [0098]) on the one or more semiconductor nanosheets (26).
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Regarding claim 16, Li teaches the semiconductor device of claim 15, further comprising:
an input/output (I/O) device (35 in Fig. 1, [0042]) on the first region (see annotated Fig. 21) and including the first semiconductor device (31, [0035]); and
a logic device (36 in Fig. 1, [0042]) on the second region (see annotated Fig. 21) and including the second semiconductor device (32, [0035]).
Regarding claim 18, Li teaches the semiconductor device of claim 16, further comprising:
the first high-k dielectric layer (27, [0035]) formed directly on the gate dielectric (19, [0035]) such that the gate dielectric (19) is interposed between the first high-k dielectric layer (27) and the one or more semiconductor fins (see annotated Fig. 21); and
the second high-k dielectric layer ((28, [0035]) formed directly on the one or more semiconductor nanosheets (26 in the second region, [0035]).
Regarding claim 20, Li teaches the semiconductor fin of claim 18, wherein the semiconductor fin (see annotated Fig. 21) comprises alternating layers of silicon germanium (SiGe) (contained in the channel forming regions 15, [0049]) and silicon (Si) (channel 26, [0049]), the alternating layers extending continuously from an upper surface of the semiconductor fin to a base of the semiconductor fin formed on an upper surface of the substrate (11, [0035]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Balakrishnan et al. (US 2017/0338308 A1, hereafter Balakrishnan) and in further view of Cheng et al. (US 2019/0067122 A1, hereafter Cheng).
Regarding claim 4, Li teaches the method of claim 1, wherein forming the one or more semiconductor fins comprises:
forming a first nanosheet stack (see annotated Fig. 16) on [substrate (11, [0035])] (as Li does not teach a BDI layer) in the first region (see annotated Fig. 16), the first nanosheet stack including an alternating arrangement of sacrificial nanosheets (15, [0035]) and active nanosheets (26, [0035]);
forming a second nanosheet stack (see annotated Fig. 16) on [substrate (11, [0035])] (as Li does not teach a BDI layer) in the second region (see annotated Fig. 16), the second nanosheet stack including an alternating arrangement of sacrificial nanosheets (15, [0035]) and active nanosheets (26, [0035]); and
Li fails to disclose forming a bottom dielectric isolation (BDI) layer on an upper surface of the substrate.
However, Balakrishnan teaches a similar method of forming a FinFET in which a BDI (buried insulator layer, 12, [0021]) is deposited on a substrate (10, [0021]). This insulator layer acts as an etch stop layer during processing steps [0025]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Li to include the buried insulator layer of Balakrishnan to protect the device during processing.
Li in view of Balakrishnan fails to disclose replacing the sacrificial nanosheets of the first nanosheet stack with a semiconductor material while maintaining the active nanosheets of the first nanosheet stack to form the one or more semiconductor fins, while maintaining the sacrificial nanosheets of the second nanosheet stack.
However, Li teaches a method of removing sacrificial nanosheets in the second nanosheet stack [0086]. One of ordinary skill in the art would know to apply this technique to the other stack should removal of nanosheets be desired. Cheng teaches a similar I/O device (104, [0021]) in which sacrificial layers 105, 109, 113, and 117 ([0021]) are removed (Cheng states the other lays may be removed as well [0110], meaning they do not have to be). Then the silicon is regrown in the gaps to create the structure (1201, [0111]) of Fig. 12. This structure can be made of silicon (as are layers 103, 107, 111, 115, [0023] states 103 can be silicon, [0035] states 103, 107, 111, and 115 are in an alternating stack with 105, 109, 113, and 117, meaning all of 103, 107, 111, and 115 would comprise silicon). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the FinFET of Li in view of Balakrishnan to have the fin comprise only semiconducting material as taught by Cheng using the selective removing sacrificial nanosheets of Li to get the expected result of reduced resistance within the fin(s).
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Claim(s) 10-11 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Cheng.
Regarding claim 10, Li teaches the method of claim 9, wherein forming the one or more semiconductor fins comprises:
forming a first nanosheet stack (see annotated Fig. 16) in the first region (see annotated Fig. 16), the first nanosheet stack including an alternating arrangement of sacrificial nanosheets (15, [0035]) and active nanosheets (26, [0035]);
forming a second nanosheet stack (see annotated Fig. 16) in the second region (see annotated Fig. 16), the second nanosheet stack including an alternating arrangement of sacrificial nanosheets (15) and active nanosheets (26).
Li fails to disclose replacing the sacrificial nanosheets of the first nanosheet stack with a semiconductor material to form the one or more semiconductor fins, while maintaining the sacrificial nanosheets of the second nanosheet stack.
However, Li teaches a method of removing sacrificial nanosheets in the second nanosheet stack [0086]. One of ordinary skill in the art would know to apply this technique to the other stack should removal of nanosheets be desired. Cheng teaches a similar I/O device (104, [0021]) in which sacrificial layers 105, 109, 113, and 117 ([0021]) are removed (Cheng states the other lays may be removed as well [0110], meaning they do not have to be). Then the silicon is regrown in the gaps to create the structure (1201, [0111]) of Fig. 12. This structure can be made of silicon (as are layers 103, 107, 111, 115, [0023] states 103 can be silicon, [0035] states 103, 107, 111, and 115 are in an alternating stack with 105, 109, 113, and 117, meaning all of 103, 107, 111, and 115 would comprise silicon). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the FinFET of Li to have the fin comprise only semiconducting material as taught by Cheng using the selective removing sacrificial nanosheets of Li to get the expected result of reduced resistance within the fin(s).
Regarding claim 11, Li teaches the method of claim 10, wherein the sacrificial nanosheets (15, [0035]) comprise silicon germanium (SiGe) [0049] and the semiconductor material (26, [0035]) comprises silicon (Si) [0049] to form a strained heterostructure semiconductor fin (see annotated Fig. 21). As the materials are there originally in Li, the strain in the fin is inherent. As XYZ teaches a final heterostructure, the semiconductor material would have to be Si.
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Regarding claim 19, Li teaches the semiconductor fin (see annotated Fig. 21) of claim 18.
Li fails to teach the semiconductor fin comprises silicon (Si) extending continuously from an upper surface of the semiconductor fin to a base of the semiconductor fin formed on an upper surface of the substrate.
However, Li teaches a method of removing sacrificial nanosheets in the second nanosheet stack [0086]. One of ordinary skill in the art would know to apply this technique to the other stack should removal of nanosheets be desired. Cheng teaches a similar I/O device (104, [0021]) in which sacrificial layers 105, 109, 113, and 117 ([0021]) are removed (Cheng states the other lays may be removed as well [0110], meaning they do not have to be). Then the silicon is regrown in the gaps to create the structure (1201, [0111]) of Fig. 12. This structure can be made of silicon (as are layers 103, 107, 111, 115, [0023] states 103 can be silicon, [0035] states 103, 107, 111, and 115 are in an alternating stack with 105, 109, 113, and 117, meaning all of 103, 107, 111, and 115 would comprise silicon). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the FinFET of Li to have the fin comprise only silicon as taught by Cheng using the selective removing sacrificial nanosheets of Li to get the expected result of reduced resistance within the fin(s).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/ERIC W JONES/Primary Examiner, Art Unit 2892
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