DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 02/12/2026 has been entered. Claims 1, 2, 4-20 and newly added claim 21, remain pending in the application. Claim 3 has been cancelled in a previous office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the limitation “the first conductive via being along a first periphery of the two or more traces” and “the second conductive via being along a second periphery of the two or more traces”. Prior to these limitations, claim 17 recites limitations that include only a first and a second trace (two traces) therefore, the more than two traces are not defined. For the purpose of examination claim 17 limitations will be interpreted as “the first conductive via being along a first periphery of the first and second traces” and “the second conductive via being along a second periphery of the first and second traces”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kudo et al., (Japanese Patent Application Number, JP H09237854A), hereinafter referenced as Kudo in view of Park et al., (United States Patent Number, US 10,194,524 B1), hereinafter referenced as Park.
Regarding claim 1, Kudo teaches an interposer, comprising: an upper surface for coupling to a chip (Fig.1, top surface of element #2); a lower surface for coupling to a package substrate (Fig.1, bottom surface of element #2); redistribution layers between the upper surface and the lower surface and comprising routed conductive lines (Fig.1, layers containing elements #4a and #4b are part of signal lines, paragraph [0025], rows 1-4), a respective one of the routed conductive lines extending between a first location and a second location (Fig.1, routed conductive line formed by elements 3-7, extends between two vertical planes that cross the vias #5a, which define the first and second location) and comprising two or more traces extending substantially in parallel between the first location and the second location (Fig.2, elements #4a and 4b are parallel and extend between elements #5a); a first conductive via at the first location to couple the two or more traces at the first location the first conductive via terminating at a bond pad on the upper surface and being absent from the lower surface (Fig.1, element #5a located on the left side of the figure couples traces #4a and 4b and terminates with bond pad element #6 on the upper surface).
Kudo does not teach the first conductive via being along a first periphery of the two or more traces. Park teaches a conductive via being along a first periphery of two or more traces (Fig.1B, via element #16 is along the periphery of traces element #30). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Park and disclose a conductive via being along a first periphery of two or more traces. This results in a smaller footprint of the conductive traces inside the redistribution layers, since the traces do not expand beyond the via.
Kudo further teaches a second conductive via at the second location to couple the two or more traces at the second location, the second conductive via terminating at an additional bond pad on the lower surface and being absent from the upper surface (Fig.1, element #5a located on the right side of the figure couples traces #4a and 4b and terminates with bond pad element #7 on the lower surface).
Kudo does not teach the second conductive via being along a second periphery of the two or more traces the second periphery being opposite the first periphery. Park teaches a second conductive via being along a second periphery of two or more traces the second periphery being opposite the first periphery (Fig.1B, there are two vias element #16 each one along opposite peripheries of traces, elements #30). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Park and disclose the second conductive via being along a second periphery of the two or more traces the second periphery being opposite the first periphery. This results in a smaller footprint of the conductive traces inside the redistribution layers, since the traces do not expand beyond the vias.
Regarding claim 2, the combination of Kudo and Park teaches the interposer of claim 1 as set forth in the obviousness rejection. Kudo further teaches the interposer of claim 1, wherein the two or more traces are stacked in respective layers of the redistribution layers (Fig.1, the two traces, elements #4a and #4b are stacked in two different layers).
Regarding claim 21, the combination of Kudo and Park teaches the interposer of claim 1 as set forth in the obviousness rejection. Kudo further teaches the interposer of claim 1, comprising a single substate (Fig.1, layers elements #2a-#2d form a single substrate, element #2), wherein the upper surface for coupling to the chip is an uppermost surface of the single substrate (Fig.1, top surface of element #2) and wherein the lower surface for coupling to the package substrate is a lowermost surface of the single substrate (Fig.1, bottom surface of element #2).
Claims 4, 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kudo, in view of Park and in view of Jinwoo Choi et al., (United States Patent Application Publication Number, US 2020/0100356 A1), hereinafter referenced as Choi.
Regarding claim 4, the combination of Kudo and Park teaches the interposer of claim 1 as set forth in the obviousness rejection. The combination of Kudo and Park does not teach the interposer of claim 1 wherein the two or more traces are arranged side-by-side in a layer of the redistribution layers. Choi teaches a conductive line comprising two or more traces are arranged side-by-side in a layer, parallel to each other between the first and second location (Fig.6, annotated below, 1st and 2nd traces are side-by-side, parallel to each other between first and second locations indicated by the red dashed lines). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Choi and disclose the two or more traces are arranged side-by-side in a layer of the redistribution layers. As disclosed by Choi, the routed conductive line comprising the two parallel traces arranged side by side can be used to reduce cross-talk between signal lines.
Regarding claim 5, the combination of Kudo and Park teaches the interposer of claim 1 as set forth in the obviousness rejection, and the combination of Kudo, Park and Choi teaches the interposer of claim 4 as set forth in the obviousness rejection. Choi further teaches wherein the respective one of the routed conductive lines further comprises a first coupling trace to couple the two or more traces at the first location and a second coupling trace to couple the two or more traces at the second location (Fig.6, annotated below, 1st and 2nd traces are coupled by a 1st and a 2nd coupling trace at the first and second location, respectively). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Choi and disclose wherein the respective one of the routed conductive lines further comprises a first coupling trace to couple the two or more traces at the first location and a second coupling trace to couple the two or more traces at the second location. As disclosed by Choi, the coupling traces electrically connect the conductive lines and reduce cross-talk between signal lines.
Regarding claim 6, the combination of Kudo and Park teaches the interposer of claim 1 as set forth in the obviousness rejection. The combination of Kudo and Park does not teach the interposer of claim 1 wherein the two or more traces comprise: a first trace and a second trace arranged side-by-side in a first layer of the redistribution layers; and a third trace and a fourth trace arranged side-by-side in a second layer of the redistribution layers; the third trace under the first trace and the fourth trace under the second trace. Choi teaches wherein two or more traces comprise: a first trace and a second trace arranged side-by-side in a first layer of the redistribution layers (Fig.6, annotated below, 1st and 2nd traces are side-by-side in the top layer); and a third trace and a fourth trace arranged side-by-side in a second layer of the redistribution layers (Fig.6, annotated below, 3rd and 4th traces are side-by-side in the middle layer), the third trace under the first trace and the fourth trace under the second trace (Fig.6, annotated below, 3rd trace is under 1st trace and 4th trace is under 2nd trace). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Choi and disclose the two or more traces comprise: a first trace and a second trace arranged side-by-side in a first layer of the redistribution layers; and a third trace and a fourth trace arranged side-by-side in a second layer of the redistribution layers, the third trace under the first trace and the fourth trace under the second trace. As disclosed by Choi, the four traces arranged as claimed can effectively surround the signal lines included in a plane between the four traces, which ensures that noise does not interfere with transmitted signals and causes a loss of reliability of data transmission across the signal lines.
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Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kudo, in view of Park, Choi and in view of John Cohn et al., (United States Patent Number, US 7,078,248 B2), hereinafter referenced as Cohn.
Regarding claim 7, the combination of Kudo and Park teaches the interposer of claim 1 as set forth in the obviousness rejection and the combination of Kudo, Park and Choi teaches the interposer of claim 6 as set forth in the obviousness rejection. Choi further teaches wherein the redistribution layers comprise: a first coupling trace to couple the first trace and the second trace at the first location; a second coupling trace to couple the first trace and the second trace at the second location (Fig.6, annotated above, the 1st coupling trace couples the 1st and 2nd trace at first location and the 2nd coupling trace couples the 1st and 2nd trace at the second location). The combination of Kudo, Park and Choi does not teach the first conductive via to couple the first trace and the third trace at the first location; the second conductive via to couple the second trace and the fourth trace at the first location; a third conductive via to couple the first trace and the third trace at the second location; and a fourth conductive via to couple the second trace and the fourth trace at the second location. Cohn teaches wherein the redistribution layers comprise: a first coupling trace to couple the first trace and the second trace at the first location (Fig.4b annotated below, 1st coupling trace couples the 1st and 2nd traces through vias V5 at 1st location indicated by the top horizontal red dashed line); a second coupling trace to couple the first trace and the second trace at the second location (Fig.4b annotated below, 2nd coupling trace couples the 1st and 2nd traces through vias V5 at 2nd location indicated by the bottom horizontal red dashed line); a first conductive via to couple the first trace and the third trace at the first location (Fig.4a, annotated below, 1st via V4 couples the 1st and 3rd traces, through the 1st coupling trace and 1st via V5 at 1st location); a second conductive via to couple the second trace and the fourth trace at the first location (Fig.4a, annotated below, 2nd via V4 couples the 2nd and 4th traces, through the 1st coupling trace and a 2nd vis V5 at 1st location); a third conductive via to couple the first trace and the third trace at the second location (Fig.4a, annotated below, 3rd via V4 couples the 1st and 3rd trace, through the second coupling trace and a third via V5 at the 2nd location); and a fourth conductive via to couple the second trace and the fourth trace at the second location (Fig.4a, annotated below, 4th via V4 couples the 2nd and 4th traces, through the second coupling trace and a 4th vis V5 at the 2nd location). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Cohn and disclose a first conductive via to couple the first trace and the third trace at the first location; a second conductive via to couple the second trace and the fourth trace at the first location; a third conductive via to couple the first trace and the third trace at the second location; and a fourth conductive via to couple the second trace and the fourth trace at the second location. This allows all four traces to be electrically connected and therefore transmit signals between the different redistribution layers. Furthermore, having multiple through vias connecting traces, increases the reliability of the electrical connections and manufacturing yield.
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Claims 8, 9, 10, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kudo, in view of Park and in view of Andrew Collins et al., (United States Patent Application Publication Number, US 2020/0312759 A1), hereinafter referenced as Collins.
Regarding claim 8, the combination of Kudo and Park teaches the interposer of claim 1 as set forth in the obviousness rejection. Kudo teaches wherein the respective one of the routed conductive lines comprises a signaling line (paragraph [0025], rows 1-4). The combination of Kudo and Park does not teach wherein the routed conductive lines further comprise a ground line extending adjacent to the signaling line. Collins teaches wherein the respective one of the routed conductive lines (Fig.4, traces showed in the figure) comprises a signaling line (Fig.4, element #443 is a differential signal line, paragraph [0050], row 6), and wherein the routed conductive lines further comprise a ground line (Fig.4, element #441 is part of a grounding plane, paragraph [0050], row 7) extending adjacent to the signaling line (Fig.4, element #441 is extending adjacent to element #443). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Collins and disclose the respective one of the routed conductive lines comprises a signaling line, and wherein the routed conductive lines further comprise a ground line extending adjacent to the signaling line. As disclosed by Collins, ground lines adjacent to the signal lines reduce the cross-talk between signal paths (paragraph [0025], rows 2-6).
Regarding claim 9, the combination of Kudo and Park teaches the interposer of claim 1 as set forth in the obviousness rejection and the combination of Kudo, Park and Collins teaches the interposer of claim 8 as set in the obviousness rejection. Collins further teaches wherein the ground line comprises two or more ground traces extending substantially in parallel (Fig.4, ground line element #441, paragraph [0050], row 7, comprises two or more lines parallel to each other). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Collins and disclose the ground line comprises two or more ground traces extending substantially in parallel. As disclosed by Collins, parallel ground lines on opposite sides of the signal lines reduce the cross-talk between signal paths (paragraph [0025], rows 2-6).
Regarding claim 10, the combination of Kudo and Park teaches the interposer of claim 1 as set forth in the obviousness rejection and the combination of Kudo, Park and Collins teaches the interposer of claims 8 and 9 as set in the obviousness rejection. Collins further teaches wherein: a first redistribution layer of the redistribution layers comprises a first trace of the two or more traces and a first ground trace of the two or more ground traces (Fig.4, layer element #426 comprises a signal trace, element #443 and a ground trace, element #441, to the left side of the image); and a second redistribution layer of the redistribution layers comprises a second trace of the two or more traces and a second ground trace of the two or more ground traces (Fig.4, layer element #425 comprises a signal trace, element #443 and a ground trace, element #441, to the left side of the image). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Collins and disclose a first redistribution layer of the redistribution layers comprises a first trace of the two or more traces and a first ground trace of the two or more ground traces and a second redistribution layer of the redistribution layers comprises a second trace of the two or more traces and a second ground trace of the two or more ground traces. Placing signal traces of the same conductive line in multiple redistribution layers allows for the transmission of signals through the redistribution layers to connected dies or circuit boards. Furthermore, placing ground traces in the same layers as the signal traces allows for a smaller distance between the ground and signal traces which helps reduce cross-talk (paragraph [0002] rows 4-7).
Regarding claim 14, the combination of Kudo and Park teaches the interposer of claim 1 as set forth in the obviousness rejection. The combination of Kudo and Park does not teach wherein one or more of a width of the two or more traces, a count of the two or more traces, an arrangement of the two or more traces, and a distance between the two or more traces and a ground line of the routed conductive lines of the redistribution layers are configured to cause the respective one of the routed conductive lines to exhibit a resistance below a resistance threshold and a capacitance below a capacitance threshold. Collins teaches wherein one or more of a width of the two or more traces (Fig.4, all traces have a width), a count of the two or more traces (Fig.4, there are multiple ground and signal traces), an arrangement of the two or more traces (Fig.4, ground traces surround the signal traces), and a distance between the two or more traces and a ground line of the routed conductive lines of the redistribution layers (Fig.4, there is a distance between the ground traces and the signal traces) are configured to cause the respective one of the routed conductive lines to exhibit a resistance below a resistance threshold and a capacitance below a capacitance threshold (paragraph [0025], rows 1-4, are configured to tune the impedance of the routed conductive line, which is determined by the capacitance and resistance of the line). Any conductive line exhibits a resistance and a capacitance value (MPEP 2144.03). One notes that a resistance threshold and a capacitance threshold can be any resistance or capacitance value. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Collins and disclose wherein a width, a count, an arrangement and a distance to a ground line are configured to cause the respective one of the routed conductive lines to exhibit a resistance below a resistance threshold and a capacitance below a capacitance threshold. As disclosed by Collins, this allows one to minimize cross-talk between the signal paths while also reducing losses in differential signal traces (paragraph [0026], rows 14-19).
Regarding claim 15, the combination of Kudo and Park teaches the interposer of claim 1 as set forth in the obviousness rejection. The combination of Kudo and Park does not teach wherein one or more of a width of the two or more traces, a count of the two or more traces, an arrangement of the two or more traces, and a distance between the two or more traces and a ground line of the routed conductive lines of the redistribution layers are configured to cause the respective one of the routed conductive lines to exhibit a predetermined resistance and a predetermined capacitance to govern a frequency response of the respective one of the routed conductive lines to signals conducted by the respective one of the routed conductive lines. Collins teaches wherein one or more of a width of the two or more traces (Fig.4, all traces have a width), a count of the two or more traces (Fig.4, there are multiple ground and signal traces), an arrangement of the two or more traces (Fig.4, ground traces surround the signal traces), and a distance between the two or more traces and a ground line of the routed conductive lines of the redistribution layers (Fig.4, there is a distance between the ground traces and the signal traces) are configured to cause the respective one of the routed conductive lines to exhibit a predetermined resistance and a predetermined capacitance, (One notes that “a predetermined resistance” and “a predetermined capacitance” does not distinguish over any resistance and capacitance values) to govern a frequency response of the respective one of the routed conductive lines to signals conducted by the respective one of the routed conductive lines (Any conductive line has a resistance and a capacitance value and therefore an impedance value, and the fact that impedance governs the frequency response of a conductive line is well known in the art (MPEP 2144.03)). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Collins and disclose wherein a width, a count, an arrangement and a distance to a ground line are configured to cause the respective one of the routed conductive lines to exhibit a predetermined resistance and a predetermined capacitance to govern a frequency response of the respective one of the routed conductive lines to signals conducted by the respective one of the routed conductive lines. As disclosed by Collins, this configuration allows one to optimize the impedance (which is determined by the resistance and capacitance of the signal line) of the differential signal traces and minimize signal losses (paragraph [0026], rows 1-5 and 14-19).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kudo, in view of Park and in view of Mukta Farooq et al., (United States Patent Application Publication Number, US 2016/0079166 A1), hereinafter referenced as Faroog.
Regarding claim 12, the combination of Kudo and Park teaches the interposer of claim 1 as set forth in the obviousness rejection. The combination of Kudo and Park does not teach wherein the routed conductive lines of the redistribution layers are arranged in a bulk substrate, the bulk substrate comprising silicon dioxide. Faroog teaches wherein the routed conductive lines of the redistribution layers are arranged in a bulk substrate, the bulk substrate comprising silicon dioxide (paragraph [0037], rows 3-10). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Faroog and disclose wherein the routed conductive lines of the redistribution layers are arranged in a bulk substrate, the bulk substrate comprising silicon dioxide. As disclosed by Farooq, the substrate comprising silicon dioxide can be used to electrically isolate the conductive lines of the redistribution layers.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kudo, in view of Park and in view of Zhiguo Qian et al., (United States Patent Number, US 8,946,900 B2), hereinafter referenced as Qian.
Regarding claim 13, the combination of Kudo and Park teaches the interposer of claim 1 as set forth in the obviousness rejection. The combination of Kudo and Park does not teach wherein the routed conductive lines of the redistribution layers are arranged in a bulk substrate, the bulk substrate comprising an organic compound. Qian teaches wherein the routed conductive lines of the redistribution layers are arranged in a bulk substrate the bulk substrate comprising an organic compound (Fig.5B, element #556 which comprise routing layers is embedded in an organic substrate, column 6, rows 65-67). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Qian and disclose the routed conductive lines of the redistribution layers are arranged in a bulk substrate, the bulk substrate comprising an organic compound. Substrates comprising organic compounds can be flexible and therefore can be used to make bendable electronics.
Claims 11, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kudo, in view of Park and in view of Owen R. Fay et al., (United States Patent Application Publication Number, US 2021/0183842 A1), hereinafter referenced as Fay.
Regarding claim 11, the combination of Kudo and Park teaches the interposer of claim 1 as set forth in the obviousness rejection. The combination of Kudo and Park does not teach wherein the redistribution layers comprise bulk substrate between the two or more traces and the upper surface and between the two or more traces and the lower surface. Fay teaches wherein the redistribution layers (Fig.3C, elements #218-224, paragraph [0068], rows 1-3) comprise bulk substrate between the two or more traces and the upper surface (Fig.3C, top element #202, paragraph [0068], row 10 is located between the traces and the upper surface of top element #224) and between the two or more traces and the lower surface (Fig.3C, bottom element #202, paragraph [0068], row 10, is located between the traces and the bottom surface of bottom element #202). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Fay and disclose wherein the redistribution layers comprise bulk substrate between the two or more traces and the upper surface and between the two or more traces and the lower surface. As disclosed by Fay, the bulk substrate can incorporate conductive vias that match the contact pitches of the dies and/or substrates connected to the interposer (paragraph [0057], rows 20-23).
Regarding claim 16, Kudo teaches a device comprising a chip electrically coupled to an interposer (Fig.1, interposer element #2 is electrically coupled with a chip, using bondpad, element #6, paragraph [0018] 1-4). Kudo does not teach a package substrate and the interposer between and electrically coupling the package substrate and the chip. Fay teaches a package substrate (Fig.1C, element #106L, paragraph [0047], row 36) and the interposer (Fig.1C, elements #106A and #106B, paragraph [0047], row 37) between and electrically coupling the package substrate and the chip (paragraph [0047], rows 10-15, 33-40). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Fay and disclose a package substrate and the interposer between and electrically coupling the package substrate and the chip. The package substrate can provide power/signal to the attached semiconductor through the interposer, as well as mechanical support.
Kudo further teaches the interposer comprising: redistribution layers comprising routed conductive lines (Fig.1, layers containing elements #4a and #4b are part of signal lines, paragraph [0025], rows 1-4), a respective one of the routed conductive lines extending between a first location and a second location (Fig.1, routed conductive line formed by elements 3-7, extends between two vertical planes that cross the vias #5a, which define the first and second location) and comprising two or more traces extending substantially in parallel between the first location and the second location (Fig.2, elements #4a and 4b are parallel and extend between elements #5a); a first conductive via at the first location to couple the two or more traces at the first location, the first conductive via terminating at a bond pad on an upper surface of the interposer and being absent from a lower surface of the interposer (Fig.1, element #5a located on the left side of the figure couples traces #4a and 4b and terminates with bond pad element #6 on the upper surface).
Kudo does not teach the first conductive via being along a first periphery of the two or more traces. Park teaches a conductive via being along a first periphery of two or more traces (Fig.1B, via element #16 is along the periphery of traces element #30). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Park and disclose a conductive via being along a first periphery of two or more traces. This results in a smaller footprint of the conductive traces inside the redistribution layers, since the traces do not expand beyond the via.
Kudo further teaches a second conductive via at the second location to couple the two or more traces at the second location, the second conductive via terminating at an additional bond pad on the lower surface of the interposer and being absent from the upper surface of the interposer (Fig.1, element #5a located on the right side of the figure couples traces #4a and 4b and terminates with bond pad element #7 on the lower surface).
Kudo does not teach the second conductive via being along a second periphery of the two or more traces the second periphery being opposite the first periphery. Park teaches a second conductive via being along a second periphery of two or more traces the second periphery being opposite the first periphery (Fig.1B, there are two vias element #16 each one along opposite peripheries of traces, elements #30). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Park and disclose the second conductive via being along a second periphery of the two or more traces the second periphery being opposite the first periphery. This results in a smaller footprint of the conductive line inside the redistribution layers, since the traces do not expand beyond the vias.
Regarding claim 17, Kudo teaches a method, comprising: forming a first redistribution layer (Fig.5, layer in which element #4c resides), the first redistribution layer comprising a first trace (Fig.5, element #4c) of a routed conductive line between a first location and a second location (Fig.5, routed conductive line formed by elements 3-7, extends between two vertical planes that cross the vias #5a, and form the first and second location); forming a second redistribution layer above the first redistribution layer (Fig.5, layer in which element #4b resides)
Kudo does not teach the second redistribution layer comprising bulk substrate. Fay teaches wherein the redistribution layers (Fig.3C, elements #218-224, paragraph [0068], rows 1-3) comprise bulk substrate (Fig.3C, top element #202, paragraph [0068], row 10, located between the traces and the upper surface of top element #224). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Fay and disclose wherein the second redistribution layer comprise bulk substrate. Using bulk substrates allows the manufacture of redistribution layers with high density interconnects suitable for chips with small pads pitch.
Kudo further teaches forming a third redistribution layer entirely above the second redistribution layer (Fig.5, layer in which element #4a resides), the third redistribution layer comprising a second trace (Fig.5, element #4a), of the routed conductive line between the first location and the second location (Fig.5, routed conductive line formed by elements 3-7, extends between two vertical planes that cross the vias #5a, and form the first and second location), the second trace above the first trace (Fig.5, element #4a is above element #4c); forming a first conductive via at the first location between the first trace and the second trace, the first conductive via terminating at a bond pad on an upper surface of an interposer (Fig.5, element #5a located on the left side of the figure couples traces #4a and #4c and terminates with bond pad element #6 on the upper surface of element #2).
Kudo does not teach the first conductive via being along a first periphery of the first and second traces. Park teaches a conductive via being along a first periphery of the first and second traces (Fig.1B, via element #16 is along the periphery of traces element #30). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Park and disclose a conductive via being along a first periphery of the first and second traces. This results in a smaller footprint of the conductive traces inside the redistribution layers, since the traces do not expand beyond the via.
Kudo further teaches forming a second conductive via at the second location between the first trace and the second trace, the second conductive via terminating at an additional bond pad on a lower surface of the interposer, (Fig.1, element #5a located on the right side of the figure couples traces #4a and 4b and terminates with bond pad element #7 on the lower surface of element #2).
Kudo does not teach the second conductive via being along a second periphery of the first and second traces, the second periphery being opposite the first periphery. Park teaches a second conductive via being along a second periphery of the first and second traces, the second periphery being opposite the first periphery (Fig.1B, there are two vias element #16 each one along opposite peripheries of traces, elements #30). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Park and disclose the second conductive via being along a second periphery of the first and second traces, the second periphery being opposite the first periphery. This results in a smaller footprint of the conductive traces inside the redistribution layers, since the traces do not expand beyond the vias.
Claims 18, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kudo, in view of Park, Fay and Collins.
Regarding claim 18, the combination of Kudo, Park and Fay teaches the method of claim 17 as set forth in the obviousness rejection. Kudo further teaches the method comprising selecting one or more of a width of the first trace (Fig.2, the first trace, element #4a has a width), a width of the second trace (Fig.2, the second trace, element #4b has a width) to cause the routed conductive line to exhibit a resistance below a resistance threshold and a capacitance below a capacitance threshold. One notes that a resistance threshold and a capacitance threshold can be any resistance and capacitance value. Any conductive line exhibits a resistance and a capacitance value (MPEP 2144.03).
The combination of Kudo, Park and Fay does not teach a count of additional traces of the routed conductive line an arrangement of the additional traces of the routed conductive line, a distance between the first trace and a ground trace in the first redistribution layer, and a distance between the second trace and a ground trace in the third redistribution layer. Collins teaches a distance between a first trace (Fig.4, bottom trace of element #443 on the upper left side of the figure) and a ground trace in the first redistribution layer (Fig.4, the trace of ground plane element #441, located in the same layer as the first trace) and a distance between the second trace (Fig.3E, shows same element #443 as in Fig. 4 but disposed over 3 layers, paragraph [0049], rows 3-7, second trace is the top trace of element #443) and a ground trace in the third redistribution layer (Fig.4, every layer is shown having a ground trace, element #441, spaced apart from element #443). Collins also teaches the method further comprising selecting one or more of a width of the first trace (Fig.4, bottom trace of element #443 on the upper left side of the figure has a width), a width of the second trace (Fig.3E, shows same element #443 as in Figure 4 but dispose over 3 layers, paragraph [0049], rows 3-7, second trace is the top trace of element #443 and has a width), a count of additional traces of the routed conductive line (Fig.3E, each element #443 has multiple traces), an arrangement of the additional traces of the routed conductive line (Fig.3E, traces #443 have an arrangement), a distance between the first trace and a ground trace in the first redistribution layer (Fig.4, the trace of ground plane element #441 located in the same layer is at a distance from element #443), and a distance between the second trace and a ground trace in the third redistribution layer (Fig.4, there is a distance between any of ground traces #441 and elements #443), to cause the routed conductive line to exhibit a resistance below a resistance threshold and a capacitance below a capacitance threshold (paragraph [0025], rows 1-4, the above are configured to tune the impedance of the routed conductive line, which is determined by the capacitance and resistance). Any conductive line exhibits a resistance and a capacitance value (MPEP 2144.03). One notes that a resistance threshold and a capacitance threshold can be any resistance and capacitance value. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Collins and disclose wherein a width, a count, an arrangement and a distance to a ground line are configured to cause the respective one of the routed conductive lines to exhibit a resistance below a resistance threshold and a capacitance below a capacitance threshold. As disclosed by Collins, this configuration allows one to minimize the cross-talk between the signal paths while also reducing losses in differential signal traces (paragraph [0026], rows 14-19).
Regarding claim 19, the combination of Kudo, Park and Fay teaches the method of claim 17 as set forth in the obviousness rejection. Kudo further teaches the method further comprising selecting one or more of a width of the first trace (Fig.2, the first trace, element #4a has a width), a width of the second trace (Fig.2, the second trace, element #4b, has a width) to cause the routed conductive line to exhibit a predetermined resistance and a predetermined capacitance (One notes that “predetermined resistance” and “predetermined capacitance” does not distinguish over any resistance and capacitance values) to govern a frequency response of the routed conductive line to signals conducted by the routed conductive line (Any conductive line has a resistance and a capacitance value and therefore an impedance, and the fact that impedance governs the frequency response is well known in the art (MPEP 2144.03)).
The combination of Kudo, Park and Fay does not teach a count of additional traces of the routed conductive, an arrangement of the additional traces of the routed conductive line, a distance between the first trace and a ground trace in the first redistribution layer, and a distance between the second trace and a ground trace in the third redistribution layer. Collins teaches a distance between a first trace (Fig.4, bottom trace of element #443 located in the upper left corner of the figure) and a ground trace in the first redistribution layer (Fig.4, the trace of ground plane element #441, located in the same layer as bottom trace of element #443) and a distance between the second trace (Fig.3E, shows same element #443 as in Figure 4 but disposed over 3 layers, paragraph [0049], rows 3-7, second trace is the top trace of element #443) and a ground trace in the third redistribution layer (Fig.4, shows all layers having a ground trace, element #441 spaced apart from element #443). Collins also teaches the method further comprising selecting one or more of a width of the first trace (Fig.4, bottom trace of element #443 on the upper left side of the figure has a width), a width of the second trace (Fig.3E, shows same element #443 as in Figure 4 but disposed over 3 layers, paragraph [0049], rows 3-7, second trace is the top trace of element #443 and has a width), a count of additional traces of the routed conductive line (Fig.3E, element #443 has multiple vias), an arrangement of the additional traces of the routed conductive line (vias connecting traces #443 have an arrangement), a distance between the first trace and a ground trace in the first redistribution layer (Fig.4, the trace of ground plane element #441 located in the same layer as element #443 is at a distance from element #443), and a distance between the second trace and a ground trace in the third redistribution layer (Fig.4, there is a distance between any of ground traces #441 and element #443 located in the same layer), to cause the routed conductive line to exhibit a predetermined resistance and a predetermined capacitance (One notes that “a predetermined resistance” and “a predetermined capacitance” does not distinguish over any resistance and capacitance values) to govern a frequency response of the routed conductive line to signals conducted by the routed conductive line (Any conductive line has a resistance and a capacitance value and therefore an impedance, and the fact that the impedance governs the frequency response, is well known in the art (MPEP 2144.03)). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Collins and disclose wherein a width, a count, an arrangement and a distance to a ground line to cause the routed conductive line to exhibit a predetermined resistance and a predetermined capacitance to govern a frequency response of the routed conductive line to signals conducted by the routed conductive line. As disclosed by Collins, this allows one to optimize the impedance of the differential signal traces to minimize signal losses (paragraph [0026], rows 1-5, 14-19).
Regarding claim 20, the combination of Kudo, Park and Fay teaches the method of claim 17 as set forth in the obviousness rejection. The combination of Kudo, Park and Fay does not teach wherein: the first redistribution layer comprises a first ground trace of a ground line, the first ground trace extending adjacent to the first trace; and the third redistribution layer comprises a second ground trace of the ground line, the second ground trace extending adjacent to the second trace. Collins teaches a redistribution layer (Fig.4, layer inside which the bottom trace of element #443 shown in the upper left corner of the figure, is located) comprises a first ground trace of a ground line (Fig.4, trace of element #441 located in the same redistribution layer), the first ground trace extending adjacent to the first trace (Fig.4, the two traces extend adjacent to each other in the direction perpendicular to the page, seen also in plane view of Fig.1C). Same teaching applied to the third distribution layer. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Collins and disclose the first redistribution layer comprises a first ground trace of a ground line, the first ground trace extending adjacent to the first trace; and the third redistribution layer comprises a second ground trace of the ground line, the second ground trace extending adjacent to the second trace. As disclosed by Collins, placing the ground traces adjacent to the signal traces helps reduce the cross-talk between signal paths (paragraph [0025], rows 1-6) in both redistribution layers.
Response to Arguments
Applicant’s arguments filed on 02/12/2026 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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