Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/20/2026 has been entered.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 rejected under 35 U.S.C. 103 as being unpatentable over of Raja (U.S. Patent Pub. No. 2021/0242241) of record, in view of Tsuda (U.S. Patent Pub. No. 2023/0352090).
Regarding Claim 1
FIGS. 5 and 8 of Raja discloses a three-dimensional memory structure formed above a planar surface of a semiconductor substrate (9), the memory structure comprising: a plurality of memory stacks arranged along a first direction and extending in a second direction, the memory stacks being separated by trenches of the first type (58) and trenches of the second type (79) alternately arranged in the first direction, the first and second directions being orthogonal to each other and both being substantially parallel to the planar surface of the semiconductor substrate, wherein (i) each memory stack comprises a plurality of active layers, each active layer comprising a first conductive layer (24) and a second conductive layer (26) spaced apart by a first isolation layer (31); and (ii) the plurality of active layers being provided one on top of another along a third direction substantially normal to the planar surface of the semiconductor substrate and being isolated one from the other active layer by a second isolation layer (34); and a plurality of gate electrode structures (66) being provided in the trenches of the first type and arranged spaced apart in the second direction, the gate electrode structures extending in the third direction substantially normal to the planar surface of the semiconductor substrate, each gate electrode structure including (i) a semiconductor oxide layer (57) formed on the sidewalls of the trenches of the first type and in contact with the first and second conductive layers in the third direction along the sidewalls of the trenches of the first type [0084]; (ii) a ferroelectric dielectric layer (154) provided adjacent the semiconductor oxide layer; and (iii) a gate conductor layer (66) formed adjacent the ferroelectric dielectric layer, wherein each active layer in the memory stack forms a plurality of thin-film ferroelectric memory transistors organized as a NOR memory string [0056], each memory transistor being formed at the intersection of the active layer and a gate electrode structure, the plurality of memory stacks forming a plurality of NOR memory strings in the trenches of the first type; and wherein the second isolation layer comprises a dielectric liner layer (56) formed on exposed surfaces in the memory stack and a first dielectric capping layer formed at an end of each second isolation layer facing the trenches of the second type, the remaining cavity in the second isolation layer forming an air gap cavity [0127].
Raja does not explicitly state the semiconductor oxide is “a metal oxide semiconductor layer”. However, by definition, semiconductor oxides are metal oxides that exhibit semiconductor properties.
Furthermore, FIG. 3 of Tsuda discloses a similar three-dimensional memory structure, wherein semiconductor oxide layer is a metal oxide semiconductor layer [0177].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Raja, as taught by Tsuda, because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values, MPEP 2144.06. The ordinary artisan would have been motivated to modify Raja in the above manner for purpose of high electron mobility.
Claims 1, 2 and 5-9 rejected under 35 U.S.C. 103 as being unpatentable over of Raja (U.S. Patent Pub. No. 2021/0242241) of record, in view of Hoang (U.S. Patent Pub. No. 2023/0143057) of record.
Regarding Claim 1
FIGS. 5 and 8 of Raja discloses a three-dimensional memory structure formed above a planar surface of a semiconductor substrate (9), the memory structure comprising: a plurality of memory stacks arranged along a first direction and extending in a second direction, the memory stacks being separated by trenches of the first type (58) and trenches of the second type (79) alternately arranged in the first direction, the first and second directions being orthogonal to each other and both being substantially parallel to the planar surface of the semiconductor substrate, wherein (i) each memory stack comprises a plurality of active layers, each active layer comprising a first conductive layer (24) and a second conductive layer (26) spaced apart by a first isolation layer (31); and (ii) the plurality of active layers being provided one on top of another along a third direction substantially normal to the planar surface of the semiconductor substrate and being isolated one from the other active layer by a second isolation layer (34); and a plurality of gate electrode structures (66) being provided in the trenches of the first type and arranged spaced apart in the second direction, the gate electrode structures extending in the third direction substantially normal to the planar surface of the semiconductor substrate, each gate electrode structure including (i) a semiconductor layer (channel 60) formed on the sidewalls of the trenches of the first type and in contact with the first and second conductive layers in the third direction along (parallel to, the contact direction refers to the direction in which forces are applied between contact surfaces, typically perpendicular to the surface) the sidewalls of the trenches of the first type [0084]; (ii) a ferroelectric dielectric layer (154) provided adjacent the semiconductor layer; and (iii) a gate conductor layer (66) formed adjacent the ferroelectric dielectric layer, wherein each active layer in the memory stack forms a plurality of thin-film ferroelectric memory transistors organized as a NOR memory string [0056], each memory transistor being formed at the intersection of the active layer and a gate electrode structure, the plurality of memory stacks forming a plurality of NOR memory strings in the trenches of the first type; and wherein the second isolation layer comprises a dielectric liner layer (56) formed on exposed surfaces in the memory stack and a first dielectric capping layer formed at an end of each second isolation layer facing the trenches of the second type, the remaining cavity in the second isolation layer forming an air gap cavity [0127].
Raja is silent with respect to the semiconductor channel is “a metal oxide semiconductor layer”.
FIG. 6A of Hoang discloses a similar three-dimensional memory structure, comprising a metal oxide semiconductor channel (530) [0055] formed on the sidewalls of the trenches of the first type and in contact with the first (511) and second (512) conductive layers along the sidewalls of the trenches of the first type (parallel to the vertical direction); (FIG. 3) a ferroelectric [0035] dielectric layer (318) provided adjacent the semiconductor oxide layer (314) [0037]; and a gate conductor layer (317) formed adjacent the ferroelectric dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Raja, as taught by Hoang, because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values ([0037] of Hoang), MPEP 2144.06. The ordinary artisan would have been motivated to modify Raja in the above manner for purpose of chemical and physical stability.
Regarding Claim 2
FIG. 11 of Raja discloses a second dielectric capping layer (80) formed in a top portion of the trenches of the second type and capping the trenches, the top portion being opposite the semiconductor substrate, wherein the remaining cavity in the trenches of the second type comprises an air gap cavity formed in the trenches of the second type under the second dielectric caping layer.
Regarding Claim 5
FIG. 5 of Raja discloses the dielectric liner layer (56) is formed from a material selected from silicon dioxide, silicon nitride, or aluminum oxide [0098].
Regarding Claim 6
FIG. 5 of Raja discloses the dielectric liner layer has a thickness of 1-2 nm in the first direction [0098].
Regarding Claim 7
FIG. 5 of Raja discloses the first dielectric capping layer is formed from a material selected from silicon dioxide or silicon nitride [0084].
Regarding Claim 8
FIG. 5 of Raja discloses the first dielectric capping layer has a thickness of 5-10 nm in the first direction [0087].
Regarding Claim 9
FIG. 11 of Raja discloses the second dielectric capping layer comprises a silicon dioxide layer [0078].
Claim 1 rejected under 35 U.S.C. 103 as being unpatentable over of Raja (U.S. Patent Pub. No. 2021/0242241) of record, in view of Jackson (WO 2016018412) of record, in view of Wu (U.S. Patent Pub. No. 2021/0407966).
Regarding Claim 1
FIGS. 5 and 8 of Raja discloses a three-dimensional memory structure formed above a planar surface of a semiconductor substrate (9), the memory structure comprising: a plurality of memory stacks arranged along a first direction and extending in a second direction, the memory stacks being separated by trenches of the first type (58) and trenches of the second type (79) alternately arranged in the first direction, the first and second directions being orthogonal to each other and both being substantially parallel to the planar surface of the semiconductor substrate, wherein (i) each memory stack comprises a plurality of active layers, each active layer comprising a first conductive layer (24) and a second conductive layer (26) spaced apart by a first isolation layer (31); and (ii) the plurality of active layers being provided one on top of another along a third direction substantially normal to the planar surface of the semiconductor substrate and being isolated one from the other active layer by a second isolation layer (34); and a plurality of gate electrode structures (66) being provided in the trenches of the first type and arranged spaced apart in the second direction, the gate electrode structures extending in the third direction substantially normal to the planar surface of the semiconductor substrate, each gate electrode structure including (i) a semiconductor layer (channel 60) formed on the sidewalls of the trenches of the first type and in contact with the first and second conductive layers in the third direction along (parallel to, the contact direction refers to the direction in which forces are applied between contact surfaces, typically perpendicular to the surface) the sidewalls of the trenches of the first type [0084]; (ii) a ferroelectric dielectric layer (154) provided adjacent the semiconductor layer; and (iii) a gate conductor layer (66) formed adjacent the ferroelectric dielectric layer, wherein each active layer in the memory stack forms a plurality of thin-film ferroelectric memory transistors organized as a NOR memory string [0056], each memory transistor being formed at the intersection of the active layer and a gate electrode structure, the plurality of memory stacks forming a plurality of NOR memory strings in the trenches of the first type; and wherein the second isolation layer comprises a dielectric liner layer (56) formed on exposed surfaces in the memory stack and a first dielectric capping layer formed at an end of each second isolation layer facing the trenches of the second type, the remaining cavity in the second isolation layer forming an air gap cavity [0127].
Raja is silent with respect to the semiconductor channel is “a metal oxide semiconductor layer” “in contact with the first and second conductive layers in the third direction along the sidewalls of the trenches of the first type”.
FIG. 14 of Jackson discloses each active layer comprising a first conductive layer (108) and a second conductive layer (112) spaced apart by a first isolation layer (106); and (ii) the plurality of active layers being provided one on top of another along a third direction substantially normal to the planar surface of the semiconductor substrate and being isolated one from the other active layer by a second isolation layer (110); and a plurality of gate electrode structures (122) being provided in the trenches of the first type and arranged spaced apart in the second direction, the gate electrode structures extending in the third direction substantially normal to the planar surface of the semiconductor substrate, each gate electrode structure including (i) a semiconductor channel layer (118) formed on the sidewalls of the trenches of the first type and in contact with the first and second conductive layers along the sidewalls of the trenches of the first type; (ii) a ferroelectric dielectric [0008] layer (120) provided adjacent the semiconductor layer; and (iii) a gate conductor layer (122) formed adjacent the ferroelectric dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Raja, as taught by Jackson. The ordinary artisan would have been motivated to modify Raja in the above manner for purpose of controlling current flow to optimize the performance.
Raja as modified by Jackson is silent with respect to the vertical semiconductor channel is “a metal oxide semiconductor layer”.
Wu discloses a similar three-dimensional memory structure, wherein the vertical semiconductor channel is a metal oxide semiconductor layer [0044].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Raja, as taught by Wu. The ordinary artisan would have been motivated to modify Raja in the above manner for purpose of high electron mobility.
Claims 3, 4 and 19-23 rejected under 35 U.S.C. 103 as being unpatentable over Raja and Hoang, in view of Harari (U.S. Patent Pub. No. 2020/0328228) of record.
Regarding Claim 3
Raja as modified by Hoang discloses Claim 1, wherein the metal oxide semiconductor layer in contact with and in between the first and second conductive layers serving as a junctionless channel region of each memory transistor in each NOR memory string.
Raja as modified by Hoang is silent with respect to “the memory transistors within each NOR memory string share the first conductive layer, which serves as a common drain line and share the second conductive layer, which serves as a common source line”.
FIG. 1 of Harari discloses a similar three-dimensional memory structure, wherein the memory transistors within each NOR memory string share the first conductive layer, which serves as a common drain line and share the second conductive layer, which serves as a common source line [0005].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Raja, as taught by Harari. The ordinary artisan would have been motivated to modify Raja in the above manner for purpose of reducing resistance ([0008] of Harari).
Regarding Claim 4
FIG. 8 of Raja discloses within a memory stack of NOR memory strings, the channel regions for the memory transistors of a first NOR memory string are physically separated from the channel regions for the memory transistors of a second adjacent NOR memory string in the third direction by the second isolation layer.
Regarding Claim 19
FIGS. 5 and 8 of Raja discloses a three-dimensional memory structure formed above a planar surface of a semiconductor substrate (9), the memory structure comprising: a plurality of memory stacks arranged along a first direction and extending in a second direction, the memory stacks being separated by trenches of a first type (58) and trenches of a second type (79) alternately arranged in the first direction, the first and second directions being orthogonal to each other and both being substantially parallel to the planar surface of the semiconductor substrate, wherein (i) each memory stack comprises a plurality of active layers, each active layer comprising a first conductive layer (24) and a second conductive layer (26) spaced apart by a first isolation layer (31); and (ii) the plurality of active layers being provided one on top of another along a third direction substantially normal to the planar surface of the semiconductor substrate and being isolated one from the other active layer by a second isolation layer (34); and a plurality of gate electrode structures (66) being provided in the trenches of the first type and arranged spaced apart in the second direction, the gate electrode structures extending in the third direction substantially normal to the planar surface of the semiconductor substrate, each gate electrode structure including (i) a semiconductor layer (60) formed on the sidewalls of the trenches of the first type and in contact with the first and second conductive layers in the third direction along (parallel to, the contact direction refers to the direction in which forces are applied between contact surfaces, typically perpendicular to the surface) along the sidewalls of the trenches of the first type [0084]; (ii) a ferroelectric dielectric layer (154) provided adjacent the semiconductor layer; and (iii) a gate conductor layer (66) formed adjacent the ferroelectric dielectric layer, wherein each active layer in the memory stack forms a plurality of thin-film ferroelectric memory transistors organized as a NOR memory string [0056], each memory transistor being formed at the intersection of the active layer and a gate electrode structure, the plurality of memory stacks forming a plurality of NOR memory strings in the trenches of the first type.
Raja is silent with respect to the semiconductor channel is “a metal oxide semiconductor layer” and “the first isolation layer comprises a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant, the second dielectric layer being formed between the semiconductor oxide layer and the first dielectric layer, the second dielectric constant being greater than the first dielectric constant”.
FIG. 6A of Hoang discloses a similar three-dimensional memory structure, comprising a metal oxide semiconductor layer (530) [0055] formed on the sidewalls of the trenches of the first type and in contact with the first (511) and second (512) conductive layers along the sidewalls of the trenches of the first type (parallel to the vertical direction); (FIG. 3) a ferroelectric [0035] dielectric layer (318) provided adjacent the semiconductor oxide layer (314) [0037]; and a gate conductor layer (317) formed adjacent the ferroelectric dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Raja, as taught by Hoang, because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values ([0037] of Hoang), MPEP 2144.06. The ordinary artisan would have been motivated to modify Raja in the above manner for purpose of chemical and physical stability.
Raja as modified by Hoang is silent with respect to “the first isolation layer comprises a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant, the second dielectric layer being formed between the semiconductor oxide layer and the first dielectric layer, the second dielectric constant being greater than the first dielectric constant”.
FIG. 3 of Harari discloses a similar three-dimensional memory structure, wherein the first isolation layer comprises a first dielectric layer (102a, silicon oxide [0066]) having a first dielectric constant (3.9-4.9) and a second dielectric layer (106, silicon nitride [0008]) having a second dielectric constant (6-9), the second dielectric layer being formed between the semiconductor oxide layer and the first dielectric layer, the second dielectric constant being greater than the first dielectric constant [0066].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Raja, as taught by Harari. The ordinary artisan would have been motivated to modify Raja in the above manner for purpose of reducing resistance ([0008] of Harari).
Regarding Claim 20
Harari discloses the first dielectric layer comprises a silicon dioxide layer [0066]. Asami discloses the second dielectric layer is formed from a material selected from hafnium oxide or silicon oxynitride [0217].
Regarding Claim 21
Harari discloses the second dielectric layer has a thickness between 3-10% of the first dielectric layer in the first direction [0067].
Regarding Claim 22
FIG. 5 of Raja discloses the second dielectric layer (34) is in electrical contact with the metal oxide semiconductor layer.
Regarding Claim 23
FIG. 5 of Raja discloses the second dielectric layer (34) is formed adjacent the metal oxide semiconductor layer and extends from the first conductive layer to the second conductive layer.
Claim 19 rejected under 35 U.S.C. 103 as being unpatentable over Raja and Tsuda, in view of Harari (U.S. Patent Pub. No. 2020/0328228) of record.
Regarding Claim 19
FIGS. 5 and 8 of Raja discloses a three-dimensional memory structure formed above a planar surface of a semiconductor substrate (9), the memory structure comprising: a plurality of memory stacks arranged along a first direction and extending in a second direction, the memory stacks being separated by trenches of the first type (58) and trenches of the second type (79) alternately arranged in the first direction, the first and second directions being orthogonal to each other and both being substantially parallel to the planar surface of the semiconductor substrate, wherein (i) each memory stack comprises a plurality of active layers, each active layer comprising a first conductive layer (24) and a second conductive layer (26) spaced apart by a first isolation layer (31); and (ii) the plurality of active layers being provided one on top of another along a third direction substantially normal to the planar surface of the semiconductor substrate and being isolated one from the other active layer by a second isolation layer (34); and a plurality of gate electrode structures (66) being provided in the trenches of the first type and arranged spaced apart in the second direction, the gate electrode structures extending in the third direction substantially normal to the planar surface of the semiconductor substrate, each gate electrode structure including (i) a semiconductor oxide layer (57) formed on the sidewalls of the trenches of the first type and in contact with the first and second conductive layers in the third direction along the sidewalls of the trenches of the first type [0084]; (ii) a ferroelectric dielectric layer (154) provided adjacent the semiconductor oxide layer; and (iii) a gate conductor layer (66) formed adjacent the ferroelectric dielectric layer, wherein each active layer in the memory stack forms a plurality of thin-film ferroelectric memory transistors organized as a NOR memory string [0056], each memory transistor being formed at the intersection of the active layer and a gate electrode structure, the plurality of memory stacks forming a plurality of NOR memory strings in the trenches of the first type; and wherein the second isolation layer comprises a dielectric liner layer (56) formed on exposed surfaces in the memory stack and a first dielectric capping layer formed at an end of each second isolation layer facing the trenches of the second type, the remaining cavity in the second isolation layer forming an air gap cavity [0127].
Raja does not explicitly state the semiconductor oxide is “a metal oxide semiconductor layer”. However, by definition, semiconductor oxides are metal oxides that exhibit semiconductor properties.
Furthermore, FIG. 3 of Tsuda discloses a similar three-dimensional memory structure, wherein semiconductor oxide layer is a metal oxide semiconductor layer [0177].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Raja, as taught by Tsuda, because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values, MPEP 2144.06. The ordinary artisan would have been motivated to modify Raja in the above manner for purpose of high electron mobility.
Raja as modified by Tsuda is silent with respect to “the first isolation layer comprises a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant, the second dielectric layer being formed between the semiconductor oxide layer and the first dielectric layer, the second dielectric constant being greater than the first dielectric constant”.
FIG. 3 of Harari discloses a similar three-dimensional memory structure, wherein the first isolation layer comprises a first dielectric layer (102a, silicon oxide [0066]) having a first dielectric constant (3.9-4.9) and a second dielectric layer (106, silicon nitride [0008]) having a second dielectric constant (6-9), the second dielectric layer being formed between the semiconductor oxide layer and the first dielectric layer, the second dielectric constant being greater than the first dielectric constant [0066].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Raja, as taught by Harari. The ordinary artisan would have been motivated to modify Raja in the above manner for purpose of reducing resistance ([0008] of Harari).
Claim 19 rejected under 35 U.S.C. 103 as being unpatentable over Raja, Jackson and Wu, in view of Harari.
Regarding Claim 19
FIGS. 5 and 8 of Raja discloses a three-dimensional memory structure formed above a planar surface of a semiconductor substrate (9), the memory structure comprising: a plurality of memory stacks arranged along a first direction and extending in a second direction, the memory stacks being separated by trenches of the first type (58) and trenches of the second type (79) alternately arranged in the first direction, the first and second directions being orthogonal to each other and both being substantially parallel to the planar surface of the semiconductor substrate, wherein (i) each memory stack comprises a plurality of active layers, each active layer comprising a first conductive layer (24) and a second conductive layer (26) spaced apart by a first isolation layer (31); and (ii) the plurality of active layers being provided one on top of another along a third direction substantially normal to the planar surface of the semiconductor substrate and being isolated one from the other active layer by a second isolation layer (34); and a plurality of gate electrode structures (66) being provided in the trenches of the first type and arranged spaced apart in the second direction, the gate electrode structures extending in the third direction substantially normal to the planar surface of the semiconductor substrate, each gate electrode structure including (i) a semiconductor layer (channel 60) formed on the sidewalls of the trenches of the first type and in contact with the first and second conductive layers in the third direction along (parallel to, the contact direction refers to the direction in which forces are applied between contact surfaces, typically perpendicular to the surface) the sidewalls of the trenches of the first type [0084]; (ii) a ferroelectric dielectric layer (154) provided adjacent the semiconductor layer; and (iii) a gate conductor layer (66) formed adjacent the ferroelectric dielectric layer, wherein each active layer in the memory stack forms a plurality of thin-film ferroelectric memory transistors organized as a NOR memory string [0056], each memory transistor being formed at the intersection of the active layer and a gate electrode structure, the plurality of memory stacks forming a plurality of NOR memory strings in the trenches of the first type; and wherein the second isolation layer comprises a dielectric liner layer (56) formed on exposed surfaces in the memory stack and a first dielectric capping layer formed at an end of each second isolation layer facing the trenches of the second type, the remaining cavity in the second isolation layer forming an air gap cavity [0127].
Raja is silent with respect to the semiconductor channel is “a metal oxide semiconductor layer” “in contact with the first and second conductive layers in the third direction along the sidewalls of the trenches of the first type”.
FIG. 14 of Jackson discloses each active layer comprising a first conductive layer (108) and a second conductive layer (112) spaced apart by a first isolation layer (106); and (ii) the plurality of active layers being provided one on top of another along a third direction substantially normal to the planar surface of the semiconductor substrate and being isolated one from the other active layer by a second isolation layer (110); and a plurality of gate electrode structures (122) being provided in the trenches of the first type and arranged spaced apart in the second direction, the gate electrode structures extending in the third direction substantially normal to the planar surface of the semiconductor substrate, each gate electrode structure including (i) a semiconductor channel layer (118) formed on the sidewalls of the trenches of the first type and in contact with the first and second conductive layers along the sidewalls of the trenches of the first type; (ii) a ferroelectric dielectric [0008] layer (120) provided adjacent the a semiconductor channel layer (118); and (iii) a gate conductor layer (122) formed adjacent the ferroelectric dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Raja, as taught by Jackson. The ordinary artisan would have been motivated to modify Raja in the above manner for purpose of controlling current flow to optimize the performance.
Raja as modified by Jackson is silent with respect to the vertical semiconductor channel is “a metal oxide semiconductor layer”.
Wu discloses a similar three-dimensional memory structure, wherein the vertical semiconductor channel is a metal oxide semiconductor layer [0044].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Raja, as taught by Wu. The ordinary artisan would have been motivated to modify Raja in the above manner for purpose of high electron mobility.
Raja as modified by Jackson and Wu is silent with respect to “the first isolation layer comprises a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant, the second dielectric layer being formed between the semiconductor oxide layer and the first dielectric layer, the second dielectric constant being greater than the first dielectric constant”.
FIG. 3 of Harari discloses a similar three-dimensional memory structure, wherein the first isolation layer comprises a first dielectric layer (102a, silicon oxide [0066]) having a first dielectric constant (3.9-4.9) and a second dielectric layer (106, silicon nitride [0008]) having a second dielectric constant (6-9), the second dielectric layer being formed between the semiconductor oxide layer and the first dielectric layer, the second dielectric constant being greater than the first dielectric constant [0066].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Raja, as taught by Harari. The ordinary artisan would have been motivated to modify Raja in the above manner for purpose of reducing resistance ([0008] of Harari).
Pertinent Art
U.S. Patent Pub. No. 2018/0366489, 2019/0244971, 2021/0313349, 2021/0013224, 2019/0355747 and 2019/0198509.
Response to Arguments
Applicant’s arguments with respect to Rajashekhar have been considered they but are not persuasive. The semiconductor channel layer (60) of Rajashekhar is formed on the sidewalls of the trenches of the first type and in contact with the first (24) and second (26) conductive layers in the third direction along the sidewalls of the trenches of the first type (the contact is along a direction parallel to the vertical direction). The contact direction refers to the direction in which forces are applied between contact surfaces, typically perpendicular to the surface. Applicant’s arguments with respect to Hoang have been considered they but are not persuasive. It has long been held that an intermediate product or article can anticipate a claimed article even if the intermediate product is merely a stage in the final production of a non-anticipatory article. See In re Mullin, 481 F.2d 1333, 1335-6 (CCPA 1973). Applicant’s arguments with respect to Jackson have been considered they but are not persuasive. FIG. 14 of Jackson discloses each active layer comprising a first conductive layer (108) and a second conductive layer (112) spaced apart by a first isolation layer (106); and (ii) the plurality of active layers being provided one on top of another along a third direction substantially normal to the planar surface of the semiconductor substrate and being isolated one from the other active layer by a second isolation layer (110); and a plurality of gate electrode structures (122) being provided in the trenches of the first type and arranged spaced apart in the second direction, the gate electrode structures extending in the third direction substantially normal to the planar surface of the semiconductor substrate, each gate electrode structure including (i) a semiconductor channel layer (118) formed on the sidewalls of the trenches of the first type and in contact with the first and second conductive layers along the sidewalls of the trenches of the first type; (ii) a ferroelectric dielectric [0008] layer (120) provided adjacent the a semiconductor channel layer (118); and (iii) a gate conductor layer (122) formed adjacent the ferroelectric dielectric layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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