Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/26/2026 has been entered.
Claim Rejections Withdrawal
Applicant’s amendment of Claim 1 is acknowledged. Thus, the rejection under 112(b) is withdrawn.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 12 and 45-47 rejected under 35 U.S.C. 103 as being unpatentable over Yang (U.S. Patent Pub. No. 2022/0028894) of record, in view of Lee (U.S. Patent Pub. No. 2022/0367479) of record.
Regarding Claim 1
FIG. 10 of Yang discloses a three-dimensional memory structure, the memory structure comprising: a plurality of memory stacks and a plurality of trenches arranged along a first direction, each memory stack being separated from each of its immediately neighboring memory stacks along the first direction by a trench (filled with 203/215) of the plurality of trenches, each memory stack and each trench extending in a second direction, the first and second directions being orthogonal to each other, wherein (i) each memory stack comprises at least one active layer, the active layer comprising a first conductive layer (223/219S) and a second conductive layer (223/219D) spaced apart by a first isolation layer (215); and (ii) the trenches comprise trenches of a first type (filled with 203/205) and trenches of a second type (filled with 215), alternately arranged along the first direction; a plurality of gate electrode structures being provided in the trenches of the first type (filled with 203) and arranged spaced apart in the second direction, the gate electrode structures extending in a third direction substantially normal to the first and second directions, each gate electrode structure including (i) a metal oxide semiconductor [0050] layer (213) formed on the sidewalls of the trenches of the first type and in contact with the first and second conductive layers along the sidewalls of the trenches of the first type; (ii) a ferroelectric [0022] dielectric layer (211) provided adjacent the metal oxide semiconductor layer; and (iii) a gate conductor [0023] layer (203) formed adjacent the ferroelectric dielectric layer; and an isolation material (215) provided in the trenches of the second type, wherein each active layer in the memory stack forms a plurality of thin-film ferroelectric memory transistors organized as a NOR memory string [0155], each memory transistor being formed at the intersection of the active layer and a gate electrode structure, the plurality of memory stacks forming a plurality of NOR memory strings in the trenches of the first type; and wherein the memory transistors within each NOR memory string share the first conductive layer, which serves as a common drain line, and share the second conductive layer, which serves as a common source line [0024], the metal oxide semiconductor layer in contact with and provided between the first and second conductive layers serving as a junctionless channel region of each memory transistor in each NOR memory string [0026].
Yang is silent with respect to the three-dimensional memory structure “formed above a planar surface of a semiconductor substrate” “the gate electrode structures extending in a third direction substantially normal to the planar surface of the semiconductor substrate”.
FIG. 1 of Lee discloses a similar three-dimensional memory structure formed above a planar surface of a semiconductor substrate (101), the memory structure comprising: a plurality of memory stacks arranged along a first direction and extending in a second direction, wherein a plurality of gate electrode structures (GS) extending in a third direction substantially normal to the planar surface [0022] of the semiconductor substrate and being arranged spaced apart in the second direction, wherein each gate electrode structure includes a metal oxide semiconductor [0030] layer (140) formed on the sidewalls of the trenches of the first type and in contact with the first (142) and second (144) conductive layers along the sidewalls of the trenches of the first type; a ferroelectric [0028] dielectric layer (150) provided adjacent the metal oxide semiconductor layer; and (iii) a gate conductor layer (170) formed adjacent the ferroelectric dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Yang, as taught by Lee. The ordinary artisan would have been motivated to modify Yang in the above manner for purpose of high performance and high integration ([0003] of Lee).
Regarding Claim 12
Yang discloses the metal oxide semiconductor layer comprises one of an indium gallium zinc oxide (IGZO) layer, an indium zinc oxide (IZO) layer, an indium tungsten oxide (IWO) layer, or an indium tin oxide (ITO) layer [0040].
Regarding Claim 45
FIG. 1 of Yang discloses the second semiconductor substrate comprises a logic integrated circuit including a processor core and the memory controller circuit is formed in a portion of the second semiconductor substrate [0013].
Regarding Claim 46
The claim “the gate conductor layer in each gate electrode structure activates first and second ferroelectric memory transistors in each active layer in respective first and second memory strings bordering the gate electrode structure” containing a recitation with respect to the manner in which a claimed apparatus is intended to be employed. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Yang teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Regarding Claim 47
The claim “in response to the gate conductor layer being biased to a first potential to program or erase the first ferroelectric memory transistor, an inhibit voltage is applied to the common drain line associated with the second ferroelectric memory transistor to prevent the second ferroelectric memory transistor from being program or erased” containing a recitation with respect to the manner in which a claimed apparatus is intended to be employed. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Yang teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Claims 1 and 56 rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar (U.S. Patent Pub. No. 2021/0242241) of record, in view of Tsuda (U.S. Patent Pub. No. 2023/0352090).
Regarding Claim 1
FIG. 22 of Rajashekhar discloses a three-dimensional memory structure formed above a planar surface of a semiconductor substrate (9), the memory structure comprising: a plurality of memory stacks arranged along a first direction, each memory stack and each trench extending in a second direction, the first and second directions being orthogonal to each other and both being substantially parallel to the planar surface of the semiconductor substrate, wherein (i) each memory stack comprises at least one active layer, the active layer comprising a first conductive layer (22) and a second conductive layer (28) spaced apart by a first isolation layer (38), each memory stack being separated from each of its immediately neighboring memory stacks along the first direction by a trench (FIG. 13); and (ii) the trenches comprise trenches of a first type (49, FIG. 5) and trenches of a second type (79, FIG. 10), alternately arranged along the first direction; a plurality of gate electrode structures being provided in the trenches of the first type and arranged spaced apart in the second direction [0111], the gate electrode structures extending in a third direction substantially normal to the planar surface of the semiconductor substrate, each gate electrode structure including (i) a semiconductor oxide layer (157) formed on the sidewalls of the trenches of the first type and in contact with the first and second conductive layers in the third direction along the sidewalls of the trenches of the first type [0222]; (ii) a ferroelectric dielectric [0223] layer (154) provided adjacent the semiconductor oxide layer; and (iii) a gate conductor layer (66) formed adjacent the ferroelectric dielectric layer [0126]; and an isolation material (76) provided in the trenches of the second type [0122], wherein each active layer in the memory stack forms a plurality of thin-film ferroelectric memory transistors organized as a NOR memory string [0155], each memory transistor being formed at the intersection of the active layer and a gate electrode structure, the plurality of memory stacks forming a plurality of NOR memory strings in the trenches of the first type ; and wherein the memory transistors within each NOR memory string share the first conductive layer, which serves as a common drain line [0116], and share the second conductive layer, which serves as a common source line [0118], the metal oxide semiconductor layer in contact with and provided between the first and second conductive layers serving as a junctionless channel region of each memory transistor in each NOR memory string.
Rajashekhar does not explicitly state the semiconductor oxide is “a metal oxide semiconductor layer”. However, by definition, semiconductor oxides are metal oxides that exhibit semiconductor properties.
Furthermore, FIG. 3 of Tsuda discloses a similar three-dimensional memory structure, wherein semiconductor oxide layer is a metal oxide semiconductor layer [0177].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Rajashekhar, as taught by Tsuda, because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values, MPEP 2144.06. The ordinary artisan would have been motivated to modify Rajashekhar in the above manner for purpose of high electron mobility.
Regarding Claim 56
FIG. 22 of Rajashekhar discloses the metal oxide semiconductor layer (157) is a continuous layer on the sidewalls of the trenches of the first type in the second direction.
Claims 1, 2, 4-11, 13-17, 25, 43, 44 and 48-55 rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar (U.S. Patent Pub. No. 2021/0242241) of record, in view of Hoang (U.S. Patent Pub. No. 2023/0143057).
Regarding Claim 1
FIG. 22 of Rajashekhar discloses a three-dimensional memory structure formed above a planar surface of a semiconductor substrate (9), the memory structure comprising: a plurality of memory stacks arranged along a first direction, each memory stack and each trench extending in a second direction, the first and second directions being orthogonal to each other and both being substantially parallel to the planar surface of the semiconductor substrate, wherein (i) each memory stack comprises at least one active layer, the active layer comprising a first conductive layer (22) and a second conductive layer (28) spaced apart by a first isolation layer (38), each memory stack being separated from each of its immediately neighboring memory stacks along the first direction by a trench (FIG. 13); and (ii) the trenches comprise trenches of a first type (49, FIG. 5) and trenches of a second type (79, FIG. 10), alternately arranged along the first direction; a plurality of gate electrode structures being provided in the trenches of the first type and arranged spaced apart in the second direction [0111], the gate electrode structures extending in a third direction substantially normal to the planar surface of the semiconductor substrate, each gate electrode structure including (i) a semiconductor channel [0168] layer (160) formed on the sidewalls of the trenches of the first type and in contact with the first and second conductive layers in the third direction along the sidewalls of the trenches of the first type; (ii) a ferroelectric dielectric [0223] layer (154) provided adjacent the semiconductor oxide layer; and (iii) a gate conductor layer (66) formed adjacent the ferroelectric dielectric layer [0126]; and an isolation material (76) provided in the trenches of the second type [0122], wherein each active layer in the memory stack forms a plurality of thin-film ferroelectric memory transistors organized as a NOR memory string [0155], each memory transistor being formed at the intersection of the active layer and a gate electrode structure, the plurality of memory stacks forming a plurality of NOR memory strings in the trenches of the first type ; and wherein the memory transistors within each NOR memory string share the first conductive layer, which serves as a common drain line [0116], and share the second conductive layer, which serves as a common source line [0118], the metal oxide semiconductor layer in contact with and provided between the first and second conductive layers serving as a junctionless channel region of each memory transistor in each NOR memory string.
Rajashekhar is silent with respect to the semiconductor channel is “a metal oxide semiconductor layer”.
FIG. 6A of Hoang discloses a similar three-dimensional memory structure, comprising a metal oxide semiconductor channel (530) [0055] formed on the sidewalls of the trenches of the first type and in contact with the first (511) and second (512) conductive layers along the sidewalls of the trenches of the first type (parallel to the vertical direction); (FIG. 3) a ferroelectric [0035] dielectric layer (318) provided adjacent the semiconductor oxide layer (314) [0037]; and a gate conductor layer (317) formed adjacent the ferroelectric dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Raja, as taught by Rajashekhar, because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values ([0037] of Hoang), MPEP 2144.06. The ordinary artisan would have been motivated to modify Rajashekhar in the above manner for purpose of chemical and physical stability.
Regarding Claim 4
FIG. 16 of Rajashekhar discloses each memory stack comprises a plurality of active layers being provided one on top of another along the third direction and being isolated one from the other active layer by a second isolation layer (39), the plurality of memory stacks forming a plurality of stacks of NOR memory strings of thin-film memory transistors in the trenches of the first type.
Regarding Claim 5
FIG. 16 of Rajashekhar discloses within a memory stack of NOR memory strings, the channel regions for the memory transistors of a first NOR memory string are separated from the channel regions for the memory transistors of a second adjacent NOR memory string in the third direction by the second isolation layer.
Regarding Claim 6
FIG. 12 of Rajashekhar discloses within a memory stack of NOR memory strings, the semiconductor oxide layer is removed in a region between two adjacent active layers in the third direction.
Regarding Claim 7
FIG. 12 of Rajashekhar discloses within a memory stack of NOR memory strings, a part of the metal oxide semiconductor layer opposite the ferroelectric dielectric layer is removed in a region between two adjacent active layers in the third direction, at least part of the metal oxide semiconductor layer (as modified by Hoang) remaining in the region between two adjacent active layers.
Regarding Claim 8
FIG. 16 of Rajashekhar discloses the second isolation layer (39) comprises an air gap cavity [0134].
Regarding Claim 9
FIG. 12 of Rajashekhar discloses the isolation material (62) in the trenches of the second type comprises a silicon oxide layer [0105].
Regarding Claim 10
FIG. 12 of Rajashekhar discloses the ferroelectric dielectric layer comprises a doped hafnium oxide layer [0107].
Regarding Claim 11
FIG. 22 of Rajashekhar discloses an interfacial layer (56) formed between the metal oxide semiconductor layer and the ferroelectric dielectric layer (154).
Regarding Claim 13
FIG. 12 of Rajashekhar discloses the metal oxide semiconductor layer comprises a first metal oxide semiconductor layer (portion of 160 having larger contact area with the first and second conductive layers) and a second metal oxide semiconductor layer (portion of 60 having smaller contact area with the first and second conductive layers), the first metal oxide semiconductor layer being provided in contact with the first and second conductive layers and providing a contact resistance to the first and second conductive layers lower than the contact resistance of the second metal oxide semiconductor layer.
Regarding Claim 14
FIG. 12 of Rajashekhar discloses the first conductive layer and the second conductive layer each comprises a metal layer.
Regarding Claim 15
FIG. 12 of Rajashekhar discloses the first isolation layer (31) comprises a silicon oxide layer [0067].
Regarding Claim 16
FIG. 17 of Rajashekhar discloses a channel length of each memory transistor is a function of a thickness of the first isolation layer in the third direction.
Regarding Claim 17
FIG. 12 of Rajashekhar discloses the thickness of the first isolation layer in the third direction is in the range of 5-10 nm [0066].
Regarding Claim 25
The claim “in each memory transistor in the NOR memory string, the common drain line and the common source line are biased to substantially the same voltage during a program or an erase operation of the memory transistor” containing a recitation with respect to the manner in which a claimed apparatus is intended to be employed. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Rajashekhar teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Regarding Claim 43
FIG. 12 of Rajashekhar discloses circuitry for supporting memory operations of the memory transistors is formed at the planar surface of the semiconductor substrate substantially underneath the plurality of memory stacks.
Regarding Claim 44
FIG. 12 of Rajashekhar discloses a plurality of connectors providing data path signals from the circuitry supporting the memory operations of the plurality of NOR memory strings, the plurality of connectors to be connected to corresponding connectors of a memory controller circuit formed on a second semiconductor substrate separate from the semiconductor substrate on which the memory structure is formed, the memory controller circuit including memory control circuitry for accessing and operating the memory transistors in the plurality of NOR memory strings in the memory structure.
Regarding Claim 48
FIG. 12 of Rajashekhar discloses the gate conductor layer comprises a metal layer of a first type formed on the ferroelectric dielectric layer.
Regarding Claim 49
Rajashekhar discloses the gate conductor layer comprises a conductive layer selected from titanium nitride or tungsten nitride [0103].
Regarding Claim 50
FIG. 12 of Rajashekhar discloses the gate conductor layer comprises a first metal layer formed on the ferroelectric dielectric layer and a second metal layer formed on the first metal layer.
Regarding Claim 51
Rajashekhar discloses the first metal layer comprises a metal layer selected from titanium nitride or tungsten nitride and the second metal layer comprises a metal layer selected from tungsten, or molybdenum [0103].
Regarding Claim 52
The limitation “within a trench of the first type, the semiconductor oxide layer is removed in a region between two adjacent gate electrode structures in the second direction” is considered to be a process or functional limitation. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), MPEP 2113. Since Rajashekhar discloses an identical or substantially identical device, Claim 52 is unpatentable even though the Rajashekhar product was made by a different process.
Regarding Claim 53
The limitation “within a trench of the first type, a part of the metal oxide semiconductor layer is removed in a region between two adjacent gate electrode structures in the second direction, at least part of the metal oxide semiconductor layer remaining in the region between two adjacent gate electrode structures” is considered to be a process or functional limitation. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), MPEP 2113. Since Rajashekhar discloses an identical or substantially identical device, Claim 53 is unpatentable even though the Rajashekhar product was made by a different process.
Regarding Claim 54
FIG. 12 of Rajashekhar discloses each memory stack in the plurality of memory stacks further comprises a third conductive layer formed between the bottommost active layer and the semiconductor structure.
Regarding Claim 55
FIG. 12 of Rajashekhar discloses in each gate electrode structure, the gate conductor layer extends into the semiconductor substrate.
Claim 3 rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar and Hoang, in view of Choi (U.S. Patent Pub. No. 2017/0271016) of record.
Regarding Claim 3
Rajashekhar as modified by Hoang discloses Claim 1.
Rajashekhar as modified by Hoang is silent with respect to “the common source line is an electrically floating source”.
FIG. 5 of Choi discloses a similar 3D memory structure, wherein the common source line (CSL) is an electrically floating source [0007].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Rajashekhar, as taught by Choi. The ordinary artisan would have been motivated to modify Rajashekhar in the above manner for purpose of improving boosting efficiency and power consumption ([0006] of Choi).
Claims 18-21, 23 and 24 rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar and Hoang, in view of Harari (U.S. Patent Pub. No. 2019/0244971) of record.
Regarding Claim 18
Rajashekhar as modified by Hoang discloses Claim 1.
Rajashekhar as modified by Hoang is silent with respect to “a first group of memory transistors within each NOR memory string is designated as precharge transistors, the precharge transistors being activated during a precharge operation to electrically connect the first and second conductive layers in each NOR memory string to equalize the voltage on the second conductive layer to the voltage on the first conductive layer”.
FIG. 3 of Harari discloses a similar 3D memory structure, comprising a first group of memory transistors within each NOR memory string is designated as precharge transistors, the precharge transistors (370) [0035] being activated during a precharge operation to electrically connect the first and second conductive layers in each NOR memory string to equalize the voltage on the second conductive layer to the voltage on the first conductive layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Rajashekhar, as taught by Harari. The ordinary artisan would have been motivated to modify Rajashekhar in the above manner for purpose of setting a voltage on shared local source line ([0035] of Harari).
Regarding Claim 19
FIG. 3 of Harari discloses in each NOR memory string, a memory transistor in the first group is selected to operate as the precharge transistor for the NOR memory string in a substantially random manner.
Regarding Claim 20
FIG. 3 of Harari discloses in each NOR memory string, each of the memory transistors in the first group is selected in turn to operate as the precharge transistor for a given number of precharge operations or for a given time interval.
Regarding Claim 21
FIG. 3 of Harari discloses in each NOR memory string, a memory transistor in the first group selected to operate as the precharge transistor is evaluated to determine a health condition of the selected memory transistor, and in response to the selected memory transistor being determined to have a health condition indicative of a failing condition, the selected memory transistor is retired and another memory transistor in the first group is selected to operate as the precharge transistor for the NOR memory string.
Regarding Claim 23
FIG. 3 of Harari discloses a plurality of non-memory transistors formed in each NOR memory string, the non-memory transistors being designated as precharge transistors, the precharge transistors being activated during a precharge operation to electrically connect the first and second conductive layers in each NOR memory string to set the voltage on the second conductive layer to equal to the voltage on the first conductive layer.
Regarding Claim 24
FIG. 3 of Harari discloses in each NOR memory string, each of the non-memory precharge transistors shares with the memory transistors the second conductive layer as a common source line, and shares with the memory transistors the first conductive layer as a common drain line, and each non-memory precharge transistor includes the metal oxide semiconductor layer as a junctionless channel region, wherein the non-memory precharge transistor includes a non-polarizable gate dielectric layer.
Claim 22 rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar and Hoang, in view of Gillingham (U.S. Patent No. 5,708,619) of record.
Regarding Claim 22
Rajashekhar as modified by Hoang discloses Claim 1.
Rajashekhar as modified by Hoang is silent with respect to “the memory transistors in the NOR memory strings each have a first transistor width, each NOR memory string further comprises a second group of memory transistors having a second transistor width greater than the first transistor width, the memory transistors in the second group being designated as precharge transistors, the precharge transistors being activated during a precharge operation to electrically connect the first and second conductive layers in each NOR memory string to equalize the voltage on the second conductive layer to the voltage on the first conductive layer”.
Gillingham discloses a similar 3D memory structure, wherein the memory transistors in the NOR memory strings each have a first transistor width, each NOR memory string further comprises a second group of memory transistors having a second transistor width greater than the first transistor width, the memory transistors in the second group being designated as precharge transistors, the precharge transistors being activated during a precharge operation to electrically connect the first and second conductive layers in each NOR memory string to equalize the voltage on the second conductive layer to the voltage on the first conductive layer (Claim 2).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Rajashekhar, as taught by Harari. The ordinary artisan would have been motivated to modify Rajashekhar in the above manner for purpose of setting a voltage on shared local source line ([0035] of Harari).
Claims 29 and 30 rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar and Hoang, in view of Liao (WO 2020/191793) of record.
Regarding Claim 29
Rajashekhar as modified by Hoang discloses Claim 1.
Rajashekhar as modified by Hoang is silent with respect to “each of the thin-film ferroelectric memory transistors comprises a front-gate electrode formed by the gate conductor layer and an electrically floating back-gate electrode formed by a back-gate layer provided in the first isolation layer”.
FIG. 3 of Liao discloses a similar thin-film ferroelectric memory transistor, wherein each of the thin-film ferroelectric memory transistors comprises a front-gate electrode formed by the gate conductor layer and an electrically floating back-gate electrode formed by a back-gate layer provided in the first isolation layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Rajashekhar, as taught by Liao. The ordinary artisan would have been motivated to modify Rajashekhar in the above manner for purpose of electrical reliability (Abstract of Liao).
Regarding Claim 30
The claim “wherein the electrically floating back-gate electrode at each memory transistor has its voltage controlled by capacitive coupling to the voltages on the first conductive layer, the second conductive layer, and a portion of the metal oxide semiconductor layer” containing a recitation with respect to the manner in which a claimed apparatus is intended to be employed. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Rajashekhar teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Claims 31-35, 41 and 42 rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar, Hoang and Liao, in view of Lee (U.S. Patent Pub. No. 2016/0043093) of record.
Regarding Claim 31
Rajashekhar as modified by Hoang and Liao discloses Claim 29.
Rajashekhar as modified by Hoang and Liao is silent with respect to “the first isolation layer comprises a first dielectric layer formed adjacent the first conductive layer, a second dielectric layer formed adjacent the second conductive layer, and a third layer as the back-gate layer formed between the first and second dielectric layers and insulated from the first and second conductive layers, the third layer interacting with a portion of the semiconductor oxide layer to form the electrically floating back-gate electrode at each memory transistor”.
FIG. 7 of Lee discloses a similar 3D memory structure, wherein the first isolation layer comprises a first dielectric layer formed adjacent the first conductive layer, a second dielectric layer formed adjacent the second conductive layer, and a third layer as the back-gate layer formed between the first and second dielectric layers and insulated from the first and second conductive layers, the third layer interacting with a portion of the semiconductor oxide layer to form the electrically floating back-gate electrode at each memory transistor [0078].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Rajashekhar, as taught by Lee. The ordinary artisan would have been motivated to modify Rajashekhar in the above manner for purpose of improving performance and scalability ([0033] of Lee).
Regarding Claim 32
Modified Rajashekhar discloses the first conductive layer and the second conductive layer are spaced apart in the third direction by a first distance being a channel length of the thin-film ferroelectric memory transistor, the third layer having a thickness in the third direction being a portion of the channel length or being almost the entire channel length.
Regarding Claim 33
Rajashekhar discloses each of the first and second dielectric layers is formed from a material selected from silicon dioxide, silicon nitride, hafnium oxide, or a high dielectric constant material [0066].
Regarding Claim 34
Lee discloses the third layer is formed from a material selected from a semiconductor or a low resistivity material or a metallic material.
Regarding Claim 35
Lee discloses the third layer is formed from a material selected from undoped silicon, P-type or N-type doped silicon, undoped polysilicon, P-type or N-type doped polysilicon, silicon germanium, titanium nitride, tungsten, or molybdenum [0029].
Regarding Claim 41
The recitation of “at each thin-film ferroelectric memory transistor, the gate conductor layer operates as the front-gate electrode, and the first conductive layer together with the second conductive layer and the back-gate layer, operate substantially as the back-gate electrode of each of the ferroelectric memory transistors” is only a functional limitation. The structure recited in Rajashekhar is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Or where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1977) and MPEP 2112.01-02.
Regarding Claim 42
With respect to “for each of the plurality of thin-film ferroelectric memory transistors, an area in the ferroelectric dielectric layer between the front-gate electrode and the back-gate electrode is an area of maximum polarization of the program state and erase state of the ferroelectric memory transistors”, said area is considered to be a result effective variable, therefore, constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Pertinent Art
Kim (U.S. Patent Pub. No. 2007/0012992), Borukhov (U.S. Patent Pub. No. 2019/0333930), Makala (U.S. Patent Pub. No. 2020/0006376), Lu (U.S. Patent Pub. No. 2021/0375933) and Wu (U.S. Patent Pub. No. 2021/0407966).
Response to Arguments
Applicant’s arguments with respect to Claim 1 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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