DETAILED ACTION
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
a) Elements, ‘shared bottom source/drain region’, ‘backside power delivery network’ cited in claim 1 must be shown the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 1.
…
a shared bottom source/drain region directly connected to the backside power delivery network.
Referring to fig. 6B, the shared bottom source/drain region (612B) is connected to the backside power delivery network (674) via a backside contact (672B). Thus, the connection between the shared bottom source/drain region (612B) and the backside power delivery network (674) is not direct.
b) Elements, ‘a contact’, ‘shared bottom source/drain region’, ‘backside power delivery network’ cited in claim 6 must be shown the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 6.
………..
a contact on a frontside of the semiconductor device, wherein the contact is directly connected to 1) a selection from the group consisting of: i) a shared bottom source/drain region directly connected to the backside power delivery network, and ii) the backside power delivery network
Please provide element mapping of the above limitataion.
Fig. 6A-6B do not show a contact on the frontside (660B/662B/664B/666B) directly connected to shared bottom source/drain region (610B/612B). According to fig. 6B, frontside contact 662B on the frontside is connected to shared bottom source/drain region (612B) via shared backside contact (670B). Also, Fig. 6A-6B do not show a contact on the frontside (660B/662B/664B/666B) directly connected to the backside power delivery network (674). According to fig. 6B, frontside contact 662B is connected to the backside power delivery network (674) via elements (670B, 612B, 672B).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 cites, “a shared bottom source/drain region directly connected to the backside power delivery network”. However, referring to fig. 6B, the shared bottom source/drain region (612B) is connected to the backside power delivery network (674) via a backside contact (672B). Thus, the connection between the shared bottom source/drain region (612B) and the backside power delivery network (674) is not direct.
Again, claim 6 cites, “a contact on a frontside of the semiconductor device, wherein the contact is directly connected to 1) a selection from the group consisting of: i) a shared bottom source/drain region directly connected to the backside power delivery network, and ii) the backside power delivery network”. However, the specification including the drawings doesn’t describe or show i) a direct connection between a contact on a frontside and a shared bottom source/drain region ii) a direct connection between a contact on a frontside and a backside power delivery network, iii) a direct connection between a shared bottom source/drain region and a backside power delivery network.
Applicant is required to cancel the unsupported matter in the reply to this Office Action.
As claims 2-5 and 7-14 depend on the above rejected claim 1 and 6 respectively, they are also being rejected on the same reason.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 4 recites the limitation " bottom source/drain region of a third FET, wherein the bottom source/drain region is connected to the shared frontside contact.”. There is insufficient antecedent basis for the limitation “the bottom source/drain region”. For examination purpose, claim 4 will be considered as below:
4. The semiconductor device of claim 1, further comprising: a shared bottom source/drain region of a third FET, wherein the bottom source/drain region is connected to the shared frontside contact.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 4-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Do et al. (US 11189692 B2, Do‘692).
Regarding independent claim 1, Do‘692 teaches, “A semiconductor device (Fig. 1C and related description) comprising:
a first vertical-transport field-effect transistor (VTFET) (Fig. 1C: P2) on a wafer (Fig. 1A: SUB);
a second VTFET (Fig. 1C: N2) adjacent to the first VTFET on the wafer;
a backside power delivery network (Fig. 1C: CR3, CR4) on a backside of the wafer (see annotated Fig. 1C);
a shared frontside contact (Fig. 1C: M14, V06, V07), wherein the shared frontside contact is on a frontside of the wafer (see annotated Fig. 1C); and
the shared frontside contact is directly connected to a first top source/drain region (Fig. 1C: CA1) of the first VTFET, a second top source/drain region (Fig. 1C: CA2) of the second VTFET, and a shared bottom source/drain region (Fig. 1C: RX1, RX2) directly connected to the backside power delivery network (see annotated Fig. 1C).
Regarding claim 2, Do‘692 further teaches, “The semiconductor device of claim 1, wherein the first VTFET (P2) and the second VTFET (P1) are in parallel”.
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Regarding claim 4, Do‘692 further teaches, “The semiconductor device of claim 1, further comprising: a bottom source/drain region of a third FET (P1/N1, fig. 1A-1B), wherein the shared bottom source/drain region (RX1, RX2) is connected to the shared frontside contact (M14, V06, V07)”.
Regarding claim 5, Do‘692 further teaches, “The semiconductor device of claim 1, wherein the backside power delivery network (CR3, CR4) is selected from the group consisting of power and ground (M11 and M12)”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3, 15, 17-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Do‘692 as applied to claim 1 as above, and further in view of Sobue (US 20210082902 A1, hereinafter Sobue‘902) of record.
Regarding claim 3, Do‘692 teaches all the limitations described in claim 1.
But Do‘692 is silent upon the provision of wherein the first VTFET and the second VTFET are each a first width, wherein the first width is a contacted poly pitch (CPP), and wherein shared frontside contact is adjacent to the second VTFET by the first width.
However, Sobue‘902 teaches a vertical contact (e.g. via 28a in fig.6 or 228a,b in fig.24,30) connects the frontside shared contact (32 in fig.6 or 231 /232 in fig.24, 30) to the bottom source/drain region of the VTFETs (12 in fig.6 or 211 /212 in fig.24,30). The vertical contact (28a, 228a,b) of Sobue‘902 is also centered at approximately 1 CPP from the center of the adjacent VTFET, as clearly indicated by the grid lines in fig.6,24,30 (see also ¶ 0070 defining the "grid spacing" as the spacing used for placing the components at the time of designing, i.e. a pre-determined pitch, which is considered analogous to the CPP mentioned in the claim.
Do‘692 and Sobue‘902 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Do‘692 with the features of Sobue‘902 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Do‘692 and Sobue‘902 to arrange the VTFETs and the shared frontside contact according to the teachings of Sobue‘902 with a motivation of achieving high breakdown voltage and reducing off current. See Sobue‘902, ¶¶ 0002-0006.
Regarding independent claim 15, Do‘692 teaches, “A semiconductor device (Fig. 1C and related description) comprising:
a first vertical-transport field-effect transistor (VTFET) (Fig. 1C: P2) on a wafer (Fig. 1A: SUB);
a second VTFET (Fig. 1C: N2) adjacent to the first VTFET on the wafer;
a third VTFET (fig. 1B: P1) adjacent to the first VTFET on the wafer;
wherein the first VTFET, the second VTFET, and the third VTFET are each a first width, ((wherein the width is a contacted poly pitch (CPP))); and
a shared frontside contact (Fig. 1B-1C: M13, M14, V06, V07) connected to the first VTFET, second VTFET, and third VTFET,
wherein the shared frontside contact (Fig. 1B-1C: M13, M14, V06, V07) is on a frontside of the wafer (SUB) and electrically connected to a backside power delivery network (see annotated Fig. 1C).
But Do‘692 is silent upon the provision of wherein the width is a contacted poly pitch (CPP);
However, Sobue‘902 teaches a vertical contact (e.g. via 28a in fig.6 or 228a,b in fig.24,30) connects the frontside shared contact (32 in fig.6 or 231 /232 in fig.24, 30) to the bottom source/drain region of the VTFETs (12 in fig.6 or 211 /212 in fig.24,30). The vertical contact (28a, 228a,b) of Sobue‘902 is also centered at approximately 1 CPP from the center of the adjacent VTFET, as clearly indicated by the grid lines in fig.6,24,30 (see also ¶ 0070 defining the "grid spacing" as the spacing used for placing the components at the time of designing, i.e. a pre-determined pitch, which is considered analogous to the CPP mentioned in the claim.
Do‘692 and Sobue‘902 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Do‘692 with the features of Sobue‘902 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Do‘692 and Sobue‘902 to arrange the VTFETs and the shared frontside contact according to the teachings of Sobue‘902 with a motivation of achieving high breakdown voltage and reducing off current. See Sobue‘902, ¶¶ 0002-0006.
Regarding claim 17, Do‘692 modified with Sobue‘902 further teaches, “The semiconductor device of claim 15, wherein the shared frontside contact (131, fig. 12; ¶ 0101, Sobue‘902) is connected to a first top source/drain region of first VTFET, a second top source/drain region of the second VTFET and a third bottom source/drain region of the third VTFET”.
Regarding claim 18, Do‘692 modified with Sobue‘902 further teaches, “The semiconductor device of claim 15, wherein the shared frontside contact (131, fig. 12; ¶ 0101, Sobue‘902) is connected to a first top source/drain region of first VTFET, a second bottom source/drain region of the second VTFET and a third top source/drain region of the third VTFET”.
Regarding claim 20, Do‘692 modified with Sobue‘902 further teaches, “The semiconductor device of claim 15, wherein the first VTFET, second VTFET, and third VTFET are in parallel” (¶ 0093, Sobue‘902).
Claims 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Do‘692 as applied to claim 15 as above, and further in view of Do (US 20200144418 A1, hereinafter Do‘418) of record.
Regarding claim 16, Do‘692 teaches all the limitations described in claim 15.
But Do‘692 is silent upon the provision of wherein the shared frontside contact is horizontally adjacent to the first VTFET and second VTFET by the first width and wherein the shared frontside contact is vertically adjacent to the third VTFET by the first width.
However, Do‘418 teaches a similar VFETs (fig. 11-12), wherein the shared frontside contact (32/32_1c) is horizontally adjacent to the first VTFET (right-hand 16_P1 in fig.11B) and second VTFET (right-hand 16_N1 in fig.11B) by the first width (a distance that is equal to the pitch between the transistors i.e., first width = CPP along direction X) and wherein the shared frontside contact is vertically adjacent to the third VTFET by the first width (another portion of the shared frontside contact 32/32_1c (the one overlapping the right-hand 16_P1 in fig.11 B) is adjacent to the third VTFET (left-hand 16_P1 in fig.11 B) by the same distance).
Do‘692 and Do‘418 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Do‘692 with the features of Do‘418 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Do‘692 and Do‘418 to arrange the VTFETs and the shared frontside contact according to the teachings of Do‘418 with a motivation of exploiting high scalability and simpler interconnections between VFETs. See Do‘418, ¶¶ 0002-0004.
Regarding claim 19, Do‘692 modified with Do‘418 further teach, “The semiconductor device of claim 15, wherein the shared frontside contact (32, the straight portion parallel to the x axis in fig.11 B) is a second width, wherein the second width is double the first width (pitch between the transistor)”.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817