DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8-15, 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al (U.S. 2023/0035899).
The applied reference has a common Assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1. Lee et al discloses a semiconductor memory device (FIG. 4) comprising:
a substrate (FIG. 4, item 100);
a first conductive line (FIG. 4, item BL) on the substrate (FIG. 4, item 100);
a capping pattern (FIG. 4, item 137) that extends along an upper surface ([0060]) of the first conductive line (FIG. 4, item BL);
a spacer structure (FIG. 4, item SP) extends along a side surface of the first conductive line (FIG. 4, item BL) and a side surface of the capping pattern (FIG. 4, item 137)
a buried contact (FIG. 4, item XP) electrically connected (FIG. 3, item 103B) to the substrate (FIG. 4, item 100) on a side surface ([0077]) of the spacer structure (FIG. 4, item SP);
a barrier conductive film (FIG. 4, item 113) extending along the buried contact (FIG. 4, item XP) and the spacer structure (FIG. 4, item SP); and
a landing pad (FIG. 4, item LP and 111) electrically connected buried contact (FIG. 4, item XP), on the barrier conductive film (FIG. 4, item 113) and the capping pattern (FIG. 4, item 137),
wherein the landing pad (FIG. 4, item LP and 111) includes: a lower pad (FIG. 4, item 111) on the side surface of the capping pattern (FIG. 4, item 137) and the side surface of the spacer structure (FIG. 4, item SP); and an upper pad (FIG. 4, item LP) having a bottommost surface (FIG. 4, item 111_US) that is in contact ([0087]-[0089]) with an uppermost surface (FIG. 4, item 111_US) of the barrier conductive film (FIG. 4, item 113) and an uppermost surface (FIG. 4, item 137_US) of the capping pattern (FIG. 4, item 137), on the lower pad (FIG. 4, item 111),
wherein an upper part of the spacer structure (FIG. 4, item SP) includes a spacer recess (annotated FIG. 4, item spacer recess) having an upper part (FIG. 4, item 111_US) that is equal (annotated FIG. 4 shows spacer recess upper part equal to an uppermost surface of item 137) to the uppermost surface (FIG. 4, item 137_US) of the capping pattern (FIG. 4, item 137),
PNG
media_image1.png
766
682
media_image1.png
Greyscale
wherein the barrier conductive film (FIG. 4, item 113) extends along the spacer recess (annotated FIG. 4, item spacer recess) and does not cover ([0087]) the upper most surface (FIG. 4, item 137_US) of the capping pattern (FIG. 4, item 137).
Regarding claim 2. Lee et al disclose all the limitations of the semiconductor memory device of claim 1 above.
a spacer structure (FIG. 4, item SP) that includes a first side spacer (FIG. 4, item 123) and a second side spacer (FIG. 4, item 125) that are stacked sequentially on a side surface ([0074]) of the first conductive line (FIG. 4, item BL) and a side surface of the capping pattern (FIG. 4, item 137), the first side spacer (FIG. 4, item 123) and the second side spacer (FIG. 4, item 125) including different materials ([0074]) from each other ([0074]);
wherein the barrier conductive film (FIG. 4, item 113) extends along the spacer recess (annotated FIG. 4, item spacer recess) and is in contact ([0076]-[0077]) with an upper surface of the first side spacer (FIG. 4, item 123) and an upper surface of the second side spacer (FIG. 4, item 125) that are each lower than the uppermost surface (FIG. 4, item 137_US) of the capping pattern (FIG. 4, item 137).
Regarding claim 3. Lee et al further discloses wherein the first side spacer (FIG. 4, item 123) includes silicon oxide ([0074]), and wherein the second side spacer (FIG. 4, item 125) includes silicon nitride ([0074]).
Regarding claim 4. Lee et al further discloses wherein the spacer structure (FIG. 4, item SP) further includes a base spacer (FIG. 4, item 121) that is between the first conductive line (FIG. 4, item BL) and the first side spacer (FIG. 4, item 123) and between the capping pattern (FIG. 4, item 37) and the first side spacer (FIG. 4, item 123), and includes a material different ([0074], the spacer liners 121 may include a material having etching selectivity with respect to the first spacers 123) from the first side spacer (FIG. 4, item 123).
Regarding claim 5. Lee et al further discloses wherein the first side spacer (FIG. 4, item 123) includes silicon oxide ([0074]), and wherein each of the second side spacer (FIG. 4, item 125) and the base spacer (FIG. 4, item 121) includes silicon nitride ([0074]).
Regarding claim 8. Lee et al further discloses wherein the landing pad (FIG. 4, item 111 and LP) includes:
a tail (FIG. 4, tail of item 111) on the buried contact (FIG. 4, item XP);
a neck (annotated FIG. 4, item a neck of item ) having a width narrower than (FIG. 4, shows a neck has a width narrower than item tail, in the D1 direction) the tail (FIG. 2, item tail), on the tail (FIG. 2, item tail); and
a head (FIG. 4, item LP) having a width greater than (FIG. 4, shows item LP has a width greater than the item neck , in the D1 direction) the neck (annotated FIG. 4, item a neck), on the neck (annotated FIG. 4, item a neck).
PNG
media_image2.png
757
672
media_image2.png
Greyscale
Regarding claim 9. Lee et al further discloses wherein a part of the head is in the spacer recess (annotated FIG. 4 shows a part of the head is in the spacer recess).
Regarding claim 10. Lee et al further discloses further comprising: a direct contact (FIG. 4, item DCC) that electrically connects ([0061] an active region (FIG. 4, item ACT) of the substrate (FIG. 4, item 100) and the first conductive line (FIG. 4, item BL, FIG. 1, item BL);
a second conductive line (FIG. 1, item WL) that extends in a direction (FIG. 1, item D1) intersecting the first conductive line (FIG. 1, item BL), and crosses the active region (FIG. 1, item ACT) between the direct contact (FIG. 1, item DC) and the buried contact (FIG. 1, item BC); and a capacitor structure (FIG. 5, item DSP) electrically connected ([0092]) to the landing pad (FIG. 1, item LP).
Regarding claim 11. Lee et al discloses a semiconductor memory device (FIG. 4) comprising:
a substrate (FIG. 4, item 100);
a first conductive line (FIG. 4, item BL) on the substrate (FIG. 4, item 100);
a capping pattern (FIG. 4, item 137) that extends along an upper surface of the first conductive line (FIG. 4, item BL);
a spacer structure (FIG. 4, item SP) that includes a first side spacer (FIG. 4, item 125) and a second side spacer (FIG. 4, item 121) that are stacked sequentially on a side surface ([0074]) of the first conductive line (FIG. 4, item BL) and a side surface of the capping pattern (FIG. 4, item 137), the first side spacer (FIG. 4, item 125) and the second side spacer (FIG. 4, item 121) including different materials ([0074]) from each other ([0074]);
a buried contact (FIG. 4, item XP) electrically connected (FIG. 3, item 103B) to the substrate (FIG. 4, item 100) on a side surface ([0077]) of the spacer structure (FIG. 4, item SP);
a first barrier conductive film (FIG. 4, item 113) extending along the buried contact (FIG. 4, item XP) and the spacer structure (FIG. 4, item SP); and
a landing pad (FIG. 4, item LP and 111) electrically connected buried contact (FIG. 4, item XP), on the first barrier conductive film (FIG. 4, item 113) and the capping pattern (FIG. 4, item 137),
wherein an upper part of the spacer structure (FIG. 4, item SP) includes a spacer recess (annotated FIG. 4, item spacer recess) having an upper part (FIG. 4, item 111_US) that is equal (annotated FIG. 4 shows spacer recess upper part equal to an uppermost surface of item 137) to the uppermost surface (FIG. 4, item 137_US)of the capping pattern (FIG. 4, item 137),
PNG
media_image1.png
766
682
media_image1.png
Greyscale
wherein the first barrier conductive film FIG. 4, item 113) extends along the spacer recess and is in contact ([0076]-[0077]) with an upper part of the first side spacer (FIG. 4, item 125) and an upper part of the second side spacer (FIG. 4, item 121), and
wherein the landing pad (FIG. 4, item LP and 111) includes: a lower pad (FIG. 4, item 111) on the side surface of the capping pattern (FIG. 4, item 137) and the side surface of the spacer structure (FIG. 4, item SP); and an upper pad (FIG. 4, item LP) having a bottommost surface (FIG. 4, item 111_US) that is in contact ([0087]-[0089]) with an uppermost surface (FIG. 4, item 111_US) of the barrier conductive film (FIG. 4, item 113) and an uppermost surface (FIG. 4, item 137_US) of the capping pattern (FIG. 4, item 137), on the lower pad (FIG. 4, item 111).
Regarding claim 12. Lee et al discloses wherein an uppermost surface (FIG.4, item 111_US) of the lower pad (FIG.4, item 111), the uppermost surface (FIG.4, item 111_US) of the first barrier conductive film (FIG. 4, item 113), and the uppermost surface (FIG.4, item 137_US) of the capping pattern (FIG. 4, item 137) are coplanar ([0087])
Regarding claim 13. Lee et al further discloses wherein the lower pad (FIG. 1, item 111) is narrower (FIG 4 shows the top of item 111 is narrower than the bottom of item LP) than the upper pad (FIG. 4, item LP).
Regarding claim 14. Lee et a further discloses wherein the lower pad is thicker than the upper pad (FIG. 4 shows the lower pad is thicker than the upper pad in the D4 direction).
Regarding claim 15. Park et al further discloses wherein the lower pad (FIG. 4, item 111) and the upper pad (FIG. 4, item LP) include the same material as each other ([0100]).
Regarding claim 20. Lee et al discloses a semiconductor memory device comprising:
a substrate (FIG. 4, item 100) including an active region (FIG. 4, item 103);
a bit line (FIG. 1 and 4, item BL) extending ([0037]) in a first direction (FIG. 1, item D2) on the substrate (FIG. 4, item 100);
a direct contact (FIG. 4, item DCC) that electrically connects ([0039]) the active region (FIG. 4, item 103A) and the bit line (FIG. 4, item BL);
a first capping pattern (FIG. 4, item 137) that extends along an upper surface of the bit line (FIG. 4, item BL);
a spacer structure (FIG. 4, item SP) that extends along a side surface of the bit line (FIG. 4, item BL) and a side surface of the first capping pattern (FIG. 4, item 137);
a buried contact (FIG. 4, item XP) electrically connected to the active region (FIG. 4, item 103), on a side surface of the spacer structure (FIG. 4, item SP);
a barrier conductive film (FIG. 4, item 113) extending along the buried contact (FIG. 4, item XP) and the spacer structure (FIG. 4, item SP);
a landing pad (FIG. 4, item LP and 111) electrically connected (FIG. 4, item 113) to the buried contact (FIG. 4, item XP), on the barrier conductive film (FIG. 4, item 113) and the first capping pattern (FIG. 4, item 137);
wherein the landing pad (FIG. 4, item LP and 111) includes: a lower pad (FIG. 4, item 111) on the side surface of the capping pattern (FIG. 4, item 137) and the side surface of the spacer structure (FIG. 4, item SP); and an upper pad (FIG. 4, item LP) having a bottommost surface (FIG. 4, item 111_US) that is in contact ([0087]-[0089]) with an uppermost surface (FIG. 4, item 111_US) of the barrier conductive film (FIG. 4, item 113) and an uppermost surface (FIG. 4, item 137_US) of the capping pattern (FIG. 4, item 137), on the lower pad (FIG. 4, item 111),
a capacitor structure (FIG. 5, item DSP; [0092]-[0093]) that is electrically connected ([0092]-[0093]) to the landing pad (FIG. 4, item LP), on the landing pad (FIG. 4, item LP); and
a word line (FIG. 1, item WL; FIG. 5, item WL) that extends in a second direction (FIG. 1, item D1) intersecting the first direction (FIG. 1, item D2), and crosses the active region (FIG. 1, item ACT) between the direct contact (FIG. 1, item DCC; FIG. 4, item 134) and the buried contact ((FIG. 1, item BC; FIG. 4, item 170),
wherein an upper part of the spacer structure (FIG. 4, item SP) includes a curved region (annotated FIG. 4, item spacer recess) that is equal (annotated FIG. 4 shows spacer recess upper part equal to an uppermost surface of item 137) to the uppermost surface (FIG. 4, item 137_US)of the first capping pattern (FIG. 4, item 137),
wherein the barrier conductive film (FIG. 4, item 113) extends along the curved region (annotated FIG. 4, item spacer recess) and does not cover ([0087]) the upper most surface (FIG. 4, item 137_US) of the capping pattern (FIG. 4, item 137)
PNG
media_image1.png
766
682
media_image1.png
Greyscale
Regarding claim 21. Lee et al discloses all the limitations of the semiconductor memory device of claim 20 above.
Lee et al further discloses wherein the substrate (FIG. 5, item 100) includes a gate trench (FIG. 1 and 5, item WL_TR) extending in the second direction (FIG. 1, item D1), and wherein the word line (FIG. 1 and 5, item WL) is inside the gate trench (FIG. 1 and 5, item WL_TR).
Regarding claim 22. Lee et al discloses all the limitations of the semiconductor memory device of claim 21 above.
Lee et al further discloses further comprising: a second capping pattern (FIG. 5, item 110) extending along an upper surface of the word line (FIG. 5, item WL), inside the gate trench (FIG. 5, item WL_TR).
Allowable Subject Matter
Claims 17 and 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 8-15, 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.E.B./ Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
Prosecution Insights