DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/27/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There is no mention in the spec as to the widths of the third gate layer and the isolation layer and how they are related so the use of the term "substantially
The term “substantially” in claim 1 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. There is no mention in the spec as to the widths of the third gate layer and the isolation layer and how they are related so the use of the term "substantially" is indefinite.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Claims 1, 13, 40- 41 and 43 are rejected under U.S.C. 103 as being unpatentable over Loy et al.; US 2022/0223609 A1; 01/2021 in view of Thomson et al.; US 2023/0087444 A1; 09/2021 and Huang et al.; US 2023/0066323 A1; 08/2021
Claim 1: Loy discloses a semiconductor device ( Fig. 1A #100 ), comprising: a substrate ( Fig. 1B #102) ; a first cell ( Fig. 1D #228 ), comprising: a first diffusion region in the substrate ( Fig. 1A #108a) ; a first gate structure ( Fig. 1A #120a ) over the first diffusion region ( Fig. 1A #108a ); a first contact over the first diffusion region and on one side of the first gate structure ( Fig. 1D: source line SL1 ) in the first row #130 may contact the first diffusion structure #108a and the second diffusion structure #108b) ; and a third diffusion region ( Fig. 1A #110a) in the substrate ( Fig. 1B #102) and separated from the first diffusion region ( Fig. 1A #108a ) ; and a second cell ( Fig. 1D second cell shown above) adjacent to the first cell ( Fig. 1D #228 ), the second cell comprising: a second diffusion region ( Fig. 1A #108b) in the substrate ( Fig. 1B #102 ), wherein the second diffusion region ( Fig. 1A #108b) and the first diffusion region ( Fig. 1A #108a) form a continuous diffusion region ( both regions are continuous as shown in Fig. 1A) ; a second gate structure over the second diffusion region ( Fig. 1A #120b) ; a second contact over the second diffusion region and on one side of the second gate structure ( Fig. 1D: source line SL2 ) ; and a fourth diffusion region ( Fig. 1A #110b) in the substrate ( Fig. 1B #102 ) and separated from the second diffusion region ( Fig. 1A #108b), wherein the second contact is adjacent to the first contact of the first cell ( as shown in Fig. 1D ), wherein the first contact ( Fig. 1D: SL1 ) and the second contact ( Fig. 1D: SL2 ) are equipotential when the semiconductor device is in operation ( [0056] to operate the second bit in the memory cell #228, the operating voltage may be supplied through the first word line WL1 to the gate structure #216a with source line SL3 as the ground terminal and the other source lines SL1, SL2, SL4, SL5, Sl6, SL7, SL8 may provide the inhibiting voltages);
Loy does not appear to disclose a third gate structure between the first contact and the second contact; wherein the third diffusion region is separated from the fourth diffusion region by an isolation layer abutting the third gate structure in a top view, wherein a width of the third gate structure and a width of the isolation layer are substantially the same.
Thomson discloses a third gate structure ( Fig. 4a gate or dielectric structure #108 is shown ) between the first contact and the second contact ( as shown in Fig. 4a between two #109 contacts ) ; wherein the third diffusion region ( middle section Fig. 4a #107a and #107b surrounding the gate ) is separated from the fourth diffusion region ( Fig. 4a: gate section to the right of the middle ) by an isolation layer ( [0037] Spacers 102 extend along the sides of diffusion regions 103b and 107b and isolates those diffusion regions from semiconductor layers 101b (or structure 108, as the case may be ) abutting the third gate structure in a top view ( as shown in Fig. 4a ).
Thomson does not appear to disclose a width of the third gate structure and a width of the isolation layer are substantially the same.
However, Huang teaches a width of the third gate structure ( Fig. 1C: gate structure 160 ) and a width of the isolation layer ( Fig. 1C: isolation layer 151 ) are substantially the same ( as shown in the figure).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Huang with Loy and Thomson to implement a third gate structure between the first contact and the second contact; wherein the third diffusion region is separated from the fourth diffusion region by an isolation layer abutting the third gate structure in a top view, a width of the third gate structure and a width of the isolation layer are substantially the same because it enhances electrical control, reduces off-state leakage and isolates adjacent active areas to minimize parasitic capacitance and the widths ensure consistent device performance.
Claim 13: Loy, Thomson, and Huang disclose the semiconductor device as claimed in claim 1 (as discussed above).
Neither Loy nor Huang appear to disclose the third gate structure is formed over the continuous diffusion region and extends parallel to the first gate structure and the second gate structure.
However, Thomson teaches the third gate structure (Fig. 4a gate or dielectric structure #108 is shown) is formed over the continuous diffusion region (as discussed above) and extends parallel to the first gate structure ( Fig. 4a all gate structures are shown in parallel) and the second gate structure (Fig. 4a all gate structures are shown in parallel).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Thomson with Loy and Huang to implement another gate structure is formed over the continuous diffusion region and extends parallel to the first gate structure and the second gate structure because this allows for enhanced gate control enabling better suppression of undesirable short-channel effect.
Claim 40: Loy, Thomson, and Huang disclose the semiconductor device as claimed in claim 1 ( as discussed above).
Loy teaches the isolation layer ( Fig. 1B #104 ) extends along a longitudinal axis of the first gate structure ( as shown in Fig. 1B ).
Claim 43: Loy, Thomson, and Huang disclose the semiconductor device as claimed in claim 1 ( as discussed above ).
Loy teaches the continuous diffusion ( both regions are continuous as shown in Fig. 1A ) comprises the second diffusion region ( Fig. 1A #108b ) and the first diffusion region ( Fig. 1A #108a ).
Claims 2, 4 – 6 are rejected under U.S.C. 103 as being unpatentable over Loy et al.; US 2022/0223609 A1; 01/2021, Thomson et al.; US 2023/0087444 A1; 09/2021, and Huang et al.; US 2023/0066323 A1; 08/2021 as it applies to claim 1 and further in view of Jain et al.; US 9337099 B1; 01/2015
Claim 2: Loy, Thomson, and Huang disclose the semiconductor device (Fig. 3A #301A) as claimed in claim 1 (as discussed above).
Neither Loy nor Thomson nor Huang appear to disclose a first conductive rail, adjacent to the first diffusion region and the second diffusion region, wherein the first contact of the first cell and the second contact of the second cell are electrically connected to the first conductive rail.
However, Jain teaches a first conductive rail ( Fig. 3A source voltage #113 and #115), adjacent to the first diffusion region (Fig. 3A #113 is adjacent to #309) and the second diffusion region (Fig. 3A #115 is adjacent to #307), wherein the first contact ( Col 6. 59 – 63 a first gate contact #313 across the first dummy gate #123 that connects structure #111 from the first cell #303 with structure #111 from the second cell, which in turn are connected to power line #113) of the first cell (Fig. 3A #303) and the second contact (Col. 6 lines 63 – 66 A second gate contact #315 crosses the first dummy gate #123 and connects other structures #111 from the first and second cells, respectively, which in turn are connected to power line #115 in the M1 layer. ) of the second cell (Fig. 3A #305) are electrically connected to the first conductive rail (Fig. 3A source voltage #113 and #115).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Jain with Loy, Thomson, and Huang to implement a first conductive rail, adjacent to the first diffusion region and the second diffusion region, wherein the first contact of the first cell and the second contact of the second cell are electrically connected to the first conductive rail because placing the conductive rail directly adjacent to the diffusion regions reduces parasitic effects.
Claim 4: Loy, Thomson, Huang, and Jain disclose the semiconductor device as claimed in claim 2 (as discussed above).
Neither Loy nor Thomson nor Huang appear to disclose the first cell comprises a first source contact and a first drain contact at opposite sides of the first gate structure, wherein the first source contact is electrically connected to the first conductive rail.
However, Jain teaches the first cell (Fig. 3A #303) comprises a first source contact ( Fig. 3A #111 ) and a first drain contact ( Fig. 3A #119) at opposite sides of the first gate structure ( Fig. 3A #313 ), wherein the first source contact (Fig. 3A #111) is electrically connected to the first conductive rail (Fig. 3A #113 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Jain with Loy, Thomson, and Huang to implement the first cell comprises a first source contact and a first drain contact at opposite sides of the first gate structure, wherein the first source contact is electrically connected to the first conductive rail because if the source is connected to a conductive power rail this provides a stable voltage reference for the transistor.
Claim 5: Loy, Thomson, Huang, and Jain disclose the semiconductor device as claimed in claim 2 (as discussed above).
Neither Loy nor Thomson nor Huang appear to disclose the second cell comprises a second source contact and a second drain contact at opposite sides of the second gate structure, wherein the second source contact is electrically connected to the first conductive rail.
However, Jain teaches the second cell (Fig. 3A #305) comprises a second source contact ( Fig. 3A #111 ) and a second drain contact (Fig. 3A #119) at opposite sides of the second gate structure ( Fig. 3A #315), wherein the second source contact (Fig. 3A #111) is electrically connected to the first conductive rail (Fig. 3A #113).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Jain with Loy, Thomson, and Huang to implement the second cell comprises a second source contact and a second drain contact at opposite sides of the second gate structure, wherein the second source contact is electrically connected to the first conductive rail because if the source is connected to a conductive power rail this provides a stable voltage reference for the transistor.
Claim 6: Loy, Thomson, and Huang disclose the semiconductor device as claimed in claim 1 (as discussed above).
Neither Loy nor Thomson nor Huang appear to disclose the first diffusion region of the first cell and the second diffusion region of the second cell have the same conductivity type.
However, Jain teaches the first diffusion region ((Fig. 3A #309 ) of the first cell (Fig. 3A #303) and the second diffusion region (Fig. 3A #307) of the second cell (Fig. 3A #305) have the same conductivity type ( Col. 6 lines 42 - 44 the first cell #303 and second cell #305 are abutted together to form a continuous drain diffusion region #307 having an upper portion and a lower portion).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Jain with Loy, Thomson, and Huang to implement the first diffusion region of the first cell and the second diffusion region of the second cell have the same conductivity type because this allows them to be electrically connected together.
Claim 7 – 11 are rejected under U.S.C. 103 as being unpatentable over Loy et al.; US 2022/0223609 A1; 01/2021, Thomson et al.; US 2023/0087444 A1; 09/2021, and Huang et al.; US 2023/0066323 A1; 08/2021 as it applies to claim 1 and further in view of Disney et al.; US 8089129 B2; 02/2008
Claim 7: Loy, Thomson, and Huang discloses the semiconductor device as claimed in claim 1 wherein the first cell comprises (as discussed above).
Neither Loy nor Thomson nor Huang appear to disclose a third contact over the third diffusion region, wherein a conductivity type of the third diffusion region is the opposite of a conductivity type of the first diffusion region.
However, Disney teaches a third contact ( Fig. 1A #109B ) over the third diffusion region ( Fig. 1A NMOS 100C ), wherein a conductivity type ( Fig. 1A P-well 105 ) of the third diffusion region (Fig. 1A NMOS100C) is the opposite of a conductivity type ( Fig. 1A N-well 104 ) of the first diffusion region ( Fig. 1A PMOS 100A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Disney with Loy, Thomson, and Huang to implement a third contact over the third diffusion region, where in a conductivity type of the third diffusion region is the opposite of a conductivity type of the first diffusion region because this can improve substrate noise reduction.
Claim 8: Loy, Thomson, Huang, and Disney disclose the semiconductor device as claimed in claim 7 (as discussed above).
Neither Loy nor Thomson nor Huang appear to disclose the first gate structure extends across the third diffusion region of the first cell, and the third contact is disposed on one side of the first gate structure.
However, Disney teaches the first gate structure (Col. 6 line 67 – Col. 7 line 1 a gate 109A located atop a first gate oxide layer 115A ) extends across the third diffusion region (Fig. 1A NMOS100C) of the first cell ( Fig. 1A #104 ), and the third contact (Fig. 1A #109B) is disposed on one side of the first gate structure ( Fig. 1A #109B is on the right side of Fig. 1A #109A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Disney with Loy, Thomson, and Huang to implement the first gate structure extends across the third diffusion region of the first cell, and the third contact is disposed on one side of the first gate structure because this can improve drive strength and reduce parasitic resistance.
Claim 9: Loy, Thomson, Huang, and Disney disclose the semiconductor device as claimed in claim 7, wherein the second cell further comprises (as discussed above).
Neither Loy nor Thomson nor Huang appear to disclose a fourth contact over the fourth diffusion region, wherein a conductivity type of the fourth diffusion region is the opposite of a conductivity type of the second diffusion region, and wherein the fourth contact of the second cell and the third contact of the first cell are non- equipotential when the semiconductor device is in operation.
However, Disney teaches a fourth contact (Fig. 5 #406C) over the fourth diffusion region (Fig. 5 #405B), wherein a conductivity type of the fourth diffusion region (Fig. 5 #406C N+ type ) is the opposite of a conductivity type of the second diffusion region (Fig. 5 #407A P+ type), and wherein the fourth contact ( Fig. 5 #406C) of the second cell and the third contact ( Fig. 5 #406B) of the first cell are non-equipotential ( Col. 8 lines 32 – 36 Any number of CMOS devices can be integrated by introducing trenches similar to trenches 103A-103D between and amongst them, with its own dedicated floor isolation region electrically biased to a different potential ) when the semiconductor device is in operation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Disney with Loy, Thomson, and Huang to implement a fourth contact over the fourth diffusion region, wherein a conductivity type of the fourth diffusion region is the opposite of a conductivity type of the second diffusion region, and wherein the fourth contact of the second cell and the third contact of the first cell are non- equipotential when the semiconductor device is in operation because this allows for control over device characteristics like threshold voltage.
Claim 11: Loy, Thomson, Huang, and Disney disclose the semiconductor device as claimed in claim 9 (as discussed above).
Neither Loy nor Huang nor Disney appear to disclose a second conductive rail, adjacent to the third diffusion region and the fourth diffusion region, wherein the third contact or the fourth contact is electrically connected to the second conductive rail, and the other of the third contact or the fourth contact is electrically isolated from the second conductive rail.
However, Thomson teaches a second conductive rail ( Fig. 4a interconnect #115), adjacent to the third diffusion region (Fig. 4a #107a ) and the fourth diffusion region (Fig. 4a #107b) , wherein the third contact (Fig. 4a #113b) or the fourth contact (Fig. 4a #113a) is electrically connected to the second conductive rail (Fig. 4a #115), and the other of the third contact ( Fig. 4a #113b ) or the fourth contact ( Fig. 4a #113a ) is electrically isolated (Fig. 4a gate spacer #102 ) from the second conductive rail (Fig. 4a #115).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Thomson with Disney, Loy, and Huang to implement a second conductive rail, adjacent to the third diffusion region and the fourth diffusion region, wherein the third contact or the fourth contact is electrically connected to the second conductive rail, and the other of the third contact or the fourth contact is electrically isolated from the second conductive rail because this reduces resistance and improves conductivity.
Claim 41 is rejected under U.S.C. 103 as being unpatentable over Loy et al.; US 2022/0223609 A1; 01/2021, Thomson et al.; US 2023/0087444 A1; 09/2021, and Huang et al.; US 2023/0066323 A1; 08/2021 as it applies to claim 1 and further in view of Hsueh et al.; US 2021/0287994 A1; 03/2020
Claim 41: Loy, Thomson, and Huang disclose the semiconductor device as claimed in claim 1 ( as discussed above ).
Neither Loy nor Thomson nor Huang appear to disclose a first sidewall of the first diffusion extends to a first sidewall of the second diffusion in a first direction, and a second sidewall of the first diffusion extends to a second sidewall of the second diffusion in the first direction.
However, Hsueh teaches a first sidewall of the first diffusion ( Fig. 14 first diffusion barrier layer 118 left side of figure right side of layer ) extends to a first sidewall of the second diffusion ( Fig. 14 second diffusion barrier layer 310 left side of figure left side of layer ) in a first direction ( as shown in Fig. 14 ), and a second sidewall of the first diffusion ( Fig. 14 #118 right side of figure left side of layer) extends to a second sidewall of the second diffusion ( Fig. 14 #310 right side of figure right side of layer ) in the first direction ( as shown in Fig. 14 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hsueh with Loy, Thomson, and Huang to implement a first sidewall of the first diffusion extends to a first sidewall of the second diffusion in a first direction, and a second sidewall of the first diffusion extends to a second sidewall of the second diffusion in the first direction because this approach enforces geometric symmetry, controls stress and isolation effects.
Claim 42 is rejected under U.S.C. 103 as being unpatentable over Loy et al.; US 2022/0223609 A1; 01/2021, Thomson et al.; US 2023/0087444 A1; 09/2021, and Huang et al.; US 2023/0066323 A1; 08/2021 as it applies to claim 1 and further in view of Kim et al.; US 2022/0173112 A1; 08/2021
Claim 42: Loy, Thomson, and Huang disclose the semiconductor device as claimed in claim 1 ( as discussed above ).
Neither Loy nor Thomson nor Huang appear to disclose a central axis of the third gate structure overlaps with a central axis of the isolation layer.
However, Kim teaches a central axis of the third gate structure ( Fig. 8B third gate insulating pattern 420 ) overlaps ( [0142] At least a part of the third gate insulating pattern 420 may overlap the second core element isolation layer 410 in the fourth direction D4 ) with a central axis of the isolation layer ( Fig. 8B second core element isolation layer 410 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kim with Loy, Thomson, and Huang to implement a central axis of the third gate structure overlaps with a central axis of the isolation layer because this design choice reduces parasitic currents and improves device reliability.
Response to Amendment
The amendment filed 05/18/2026 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: Applicant argues that support for the amendments to claim 1 and 41 are shown in Fig. 4. With regard to the amendment to claim 1, “wherein a width of the third gate structure and a width of the isolation layer are substantially the same.” A gate structure 310 is shown in Fig. 4 but no specific mention of width is made. Additionally, as stated in paragraph [0016] of the specification it is stated "In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale." For the isolation layer, the third part 2031 of the third diffusion region 203 and the fourth part 2041 of the fourth diffusion region 204 are removed (e.g. by forming a trench, and the trench is then filled with one or more dielectric materials to form 28 an isolation layer). No mention of the width of the isolation layer is provided in Fig. 4. With regard to the amendment to claim 41, “sidewalls” are not specifically mentioned with regard to Fig. 4 or mentioned anywhere in the Specification.
Applicant is required to cancel the new matter in the reply to this Office Action.
The amendment filed 05/18/2026 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: Claim 42 states "a central axis of the third gate structure overlaps with a central axis of the isolation layer." However, no mention is made in the specification of a central axis in either the third gate structure or the isolation layer.
Applicant is required to cancel the new matter in the reply to this Office Action.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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