DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lilak et al (US Publication No. 2021/0296315).
Regarding claim 1, Lilak discloses an integrated circuit comprising: a first semiconductor device having first and second semiconductor bodies each extending between a first source region and a first drain region Fig 1A-1B ¶0036-0037, and a first gate dielectric Fig 1B, 108 wrapped around each of the first and second semiconductor bodies Fig 1B ¶0037; a second semiconductor device having third and fourth semiconductor bodies each extending between a second source region and a second drain region Fig 1A-1B ¶0036-0037, and a second gate dielectric wrapped around each of the third and fourth semiconductor bodies Fig 1A-1B; and a dielectric spine Fig 1B, 110 between the first semiconductor device and the second semiconductor device, such that the dielectric spine contacts both the first and second semiconductor bodies Fig 1B and both the third and fourth semiconductor bodies Fig 1B; wherein the first gate dielectric is not on a portion of a first sidewall of the dielectric spine Fig 1B between the first and second semiconductor bodies Fig 1B, and wherein the second gate dielectric is not on a portion of a second sidewall of the dielectric spine between the third and fourth semiconductor bodies Fig 1B ¶0037.
Regarding claim 2, Lilak discloses wherein the first semiconductor device comprises a first gate electrode on the first gate dielectric and the second semiconductor device comprises a second gate electrode on the second gate dielectric ¶0037.
Regarding claim 5, Lilak discloses wherein the dielectric spine further extends between the first drain region and the second drain region, and between the first source region and the second source region Fig 1A-1B ¶0036-0037.
Regarding claim 6, Lilak discloses wherein the first drain region and the second drain region each contact respective sidewalls of the dielectric spine along an entire height of the first drain region and the second drain region, and wherein the first source region and the second source region each contact respective sidewalls of the dielectric spine along an entire height of the first source region and the second source region Fig 1A-1B ¶0036-0037.
Regarding claim 7, Lilak discloses a printed circuit board comprising the integrated circuit of claim 1 Fig 21.
Regarding claim 8, Lilak discloses an integrated circuit comprising: a spine Fig 1A, 110 comprising dielectric material ¶0005 and 0057; a first set of two or more semiconductor bodies each laterally extending from a first side of the spine Fig 1A-1B; a second set of two or more semiconductor bodies each laterally extending from a second side of the spine Fig 1A-1B, 2A-2C; a first gate structure on the two or more semiconductor bodies of the first set Fig 1A-1B, 2A-2C, the first gate structure including a first gate electrode and a first gate dielectric Fig 1A-1B, 108 and Fig 2A-2C, 208, the first gate dielectric between the two or more semiconductor bodies of the first set and the first gate electrode Fig 1A-1B, 2A-2C, and the first gate electrode directly on the first side of the spine between adjacent semiconductor bodies of the first set Fig 1A-1B, 2A-2C; and a second gate structure on the two or more semiconductor bodies of the second set Fig 1A-1B, 2A-2C, the second gate structure including a second gate electrode and a second gate dielectric Fig 1A-1B, 108 and Fig 2A-2C, 208, the second gate dielectric between the two or more semiconductor bodies of the second set and the second gate electrode Fig 1A-1B, 108 and Fig 2A-2C, 208, and the second gate electrode directly on the second side of the spine between adjacent semiconductor bodies of the second set Fig 1A-1B, 108 and Fig 2A-2C, 208.
Regarding claim 9, Lilak discloses wherein the first set of one or more semiconductor bodies and the first gate structure are part of a p-type metal oxide semiconductor (PMOS) transistor structure, and the second set of one or more semiconductor bodies and the second gate structure are part of an n-type metal oxide semiconductor (NMOS) transistor structure ¶0044.
Regarding claim 10, Lilak discloses wherein the PMOS transistor structure and the NMOS transistor structure are part of a forksheet device ¶0044.
Regarding claim 11, Lilak discloses a first source region and a first drain region, each in contact with the first set of two or more semiconductor bodies, such that the first set of two or more semiconductor bodies is between the first source region and the first drain region; and a second source region and a second drain region, each in contact with the second set of two or more semiconductor bodies, such that the second set of two or more semiconductor bodies is between the second source region and the second drain region¶0036-0037.
Regarding claim 12, Lilak discloses wherein the spine includes at least two different material layers ¶0091-0092, 0101.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over
Lilak et al (US Publication No. 2021/0296315) in view of Frougier et al (US Publication No. 2023/0066979).
Regarding claim 3, Lilak discloses all the limitations but silent on the gate cut. Whereas Frougier discloses a gate cut Fig 2, 122 through a portion of the first gate electrode or a portion of the second gate electrode Fig 2 and Fig 4, the gate cut comprising a dielectric material that is the same as the dielectric material of the dielectric spine ¶0003, 0042, 0051, 0062. Lilak and Frougier are analogous art because they are directed to semiconductor devices having forksheet transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lilak because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Lilak and incorporate the teachings of Frougier to reduce parasitic capacitance and improves performance.
Regarding claim 4, Lilak discloses wherein the first gate electrode is on the portion of the first sidewall of the dielectric spine between the first and second semiconductor bodies where there is no first gate dielectric, and wherein the second gate electrode is on the portion of the second sidewall of the dielectric spine between the third and fourth semiconductor bodies where there is no second gate dielectric Fig 1A-1B,2A-2C.
Claims 13-14, 16, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al (US Publication No. 2021/0296315) in view of Hirose (US Publication No. 2022/0310631).
Regarding claim 13, Lilak discloses an integrated circuit comprising: a first semiconductor device having a first plurality of semiconductor nanoribbons extending in a first direction between a first source region and a first drain region ¶0036-0037 Fig 1A-1B,2A-2C; a second semiconductor device having a second plurality of semiconductor nanoribbons extending in the first direction between a second source region and a second drain region¶0036-0037 Fig 1A-1B,2A-2C; and a dielectric spine Fig 1A-1B,2A-2C, 110 between the first plurality of semiconductor nanoribbons and the second plurality of semiconductor nanoribbons Fig 1A-1B,2A-2C, such that the dielectric spine contacts both the first plurality of semiconductor nanoribbons and the second plurality of semiconductor nanoribbons Fig 1A-1B,2A-2C. Lilak discloses all the limitations but silent on the width. Whereas Hirose discloses wherein a width of the first plurality of semiconductor nanoribbons in a second direction differs from a width of the second plurality of semiconductor nanoribbons in the second direction by at least 10%, the second direction being substantially orthogonal to the first direction ¶0060, 0086. Lilak and Hirose are analogous art because they are directed to semiconductor devices having forksheet transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lilak because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Lilak and incorporate the teachings of Hirose to achieve reduction in device area.
Regarding claim 14, Lilak discloses wherein the first plurality of semiconductor nanoribbons and the second plurality of semiconductor nanoribbons comprise germanium, silicon, or both ¶0045.
Regarding claim 16, Lilak discloses wherein the dielectric spine comprises a first layer of dielectric material that contacts both the first plurality of semiconductor nanoribbons and the second plurality of semiconductor nanoribbons, and a second layer of dielectric material on the first layer of dielectric material Fig 10J.
Regarding claim 18, Lilak discloses wherein the dielectric spine further extends between the first drain region and the second drain region, and between the first source region and the second source region¶0036-0037 Fig 1A-1B,2A-2C.
Regarding claim 19, Lilak discloses wherein the first drain region and the second drain region each contact respective sidewalls of the dielectric spine along an entire height of the first drain region and the second drain region, and wherein the first source region and the second source region each contact respective sidewalls of the dielectric spine along an entire height of the first source region and the second source region¶0036-0037 Fig 1A-1B,2A-2C.
Regarding claim 20, Lilak discloses a printed circuit board comprising the integrated circuit of claim 13 Fig 21.
Claims 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al (US Publication No. 2021/0296315) in view of Hirose (US Publication No. 2022/0310631) in view of Xie et al (US Publication No. 2023/0038116).
Regarding claim 15, Lilak discloses all the limitations but silent on the width. Whereas Xie discloses wherein the dielectric spine has a width extending between the first plurality of semiconductor nanoribbons and the second plurality of semiconductor nanoribbons of about 10 nm to about 20 nm ¶0054. Lilak and Xie are analogous art because they are directed to semiconductor devices having forksheet transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lilak because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Lilak and incorporate the teachings of Xie since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
Regarding claim 17, Xie discloses wherein the first layer of dielectric material comprises a high-k dielectric material and the second layer of dielectric material comprises a low-k dielectric material ¶0054 and 0079.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811