DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 6, 9-11, 13, 14, 16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over US PG Pub 2022/0310638 to Cheng et al (hereinafter Cheng) in view of US PG Pub 2022/0122975 to Ryu et al (hereinafter Ryu).
Regarding Claim 1, Cheng discloses an integrated circuit comprising:
a semiconductor region (310, Fig. 11) over a substrate and extending in a first direction from a first source or drain region (170) to a second source or drain region;
a gate structure (358) extending in a second direction over the semiconductor region;
a capacitor structure (188) having a first electrode (1050), a second electrode (1054), and a ferroelectric layer (1052) between the first and second electrodes; and
a conductive contact (190) over the capacitor structure.
Cheng does not disclose wherein the first electrode directly contacts the first source or drain region and the second electrode directly contacts the conductive contact.
Ryu discloses an integrated circuit which includes a semiconductor region (Fig. 2B, CH1/CH2) over a substrate and extending in a first direction from a first source or drain region (DR, Fig. 3A) to a second source or drain region wherein the first electrode of a capacitor (CAP) directly contacts the first source or drain region and the second electrode directly contacts the conductive contact (Fig. 3A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the capacitor of Cheng such that the first electrode of the capacitor was in direct contact with the source or drain region. Such a modification would have provided obvious benefits such as reducing the size of the circuit.
Regarding Claims 3 and 4, the combination of Cheng and Ryu makes obvious the integrated circuit of Claim 1. The references do not explicitly disclose a fin isolation structure adjacent to the capacitor structure. However, it would have been obvious to provide isolation structures adjacent to the capacitor so as to provide electrical isolation from neighboring, conductive elements and prevent parasitic capacitance.
Regarding Claim 6, the combination of Cheng and Ryu makes obvious the integrated circuit of Claim 1 but does not explicitly disclose a dielectric layer between the first electrode of the capacitor structure and a portion of the substrate beneath the first source or drain region.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the embodiment suggested by Cheng and Ryu such that a dielectric layer is between the first electrode of the capacitor structure and a portion of the substrate beneath the first source or drain region. It is common in the art for substrates to be made of semiconductive material. A dielectric layer would therefore have been obvious to prevent the capacitor from electrically interacting with a semiconductive substrate.
Regarding Claim 9, the combination of Cheng and Ryu makes obvious the integrated circuit of Claim 1, wherein the ferroelectric layer comprises oxygen and hafnium (Cheng [0050]).
Regarding Claim 10, the combination of Cheng and Ryu makes obvious a printed circuit board comprising the integrated circuit of Claim 1 since using transistors as part of a printed circuit board would have been obvious to provide signal switching for common semiconductive devices.
Regarding Claim 11, Cheng discloses an integrated circuit comprising:
a semiconductor region (310, Fig. 11) over a substrate and extending in a first direction from a first source or drain region (170) to a second source or drain region;
a gate structure (358) extending in a second direction over the semiconductor region;
a first conductive layer (1050) contacting a sidewall portion of the first source or drain region (see below);
a ferroelectric layer (1052) on the first conductive layer;
a second conductive layer (1054) on the ferroelectric layer; and
a conductive contact (190) on the second conductive layer.
Cheng does not disclose wherein the first electrode directly contacts the first source or drain region and the second electrode directly contacts the conductive contact.
Ryu discloses an integrated circuit which includes a semiconductor region (Fig. 2B, CH1/CH2) over a substrate and extending in a first direction from a first source or drain region (DR, Fig. 3A) to a second source or drain region wherein the first electrode of a capacitor (CAP) directly contacts the first source or drain region and the second electrode directly contacts the conductive contact (Fig. 3A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the capacitor of Cheng such that the first electrode of the capacitor was in direct contact with the source or drain region. Such a modification would have provided obvious benefits such as reducing the size of the circuit.
Regarding Claims 13 and 14, the combination of Cheng and Ryu makes obvious the integrated circuit of Claim 11. The references do not explicitly disclose a fin isolation structure adjacent to the capacitor structure. However, it would have been obvious to provide isolation structures adjacent to the capacitor so as to provide electrical isolation from neighboring, conductive elements and prevent parasitic capacitance.
Regarding Claim 16, the combination of Cheng and Ryu makes obvious the integrated circuit of Claim 11 but does not explicitly disclose a dielectric layer between the first electrode of the capacitor structure and a portion of the substrate beneath the first source or drain region.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the embodiment suggested by Cheng and Ryu such that a dielectric layer is between the first electrode of the capacitor structure and a portion of the substrate beneath the first source or drain region. It is common in the art for substrates to be made of semiconductive material. A dielectric layer would therefore have been obvious to prevent the capacitor from electrically interacting with a semiconductive substrate.
Regarding Claim 19, the combination of Cheng and Ryu makes obvious a printed circuit board comprising the integrated circuit of Claim 11 since using transistors as part of a printed circuit board would have been obvious to provide signal switching for common semiconductive devices.
Regarding Claim 20, Cheng discloses an integrated circuit comprising:
a semiconductor region (310, Fig. 11) over a substrate and extending in a first direction from a first source or drain region (170) to a second source or drain region;
a gate structure (358) extending in a second direction over the semiconductor region;
a conductive layer (1050) on a top surface of the first source or drain region;
a ferroelectric layer (1052) on the conductive layer; and
a conductive contact (1054) on the ferroelectric layer.
Cheng does not disclose wherein the conductive layer is on a top surface of the first source or drain region.
Ryu discloses an integrated circuit which includes a semiconductor region (Fig. 2B, CH1/CH2) over a substrate and extending in a first direction from a first source or drain region (DR, Fig. 3A) to a second source or drain region wherein the first electrode of a capacitor (CAP) directly contacts the first source or drain region and the second electrode directly contacts the conductive contact (Fig. 3A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the capacitor of Cheng such that the conductive layer is on a top surface of the first source or drain region. Such a modification would have provided obvious benefits such as reducing the size of the circuit.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Cheng and Ryu as applied to Claims 1 and 11 above, and further in view of US PG Pub 2023/0268392 to Sharma et al (hereinafter Sharma).
Regarding Claims 8 and 18, the combination of Cheng and Ryu makes obvious the integrated circuit of Claims 1 and 11 but do not explicitly disclose wherein the conductive contact is a multilayer structure and/or the first source or drain region is a multilayer structure.
Sharma disclose a source/drain contact where in the contact is a multilayer structure (Figs. 8A-8D and Figs. 9A-9D).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have formed the contact structure of Cheng to comprise a multilayered structure. Multilayered structures are commonly found in the art for contacts for numerous benefits such as increasing conductivity between metallization layers
Allowable Subject Matter
Claims 2, 5, 7, 12, 15 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 2, 5, 7, 12, 15 and 17 disclose embodiments that are not suggested by the references of record and are not apparent such as the capacitor extending into the substrate below the source or drain region or the ferroelectric layer directly contacting the fin isolation structure. It is not apparent that the embodiments suggested by the references would benefit from such modifications or function equally as well.
Conclusion
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893