DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 1/26/2026 has been entered.
Response to Arguments
Applicant's arguments with respect to claims 1-20 have been considered but are moot because the arguments do not apply to all of the references being used in the current rejection. Specifically, Applicant s arguments filed 1/26/2026 applied to the Cheng 776 reference used to reject at least claim 1 in the rejection under 35 USC 102(a)(1). In the current rejection, Applicant s amendment filed 1/26/2026 necessitated the incorporation of a secondary reference Chiang 150 to supplement the teachings of Cheng 776 by providing the specifically recited claimed the first gate cut extending partially into the dielectric fill; the second gate cut extending partially into the dielectric fill.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US 2022/0254776) in view of Chiang (US 2022/0352150).
Regarding claim 1, Cheng discloses, in at least figures 4, 11, 18, 32, 36, and related text, an integrated circuit (the limitation of "an integrated circuit" has not patentable weight because it is interpreted as intended use) comprising:
one or more semiconductor regions (2080 (208), [17], [35]) extending in a first direction (Y direction, figures) above a dielectric fill (216/2160, [22], [23]) and between corresponding source regions (left 238/240, [32], figures) and drain regions (right 238/240, [32], figures);
a gate structure (252/254/256, [36]) extending in a second direction (X direction, figures) over the one or more semiconductor regions (2080 (208), [17], [35]);
a first gate cut (2220, [25]) comprising a first dielectric material ([25]) and extending in a third direction (Z direction, figures) through an entire thickness of the gate structure (252/254/256, [36]); and
a second gate cut (222B, [47]) comprising a second dielectric material ([25], [47]) and extending in the third direction (Z direction, figures) through the entire thickness of the gate structure (252/254/256, [36]),
wherein a width (W2, [47]) at a top of the second gate cut (2220, [25]) is at least twice as large as a width (W1, [47]) at a top of the first gate cut (2220, [25]), and wherein the first gate cut (2220, [25]) and the second gate cut (2220, [25]) each has a height in the third direction (Z direction, figures) that differs by no more than 10 nm (difference D, [31], [32]).
Cheng does not explicitly disclose the first gate cut extending partially into the dielectric fill; the second gate cut extending partially into the dielectric fill.
Chiang teaches, in at least figures 2Z, 3E, and related text, the device comprising the first gate cut (186, [87]) extending partially into the dielectric fill (126, [39]); the second gate cut (178, [81]) extending partially into the dielectric fill (126, [39]), for the purpose of providing an integrated circuit with nanosheet transistors having improved performance ([16]).
Cheng and Chiang are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng with the specified features of Chiang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Cheng to have the first gate cut extending partially into the dielectric fill; the second gate cut extending partially into the dielectric fill, as taught by Chiang, for the purpose of providing an integrated circuit with nanosheet transistors having improved performance ([16], Chiang).
Regarding claim 2, Cheng in view of Chiang discloses the integrated circuit of claim 1 as described above.
Cheng further discloses, in at least figures 4, 11, 18, 32, 36, and related text, the gate structure (252/254/256, [36]) includes a gate dielectric (254, [36]) around the one or more semiconductor regions (2080 (208), [17], [35]).
Regarding claim 3, Cheng in view of Chiang discloses the integrated circuit of claim 2 as described above.
Cheng further discloses, in at least figures 4, 11, 18, 32, 36, and related text, the gate dielectric (254, [36]) is not present on any sidewall of the first gate cut (2220, [25]) and not present on any sidewall of the second gate cut (222B, [47]).
Regarding claim 5, Cheng in view of Chiang discloses the integrated circuit of claim 1 as described above.
Cheng further discloses, in at least figures 4, 11, 18, 32, 36, and related text, subfin regions (214AF/214BF, [20]) beneath each of the one or more semiconductor regions (2080 (208), [17], [35]) and a dielectric fill (216/2160, [22], [23]) between adjacent subfin regions (214AF/214BF, [20]).
Regarding claim 8, Cheng in view of Chiang discloses the integrated circuit of claim 1 as described above.
The claimed limitation of " A printed circuit board comprising the integrated circuit of claim 1" has not patentable weight because it is interpreted as intended use.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US 2022/0254776) in view of Chiang (US 2022/0352150), and further in view of Bayati (US 2024/0105800).
Regarding claim 4, Cheng in view of Chiang discloses the integrated circuit of claim 1 as described above.
Cheng in view of Chiang does not explicitly disclose the first gate cut and the second gate cut each has a height in the third direction, and their respective heights differ by no more than 4 nm.
Bayati teaches, in at least figure 3C and related text, the device comprising the first gate cut (311, [68]) and the second gate cut (313, [68]) each has a height in the third direction (vertical direction, figure), and their respective heights differ by no more than 4 nm (ΔH, [68]), for the purpose of providing gate cuts having a high length-to-width aspect ratio (e.g., 5:1 or higher) ([14]) thereby improving density of integration.
Cheng, Chiang, and Bayati are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng in view of Chiang with the specified features of Bayati because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Cheng in view of Chiang to have the first gate cut and the second gate cut each having a height in the third direction, and their respective heights differ by no more than 4 nm, as taught by Bayati, for the purpose of providing gate cuts having a high length-to-width aspect ratio (e.g., 5:1 or higher) ([14], Bayati) thereby improving density of integration.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US 2022/0254776) in view of Chiang (US 2022/0352150), and further in view of Bouche (US 2022/0157722).
Regarding claim 6, Cheng in view of Chiang discloses the integrated circuit of claim 1 as described above.
Cheng in view of Chiang does not explicitly disclose a conductive via that extends in the third direction through a height of the second gate cut.
Bouche teaches, in at least figure 4A and related text, the device comprising a conductive via (322, [76]) that extends in the third direction (vertical direction, figure) through a height of the second gate cut (312-2, [74]), for the purpose of providing improvements in terms of accuracy, cost-efficiency, and device performance, compared to conventional approaches to forming metal gate cuts ([30]).
Cheng, Chiang, and Bouche are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng in view of Chiang with the specified features of Bouche because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Cheng in view of Chiang to have the conductive via that extends in the third direction through a height of the second gate cut, as taught by Bouche, for the purpose of providing improvements in terms of accuracy, cost-efficiency, and device performance, compared to conventional approaches to forming metal gate cuts ([30], Bouche).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US 2022/0254776) in view of Chiang (US 2022/0352150), and further in view of Ching (US 2019/0067417).
Regarding claim 7, Cheng in view of Chiang discloses the integrated circuit of claim 1 as described above.
Cheng in view of Chiang does not explicitly disclose the first dielectric material has a different material composition than the second dielectric material.
Ching teaches, in at least figures 1A-1B and related text, the device comprising the first dielectric material (material of 108a, [19], [41]) has a different material composition than the second dielectric material (material of 108b, [19], [41]), for the purpose of providing dielectric fill fins along with device fins thereby improving uniformity of fin density and providing better structure fidelity ([16]).
Cheng, Chiang, and Ching are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng in view of Chiang with the specified features of Ching because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Cheng in view of Chiang to have the first dielectric material having a different material composition than the second dielectric material, as taught by Ching, for the purpose of providing dielectric fill fins along with device fins thereby improving uniformity of fin density and providing better structure fidelity ([16], Ching).
Claim(s) 9-11 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bayati (US 2024/0105800) in view of in view of Chiang (US 2022/0352150).
Regarding claim 9, Bayati discloses, in at least figures 1A-1B, 3C, 4, and related text, an electronic device (the limitation of "an electronic device" has not patentable weight because it is interpreted as intended use), comprising:
a chip package (400, [69]) comprising one or more dies (402, [69]), at least one of the one or more dies (402, [69]) comprising
one or more semiconductor regions (104, [29]) extending in a first direction (horizontal direction, figure 1B) between corresponding source regions (110a/112a, [31]) and drain regions (110b/112b, [31]);
a gate structure (118 (118a/116a/118b/116b), [33], [67]) extending in a second direction (horizontal direction, figures 1A, 3C) over the one or more semiconductor regions (104, [29]);
a first gate cut (311, [68]) extending in a third direction through an entire thickness of the gate structure (118 (118a/116a/118b/116b), [33], [67]); and
a second gate cut (313, [68]) extending in the third direction through the entire thickness of the gate structure (118 (118a/116a/118b/116b), [33], [67]),
wherein the first gate cut (311, [68]) and the second gate cut (313, [68]) each has a height in the third direction (vertical direction, figure 3C) that differs by no more than 5 nm (ΔH, [68]).
Bayati does not explicitly disclose one or more semiconductor regions above a dielectric fill; a first gate cut comprising a first dielectric material and extending in a third direction through an entire thickness of the gate structure; a second gate cut comprising a second dielectric material and extending in the third direction through the entire thickness of the gate structure; a width at a top of the second gate cut is at least 1.5x as large as a width at a top of the first gate cut.
Chiang teaches, in at least figures 2Z, 3E, and related text, the device comprising one or more semiconductor regions (167, [73]) above a dielectric fill (126, [39]); a first gate cut (186, [87]) comprising a first dielectric material ([87]) and extending in a third direction through an entire thickness of the gate structure (110/114/184, [91]); a second gate cut (178, [81]) comprising a second dielectric material ([81]) and extending in the third direction through the entire thickness of the gate structure (110/114/184, [91]); a width at a top of the second gate cut (178, [81]) is at least 1.5x as large as a width at a top of the first gate cut (186, [87]) (figure), for the purpose of providing an integrated circuit with nanosheet transistors having improved performance ([16]).
Bayati and Chiang are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Bayati with the specified features of Chiang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Bayati to have the one or more semiconductor regions above a dielectric fill; the first gate cut comprising a first dielectric material and extending in a third direction through an entire thickness of the gate structure; the second gate cut comprising a second dielectric material and extending in the third direction through the entire thickness of the gate structure; the width at a top of the second gate cut being at least 1.5x as large as a width at a top of the first gate cut, as taught by Chiang, for the purpose of providing an integrated circuit with nanosheet transistors having improved performance ([16], Chiang).
Regarding claim 10, Bayati in view of Chiang discloses the electronic device of claim 9 as described above.
Bayati further discloses, in at least figures 1A-1B, 3C, 4, and related text, the gate structure (118 (118a/116a/118b/116b), [33], [67]) includes a gate dielectric (116a/116b, [33]) around the one or more semiconductor regions (104, [29]).
Chiang further teaches, in at least figures 2Z, 3E, and related text, the gate dielectric (158, [81]) is not present on any sidewall of the first gate cut (186, [87]) and not present on any sidewall of the second gate cut (178, [81]), for the purpose of providing an integrated circuit with nanosheet transistors having improved performance ([16]).
Regarding claim 11, Bayati in view of Chiang discloses the electronic device of claim 9 as described above.
Bayati further discloses, in at least figures 1A-1B, 3C, 4, and related text, the first gate cut (311, [68]) and the second gate cut (313, [68]) each has a height in the third direction (vertical direction, figure 3C) that differs by no more than 2 nm (ΔH, [68]).
Regarding claim 14, Bayati in view of Chiang discloses the electronic device of claim 9 as described above.
Bayati further discloses, in at least figures 1A-1B, 3C, 4, and related text, a printed circuit board ([70]), wherein the chip package (400, [70]) is coupled to the printed circuit board ([70]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bayati (US 2024/0105800) in view of Chiang (US 2022/0352150), and further in view of Bouche (US 2022/0157722).
Regarding claim 12, Bayati in view of Chiang discloses the electronic device of claim 9 as described above.
Bayati in view of Chiang does not explicitly disclose a conductive via that extends in the third direction through a height of the second gate cut.
Bouche teaches, in at least figure 4A and related text, the device comprising a conductive via (322, [76]) that extends in the third direction (vertical direction, figure) through a height of the second gate cut (312-2, [74]), for the purpose of providing improvements in terms of accuracy, cost-efficiency, and device performance, compared to conventional approaches to forming metal gate cuts ([30]).
Bayati, Chiang, and Bouche are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Bayati in view of Chiang with the specified features of Bouche because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Bayati in view of Chiang to have the conductive via that extends in the third direction through a height of the second gate cut, as taught by Bouche, for the purpose of providing improvements in terms of accuracy, cost-efficiency, and device performance, compared to conventional approaches to forming metal gate cuts ([30], Bouche).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bayati (US 2024/0105800) in view of Chiang (US 2022/0352150), and further in view of Ching (US 2019/0067417).
Regarding claim 13, Bayati in view of Chiang discloses the electronic device of claim 9 as described above.
Bayati in view of Chiang does not explicitly disclose the first dielectric material has a different material composition than the second dielectric material.
Ching teaches, in at least figures 1A-1B and related text, the device comprising the first dielectric material (material of 108a, [19], [41]) has a different material composition than the second dielectric material (material of 108b, [19], [41]), for the purpose of providing dielectric fill fins along with device fins thereby improving uniformity of fin density and providing better structure fidelity ([16]).
Bayati, Chiang, and Ching are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Bayati in view of Chiang with the specified features of Ching because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Bayati in view of Cheng to have the first dielectric material having a different material composition than the second dielectric material, as taught by Ching, for the purpose of providing dielectric fill fins along with device fins thereby improving uniformity of fin density and providing better structure fidelity ([16], Ching).
Claim(s) 15-16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ching (US 2019/0067417) in view of Chiang (US 2022/0352150), and further in view of Cheng (US 2022/0254776).
Regarding claim 15, Ching discloses, in at least figures 1A-1B and related text, an integrated circuit (the limitation of "an integrated circuit" has not patentable weight because it is interpreted as intended use) comprising:
a first semiconductor region (110 of 104b, [19], [22], [30]) above a dielectric fill (106a/106b, [20]) and extending in a first direction (Y direction, figures) between corresponding source (one of pair 112 of 104b, [19], [22]) and drain (another one of pair 112 of 104b, [19], [22]) regions;
a second semiconductor region (110 of 104c, [19], [22], [30]) above the dielectric fill (106a/106b, [20]) and extending in the first direction (Y direction, figures) between corresponding source (one of pair 112 of 104c, [19], [22]) and drain (another one of pair 112 of 104c, [19], [22]) regions;
a gate structure (114, [22]) extending in a second direction over (X direction, figures) at least the first semiconductor region (110 of 104b, [19], [22], [30]) and the second semiconductor region (110 of 104c, [19], [22], [30]);
a first gate cut (108a, [19]) comprising a first dielectric material ([41]) and extending in a third direction (Z direction, figures) through an entire thickness of the gate structure (114, [22]), the first gate cut (108a, [19]) extending partially into the dielectric fill (106a/106b, [20]); and
a second gate cut (108b, [19]) comprising a second dielectric material ([41]) and extending in the third direction (Z direction, figures) through the gate structure (114, [22]), the second gate cut (108b, [19]) extending partially into the dielectric fill (106a/106b, [20]),
wherein the first gate cut (108a, [19]) is adjacent to a first side (left side of 110 of 104b, figures) of the first semiconductor region (110 of 104b, [19], [22], [30]) and is spaced in the second direction (X direction, figures) from the first side (left side of 110 of 104b, figures) of the first semiconductor region (110 of 104b, [19], [22], [30]) by a first distance, and the second gate cut (108a, [19]) is adjacent to the corresponding first side (left side of 110 of 104c, figures) of the second semiconductor region (110 of 104c, [19], [22], [30]) and is spaced in the second direction (X direction, figures) from the corresponding first side (left side of 110 of 104c, figures) of the second semiconductor region (110 of 104c, [19], [22], [30]) by a second distance, the second distance differing by at least 4 nm from the first distance ([21]).
Ching does not explicitly disclose a second gate cut comprising a second dielectric material and extending in the third direction through the entire thickness of the gate structure, the second gate cut extending partially into the dielectric fill.
Chiang teaches, in at least figures 2Z, 3E, and related text, the device comprising a second gate cut (178, [81]) comprising a second dielectric material ([81]) and extending in the third direction through the entire thickness of the gate structure (110/114/184, [91]), the second gate cut (178, [81]) extending partially into the dielectric fill (126, [39]), for the purpose of providing an integrated circuit with nanosheet transistors having improved performance ([16]).
Ching and Chiang are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ching with the specified features of Chiang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Ching to have the second gate cut comprising a second dielectric material and extending in the third direction through the entire thickness of the gate structure, the second gate cut extending partially into the dielectric fill, as taught by Chiang, for the purpose of providing an integrated circuit with nanosheet transistors having improved performance ([16], Chiang).
Regarding claim 16, Ching in view of Chiang discloses the integrated circuit of claim 15 as described above.
Ching further discloses, in at least figures 1A-1B and related text, the gate structure (114, [22]) includes a gate dielectric (116, [22]) around the first (110 of 104b, [19], [22], [30]) and second (110 of 104c, [19], [22], [30]) semiconductor regions.
Chiang further teaches, in at least figures 2Z, 3E, and related text, the gate dielectric (158, [81]) is not present on any sidewall of the first gate cut (186, [87]) and not present on any sidewall of the second gate cut (178, [81]), for the purpose of providing an integrated circuit with nanosheet transistors having improved performance ([16]).
Regarding claim 18, Ching in view of Chiang discloses the integrated circuit of claim 15 as described above.
Chiang further teaches, in at least figures 2Z, 3E, and related text, a width at a top of the second gate cut (178, [81]) is at least twice as large as a width at a top of the first gate cut (186, [87]) (figure), for the purpose of providing an integrated circuit with nanosheet transistors having improved performance ([16]).
Claim(s) 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ching (US 2019/0067417) in view of Chiang (US 2022/0352150), and further in view of Bayati (US 2024/0105800).
Regarding claim 17, Ching in view of Chiang discloses the integrated circuit of claim 15 as described above.
Ching in view of Chiang does not explicitly disclose the first gate cut and the second gate cut each has a height in the third direction, and their respective heights differ by no more than 4 nm.
Bayati teaches, in at least figure 3C and related text, the device comprising the first gate cut (311, [68]) and the second gate cut (313, [68]) each has a height in the third direction (vertical direction, figure), and their respective heights differ by no more than 4 nm (ΔH, [68]), for the purpose of providing gate cuts having a high length-to-width aspect ratio (e.g., 5:1 or higher) ([14]) thereby improving density of integration.
Ching, Chiang, and Bayati are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ching in view of Chiang with the specified features of Bayati because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Ching in view of Chiang to have the first gate cut and the second gate cut each having a height in the third direction, and their respective heights differ by no more than 4 nm, as taught by Bayati, for the purpose of providing gate cuts having a high length-to-width aspect ratio (e.g., 5:1 or higher) ([14], Bayati) thereby improving density of integration.
Regarding claim 19, Ching in view of Chiang discloses the integrated circuit of claim 15 as described above.
Ching in view of Chiang does not explicitly disclose the first gate cut and the second gate cut each has a height-to-width aspect ratio of 5:1 or higher.
Bayati teaches, in at least figure 3C and related text, the device comprising the first gate cut (311, [68]) and the second gate cut (313, [68]) each has a height-to-width aspect ratio of 5:1 or higher ([15]), for the purpose of providing gate cuts having a high length-to-width aspect ratio (e.g., 5:1 or higher) ([14]) thereby improving density of integration.
Ching, Chiang, and Bayati are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ching in view of Chiang with the specified features of Bayati because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Ching in view of Chiang to have the first gate cut and the second gate cut each having a height-to-width aspect ratio of 5:1 or higher, as taught by Bayati, for the purpose of providing gate cuts having a high length-to-width aspect ratio (e.g., 5:1 or higher) ([14], Bayati) thereby improving density of integration.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ching (US 2019/0067417) in view of Chiang (US 2022/0352150), and further in view of Bouche (US 2022/0157722).
Regarding claim 20, Ching in view of Chiang discloses the integrated circuit of claim 15 as described above.
Ching in view of Chiang does not explicitly disclose a conductive via that extends in the third direction through a height of the second gate cut.
Bouche teaches, in at least figure 4A and related text, the device comprising a conductive via (322, [76]) that extends in the third direction (vertical direction, figure) through a height of the second gate cut (312-2, [74]), for the purpose of providing improvements in terms of accuracy, cost-efficiency, and device performance, compared to conventional approaches to forming metal gate cuts ([30]).
Ching, Chiang, and Bouche are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ching in view of Chiang with the specified features of Bouche because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Ching in view of Chiang to have the conductive via that extends in the third direction through a height of the second gate cut, as taught by Bouche, for the purpose of providing improvements in terms of accuracy, cost-efficiency, and device performance, compared to conventional approaches to forming metal gate cuts ([30], Bouche).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811