DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
1. Applicant’s election without traverse of Group I, claims 1-7 in the reply filed on 12/22/2025 is acknowledged.
Claims 1-7 are being examined in this Office Action. Claims 8-20 are cancelled. Claims 21-33 are withdrawn.
Claim Objections
2. The claims are objected because of the following reasons:
Re claim 1, lines 7-8: in between “body material” insert --semiconductor--, because floating body semiconductor material is prior claimed.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 1, 3 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Endoh et al. (US 2013/0119452).
Re claim 1, Endoh teaches, under BRI, Figs. 1, 2, 3H, 5, 15 & 17, abstract, [0007, 0034, 0189, 0193], a memory cell structure, comprising:
-a first semiconductor material (semiconductor pillar 2);
-a floating body semiconductor material (floating gate 5 composed of poly Si) having an internal side surface that surrounds and connects to the first semiconductor material (2);
-a second semiconductor material (material of upper CG 4) having an internal side surface that surrounds and connects to the floating body semiconductor material (5);
-a first dielectric layer (upper 7) connected to a top surface of the floating body material (5);
-a second dielectric layer (lower 7) connected to a bottom surface of the floating body material (5);
-a front gate (upper CG 4) connected to the first dielectric layer (upper 7); and
-a back gate (lower CG 4) connected to the second dielectric layer (lower 7).
Note: connect # directly/physically connect.
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448
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Re claim 3, Endoh teaches a metal line (BL) connected to the first semiconductor material (Fig. 17, [0242]).
Re claim 5, Endoh teaches, Fig. 3G, the first and second dielectric layers (7) comprise one of an oxide material (SiO2) [0194] and a high-K material.
3. Claims 1, 3 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Alsmeier et al. (US 2012/0001249).
Re claim 1, Alsmeier teaches, under BRI, Figs. 1A-4 & 10, [0038, 0043, 0046, 0048, 0049, 0052, 0055, 0057, 0070, 0076], a memory cell structure, comprising:
-a first semiconductor material (semiconductor channel 1);
-a floating body semiconductor material (storage element/floating gate 9a) having an internal side surface that surrounds and connects to the first semiconductor material (2);
-a second semiconductor material (of CG 3) having an internal side surface that surrounds and connects to the floating body semiconductor material (9a);
-a first dielectric layer (left 11 or 7a) connected to a top surface of the floating body material (9a);
-a second dielectric layer (right 11 or 7a) connected to a bottom surface of the floating body material (9a);
-a front gate (upper CG 3a or 202) connected to the first dielectric layer (7a or 11); and
-a back gate (lower CG 3b or 102) connected to the second dielectric layer (7a or 11).
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Note: in Fig. 10, layers 121a, b, similar to 3a, comprise semiconductor material [0051, 0052]. Connect # directly/physically connect
Re claim 3, Alsmeier teaches, Fig. 1A, [0076], a metal line (202, when consider 3a as front gate) connected to the first semiconductor material (1).
Re claim 5, Alsmeier teaches the first and second dielectric layers (7a or 11) comprise one of an oxide material and a high-K material [0048, 0055].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 2, 4, 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Endoh in view of Lee et al. (US 2018/0261620).
The teachings of Endoh have been discussed above.
Re claims 2 & 4, Endoh teaches the first semiconductor material comprises N+ type doping [0026] or P + type doping [0026].
Endoh does not explicitly teach the floating body semiconductor material comprises P-type doping or N-type doping, and the second semiconductor material comprises N+ type doping or P+ type doing.
Lee teaches “a semiconductor material, such as n-type poly-silicon or n-type epitaxial single crystal silicon, doped with phosphorus or arsenic, p-type poly-silicon or p-type epitaxial single crystal silicon doped with boron” [0055].
As taught by Lee, one of ordinary skill in the art would utilize & modify the above teaching into Endoh to obtain the floating body semiconductor material comprises P-type doping or N-type doping, and the second semiconductor material comprises N+ type doping or P+ type doing as claimed, because N-type and P-type semiconductors are known in the art for enhancing conductivity and performance of the formed device.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lee in combination with Endoh due to above reason.
Re claims 6 & 7, in combination cited above, Lee teaches the first and second dielectric layers comprises charge-trapping layers, wherein the charge-trapping layers comprise oxide-nitride-oxide layers [0078].
“It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.”
5. Claims 2-4, 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Alsmeier in view of Lee et al. (US 2018/0261620).
The teachings of Alsmeier have been discussed above.
Re claims 2 & 4, Alsmeier teaches the first semiconductor material (1) comprises N+ type doping or P + type doping [0070]; and the second semiconductor material comprises N+ type doping or P+ type doping (of 121, [0052]).
Alsmeier teaches the floating body semiconductor material comprises doping (e.g., doped polysilicon) [0057], but does not explicitly teach the floating body semiconductor material comprises P-type doping or N-type doping.
Lee teaches “a semiconductor material, such as n-type poly-silicon or n-type epitaxial single crystal silicon, doped with phosphorus or arsenic, p-type poly-silicon or p-type epitaxial single crystal silicon doped with boron” [0055].
As taught by Lee, one of ordinary skill in the art would utilize & modify the above teaching into Alsmeier to obtain the floating body semiconductor material comprises P-type doping or N-type doping as claimed, because N-type and P-type semiconductors are known in the art for enhancing conductivity and performance of the formed device.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lee in combination with Alsmeier due to above reason.
Re claim 3, in combination cited above, Lee teaches a metal line (bit line, control line) connected to the fist semiconductor material [0085].
Re claims 6 & 7, in combination cited above, Lee teaches the first and second dielectric layers comprises charge-trapping layers, wherein the charge-trapping layers comprise oxide-nitride-oxide layers [0078].
“It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.”
Response to Arguments
6. Applicant's arguments filed 10/8/2025 have been fully considered but they are not persuasive.
Applicant submits, page 10, “First, Endoh's floating gate (5) is an electrode for charge trapping in flash, not a "floating body semiconductor material" as claimed (i.e., an isolated channel using body-effect storage).
Second, the floating gate (5) surrounds the pillar (2) via an insulator (6), and does not directly "connects to" it-the claim requires direct connection (e.g., junction for carrier flow, as in Applicant's N+/P- doping).
Third, there is no second semiconductor surrounding a floating body; Endoh's control gate (4) surrounds the floating gate radially along sides, not an annular body.
Fourth, Endoh's dielectrics (6/7/8) are on side surfaces (radial, surrounding circumference vertically), not "connected to a top surface" and "bottom surface" of the floating body as claimed (planar ends for horizontal dual gate). Endoh’s gates (4) are side-surrounding (vertical orientation), not front/back on top/bottom”.
The examiner respectfully disagrees.
Under BRI, first, Endoh teaches floating gate 5 composed of poly Si [0193], it is equivalent to claimed floating body semiconductor material. The claim does not require an isolated channel. Second, the claim does not require “connects” as directly “connects to”, hence, Endoh teaches the floating body semiconductor material (5) surrounds and connects to the first semiconductor material (2). Third, in view of Fig. 15, Endoh teaches control gate 4 surrounds the floating gate 5. Clearly there is no annual body in the claim. Fourth, the claim does not require “directly connect”, under BRI, Endoh teaches first & second dielectric layers (upper and lower insulating layer 7) connected to top & bottom surfaces of the floating body material (5), and first & back gate (4) connected to the first & second dielectric layers (7) within memory (10A). Accordingly, Endoh anticipates claim 1.
Applicant submits, page 12, “First, Alsmeier's charge storage is for flash trapping, and does not have a "floating body semiconductor material" as an isolated channel. The channel (1) is the central pillar, vertically continuous and not annular or floating.
Second, Alsmeier's charge storage (9a) surrounds the channel via tunnel dielectric (11), and is therefore insulated, and does not directly "connects to" the channel.
Third, there is no second semiconductor surrounding and directly connected to the floating body. Control gates (3a) surround charge storage segments radially along sides but are isolated from the charge storage segments (9a) by dielectric layer (7a).”
The examiner respectfully disagrees.
The claim requires a floating body semiconductor material, but does not clearly require it is an isolated channel. Alsmeier teaches charge storage material may comprises semiconductor floating gate material [0057], it is equivalent to “floating body semiconductor material” as claimed. The claim does not require “directly connects to”, and Alsmeier teaches dielectric (11) connects to the floating body material (9a), and second semiconductor material (of CG 3) [0043] surrounds & connects to the floating body material (9a). Accordingly, Alsmier anticipates claim 1.
As result, given a broadest reasonable interpretation, Endoh & Alsmier teach the claimed invention.
Terminal Disclaimer submitted on 10/8/20255, and Double Patenting rejection is withdrawn.
Conclusion
7. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 1/8/26