DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 10, 20-26, and 29-30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (U.S. Publication No. 2021/0336012 A1; hereinafter Huang)
With respect to claim 1, Huang discloses a semiconductor device comprising: an insulator layer [1302]; a transistor upon the insulator layer, the transistor includes one or more channel regions [208], a first source or drain (S/D) region [610] upon the insulator layer and connected to the one or more channel regions, and a second S/D region [610/1202] that extends below a top surface of the insulator layer; and a liner [1502] upon a section of the insulator layer, the liner comprising a front portion in contact with a front surface of the second S/D region and a rear portion in contact with a rear surface of the second S/D region (see Figure 22B; liner wraps around second S/D region).
With respect to claim 2, Huang discloses wherein a bottom surface of the second S/D region is coplanar with a bottom surface of the insulator layer (See Figure 22B).
With respect to claim 3, Huang discloses a frontside S/D contact [716] connected to a top surface of the first S/D region (See Figure 22B).
With respect to claim 4, Huang discloses a backside S/D contact [1402] connected to a bottom surface of the second S/D region (See Figure 22B).
With respect to claim 5, Huang discloses a backside rail connected to a bottom surface of the backside S/D contact (see ¶[0057]; 1402 includes a power rail and multiple metal lines for direct contacting S/D region).
With respect to claim 6, Huang discloses wherein the transistor is a gate all around nanosheet structure that includes a plurality of channel regions each surrounded by one work function metal gate (see ¶[0014] and ¶[0039]).
With respect to claim 7, Huang discloses wherein a top surface of the first S/D region is coplanar with a top surface of the second S/D region (See Figure 22B).
With respect to claim 10, Huang discloses wherein the first S/D region is formed of a first material and wherein the second S/D region is formed of a second material different than the first material (See ¶[0033] and ¶[0053-0055]).
With respect to claim 20, Huang discloses a transistor comprising: one or more channel regions [208]; a single gate [702] that is around each of the one or more channel regions; a first source or drain (S/D) region [610] connected to the one or more channel regions; and a second S/D region [610/1202] connected to the one or more channel regions, wherein a bottom surface of the second S/D region is below a bottom surface of the single gate (See Figure 22B). With respect to claim 21, Huang discloses wherein a bottom surface of the second S/D region is coplanar with a backside interlayer dielectric [1502].
With respect to claim 22, Huang discloses a frontside S/D contact [716] connected to a top surface of the first S/D region (See Figure 22B).
With respect to claim 23, Huang discloses a backside S/D contact [1402] connected to a bottom surface of the second S/D region (See Figure 22B).
With respect to claim 24, Huang discloses a backside rail connected to a bottom surface of the backside S/D contact (see ¶[0057]; 1402 includes a power rail and multiple metal lines for direct contacting S/D region).
With respect to claim 25, Huang discloses wherein the transistor is a gate all around nanosheet structure that includes a plurality of channel regions each surrounded by one work function metal gate (see ¶[0014] and ¶[0039]).
With respect to claim 26, Huang discloses wherein a top surface of the first S/D region is coplanar with a top surface of the second S/D region (See Figure 22B)
With respect to claim 29, Huang discloses wherein the first S/D region is formed of a first material and wherein the second S/D region is formed of a second material different than the first material (See ¶[0033] and ¶[0053-0055]).
With respect to claim 30, Huang discloses a semiconductor device comprising: nanosheet channels [208]; a gate around [702] each of the nanosheet channels; a first source or drain (S/D) region [610] connected to the nanosheet channels and upon an insulator layer [1302]; a second S/D region [610/1202] connected to the nanosheet channels and that extends through the insulator layer; an interlayer dielectric (see ¶[0029]) upon the insulator layer, upon the first S/D region, and upon the second S/D region; and a liner [1502] upon the insulator layer and connected to solely the second S/D region (see Figure 22B).
Allowable Subject Matter
Claims 8-9 and 27-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claims 8 and 27, none of the prior art teaches or suggests, alone or in combination, wherein a top surface of the first S/D region is below a top surface of the second S/D region.
With respect to claims 9 and 28, none of the prior art teaches or suggests, alone or in combination, wherein the second S/D region wraps around a perimeter of the backside S/D contact.
Response to Arguments
Applicant's arguments filed 12/15/2025 have been fully considered but they are not persuasive. With respect to arguments made in regards to claim 1, 20, and 30, Applicant has argued that Huang fails to disclose “a second S/D region that extends below a top surface of the insulator layer,” arguing that [1202] cannot be considered part of “a second S/D region.” Examiner respectfully disagrees. No structural limitations within the claim excludes [1202] from being included in “a second S/D region” as a region can be broadly interpreted as the specific source/drain feature and physically contiguous conductive elements that provide electrical contact with the source/drain. [1202] provides electrical connection to the source/drain within the second S/D region and physically interfaces, therefore can be considered a singular region i.e., a second S/D region (see Huang ¶[0055]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN LOKE can be reached at 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JONATHAN HAN/Primary Examiner, Art Unit 2818