DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 12/31/2025 has been entered. Claims 1 and 7-20 remain pending in the application. Claims 2-6 have been cancelled. Claims 15-20 were previously withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, 8 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Morihara et al., (United States Patent Application Publication Number, US 2014/0184352 A1) hereinafter referenced as Morihara, in view of Ichitsubo et al., (United States Patent Application Publication Number, US 2005/0266617 A1) hereinafter referenced as Ichitsubo, and in view of Gavagnin et al., (United States Patent Application Publication Number, US 2020/0357706 A1) hereinafter referenced as Gavagnin.
Regarding claim 1, Morihara teaches a power amplifier package, comprising: a package body having a package topside surface and a package bottomside surface opposite the package topside surface in a package height direction (Fig.24, shows the package with a topside and a bottomside surface opposite to each other in height direction), the package body comprising: an air cavity (Fig.24, formed by element #39a and #39b, the lid is bonded to the substrate which leaves air inside the cavity), a package substrate having a side with electrodes bounding a portion of the air cavity (Fig.24, top side of element #10 has electrodes, elements #16, #15, #14, #13, #12 and #11 and bounds the cavity).
Morihara does not teach the substrate having a populated side. Ichitsubo teaches the substrate having a populated side and radio frequency (RF) circuitry attached to the populated side (Fig.1, element #10 top surface is populated with element #20, #30 and #40 and paragraph [0019], rows 3-4). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ichitsubo and disclose the substrate having a populated side and radio frequency (RF) circuitry attached to the populated side. As disclosed by Ichitsubo, populating the substrate with circuitry can be used to manufacture RF circuits with improved RF performance.
Morihara further teaches lid-facing contacts provided on the populated side of the package substrate (Fig.2, elements #11, #12, #15 and #16 have lid facing contacts, paragraph [0078], rows 1-8, paragraph [0080], rows 1-5, provide on the top side of the substrate), and an electrically-routed lid (Fig.24, element #30 has vias, elements #35 and #36) bonded to the package substrate to sealingly enclose the air cavity (Fig.24, element #38 bonds the lid, element #30, to the substrate, element #10 and seals the cavity, paragraph [0081], rows 2-3), the electrically-routed lid comprising: an upper lid wall defining at least a portion of the package topside surface (Fig.24, lid, element #30, has an upper lid wall with the topside surface being the topside surface of the package), peripheral lid sidewalls joined to the upper lid wall and bounding a periphery of the air cavity (Fig.24, lid, element #30, has sidewalls joined with the upper lid, which bound the air cavity), sidewall-embedded vias contained in the peripheral lid sidewalls and each extending essentially in the package height direction (Fig.24, element #35 and #36) and substrate-facing lid contacts distributed along a lower edge of the peripheral lid sidewalls (Fig.24, element #55 and #56) and electrically coupled to the sidewall-embedded vias (paragraph [0121], rows 7-11). As noted above, Ichitsubo teaches radio frequency (RF) circuitry attached to the populated side of the substrate (top side of the substrate). Since Morihara teaches the top side of the substrate inside the air cavity, the combination of Morihara and Ichitsubo teaches the RF circuitry being located within the cavity.
Morihara further teaches a topside input/output (I/O) interface on the package topside surface (Fig.1, external electrodes, elements #41a, #42a, #43a, #43b, #43c, #44a, #44b, #44c, #45a, #45b, #46a and #46b form the I/O interface and are connected to input or output, paragraph [0077], rows 1-4 and paragraph [0078], rows 5-7) and electrically interconnected with the circuitry on the substrate through the sidewall-embedded vias of the electrically-routed lid (paragraph [0077], rows 1-4 and paragraph [0078], rows 5-7). As noted above, Ichitsubo teaches RF circuitry attached to the circuitry of the substrate. Therefore, the combination of Morihara and Ichitsubo teaches the (I/O) interface on the packaged topside surface is electrically interconnected with the RF circuitry through the sidewall-embedded vias of the electrically-routed lid.
Morihara further teaches wherein the package body further comprises a bond layer system attaching the lower edge of the peripheral lid sidewalls to the populated side of the package substrate (Fig.24, element #38 attaches the lower edge of lid, element #30, to the top surface of substrate, element #10) that forms a 360 degree seal at an interface between the electrically-routed lid and the package substrate (paragraph [0122], rows 1-9).
Morihara does not teach wherein the bond layer includes the discrete bodies of electrically conductive materials, element, #50b, that are between the lid-facing contacts, elements #15 and the substrate-facing lid contacts, element #50a. The combination of Morihara and Ichitsubo does not teach the bond layer includes discrete bodies of electrically-conductive epoxy between the lid-facing contacts and the substrate-facing lid contacts, and a dielectric bond layer formed exclusively from a cured B-stage epoxy that attaches the electrically-routed lid to the package. Gavagnin teaches wherein the bond layer system (Fig.2, formed by element #120 and #132) includes discrete bodies of electrically-conductive epoxy (Fig.10, elements #132, paragraph [0069], rows 1-3) between the lid-facing contacts (Fig.2, elements #122 of the top element #118) and the substrate-facing lid contacts (Fig.2, elements #122 of the bottom element #118) , and a dielectric bond layer formed exclusively from a cured B-stage epoxy (Fig.2, element #120, paragraph [0069], rows 4-8) that attaches the electrically-routed lid to the package substrate Fig.2, element #120, attaches the two). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Gavagnin and disclose the bond layer includes discrete bodies of electrically-conductive epoxy between the lid-facing contacts and the substrate-facing lid contacts, and a dielectric bond layer formed exclusively from a cured B-stage epoxy that attaches the electrically-routed lid to the package. As disclosed by Gavagnin, the bond layer can be formed by additive manufacturing, in particular printing (paragraph [0028]) which eliminates cumbersome patterning procedures (paragraph [0035], rows 14-16).
Regarding claim 7, the combination of Morihara, Ichitsubo and Gavagnin teaches the package of claim 1 as set forth in the obviousness rejection. Morihara further teaches the package of claim 1, wherein the lid-facing contacts align with corresponding ones of the substrate-facing lid contacts as taken along axes extending in the package height direction (Fig.24, elements #15 and #16 align with elements #55 and #56 in vertical direction).
Regarding claim 8, the combination of Morihara, Ichitsubo and Gavagnin teaches the package of claim 1 as set forth in the obviousness rejection. Morihara further teaches the package of claim 1, wherein the topside I/O interface comprises electrically-conductive pads formed on a surface of the upper lid wall facing away from the package substrate and in contact with the sidewall-embedded vias (Fig.2, external electrodes, elements #41a, #42a, #43a, #43b, #43c, #44a, #44b, #44c, #45a, #45b, #46a and #46b are on the top surface of the upper lid, and in contact with sidewall vias).
Regarding claim 13, the combination of Morihara, Ichitsubo and Gavagnin teaches the package of claim 1 as set forth in the obviousness rejection. Morihara further teaches the package of claim 1, wherein the peripheral lid sidewalls comprise a first peripheral lid sidewall and a second peripheral lid sidewall (Fig.1, first peripheral wall is the left sidewall, and second peripheral wall is the right sidewall); wherein the topside I/O interface comprises an RF input terminal (Fig.1, located on the left sidewall, paragraph [0077], rows 1-4) and an RF output terminal (Fig.1, located on the left sidewall, paragraph [0078], rows 5-7); and wherein the sidewall-embedded vias comprise: a first sidewall-embedded via electrically coupled to the input terminal and extending within the first peripheral lid sidewall from the input terminal toward the package substrate (Fig.1, element #31, paragraph [0077], rows 1-4); and a second sidewall-embedded via electrically coupled to the output terminal and extending within the second peripheral lid sidewall from the output terminal toward the package substrate (Fig.1, element #32a, paragraph [0078], rows 1-5). As noted in the obviousness rejection of claim 1, Ichitsubo teaches the circuitry is RF circuitry, therefore the input and the output terminals are RF input and RF output terminals, respectively.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Morihara in view of Ichitsubo, Gavagnin and in view of Holmberg, (United States Patent Number, US 7,381,906 B2), hereinafter referenced as Holmberg.
Regarding claim 9, the combination of Morihara, Ichitsubo and Gavagnin teaches the package of claim 1 as set forth in the obviousness rejection. Morihara further teaches wherein the upper lid wall and the peripheral lid sidewalls are composed of a dielectric material (lid is made of glass, paragraph [0107], rows 1-3). The combination of Morihara, Ichitsubo and Gavagnin does not teach wherein the lid walls are composed of a molded dielectric material and the sidewall-embedded vias are at least partly composed of a metallic material. Holmberg teaches wherein the lid walls are composed of a molded dielectric material (Fig.8, sidewall, element #10 is made of silicone and molded, column 4, rows 49-51, cover, element #83 may be made of plastic and molded, column 7, rows 28-31) and the sidewall-embedded vias are at least partly composed of a metallic material (Fig.8, element #11, column 4, rows 57-64). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Holmberg and disclose wherein the lid walls are composed of a molded dielectric material and the sidewall-embedded vias are at least partly composed of a metallic material. As disclosed by Holmberg, molding provides a way to manufacture the lid walls as one or more pieces having different shapes that fit the substrate circuitry and can be combined together (column 8, rows 43-49), while metallic materials are used for the vias to enhance their electric conductivity (column 4, rows 62-64).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Morihara in view of Ichitsubo, Gavagnin, Holmberg and in view of Ito, (United States Patent Application Publication Number, US 2002/0020916 A1), hereinafter referenced as Ito.
Regarding claim 10, the combination of Morihara, Ichitsubo and Gavagnin teaches the package of claim 1 as set forth in the obviousness rejection and the combination of Morihara, Ichitsubo, Gavagnin and Holmberg teaches the package of claim 9 as set forth in the obviousness rejection. The combination of Morihara, Ichitsubo, Gavagnin and Holmberg does not teach the package of claim 9, wherein sidewall-embedded vias comprise plated through holes formed in the peripheral lid sidewalls. Ito teaches wherein the sidewall-embedded vias comprise plated through holes formed in the peripheral lid sidewalls (Fig.2, element #26, paragraph [0037], rows 1-4). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ito and disclose wherein the sidewall-embedded vias comprise plated through holes formed in the peripheral lid sidewalls. Plated through holes enable electrical connections between electronic components located on top and bottom sides of the sidewall, while the sidewall can hold the components firmly attached on the two sides.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Morihara in view of Ichitsubo, Gavagnin, Holmberg, Ito and in view of Shuto, (United States Patent Application Publication Number, US 2017/0271277 A1), hereinafter referenced as Shuto.
Regarding claim 11, the combination of Morihara, Ichitsubo and Gavagnin teaches the package of claim 1 as set forth in the obviousness rejection, the combination of Morihara, Ichitsubo, Gavagnin and Holmberg teaches the package of claim 9 as set forth in the obviousness rejection, and the combination of Morihara, Ichitsubo, Gavagnin Holmberg and Ito teaches the package of claim 10 as set forth in the obviousness rejection. Morihara teaches a via comprises a cylindrical layer electrically coupling a terminal included in the topside I/O interface to a lid-facing contact included in the lid-facing contacts (paragraph [0077], rows 1-4) and a metallic cap covering the via (Fig.24 , element #40a, paragraph [0118], rows 3-4) electrically coupled to the tubular plated layer (Fig.24, element #40 is electrically coupled to via, element #35, paragraph [0118], rows 6-7) and forming a contact in the topside I/O interface of the package (Fig.24, element #40a forms contacts in the topside I/O interface of the package). The combination of Morihara, Ichitsubo, Gavagnin, Holmberg, and Ito does not teach the via is a plated through hole comprising a tubular plated layer, and a backfill material surrounded by the tubular plated layer and a metallic cap covering the plated through hole, electrically coupled to the tubular plated layer. Shuto teaches wherein the plated through holes (Fig.1, element #110b): each comprise a tubular plated layer (Fig.1, opening element #110c is plated with copper, paragraph [0030], rows 7-10) and a backfill material surrounded by the tubular plated layer (Fig.1, element #110d, paragraph [0030, rows 9-11); and a metallic cap covering the plated through hole, electrically coupled to the tubular plated layer (Fig.1, top element #110e, not numbered, paragraph [0044], rows 5-7). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Shuto and disclose a plated through hole comprising a tubular plated layer, and a backfill material surrounded by the tubular plated layer and a metallic cap covering the plated through hole, electrically coupled to the tubular plated layer. Filling the plated through hole with a backfilled material can increase its electrical and thermal conductivity, while the metallic cap covering the plated through hole provides a pad for electrical connections of electronic components.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Morihara in view of Ichitsubo, Gavagnin and in view of Su et al., (United States Patent Application Publication Number, US 2020/0312734 A1), hereinafter referenced as Su.
Regarding claim 12, the combination of Morihara, Ichitsubo and Gavagnin teaches the package of claim 1 as set forth in the obviousness rejection. As noted in the obviousness rejection of claim 1, the combination of Morihara, Ichitsubo and Gavagnin teaches the power amplifier package of claim 1, wherein the RF circuitry comprises an RF power die (Fig.1, element #20 of Ichitsubo is an amplifier). The combination of Morihara, Ichitsubo and Gavagnin does not teach wherein the package body further comprises: a thermal dissipation structure embedded in the package substrate and to which the RF power die is attached; and a primary heat dissipation path extending from the RF power die, through the thermal dissipation structure, and to the package bottomside surface in a direction opposite the electrically-routed lid. Su teaches wherein the package body (Fig.1, element #1) further comprises: a thermal dissipation structure embedded in the package substrate (Fig.1, element #12 is a heat sink embedded in the substrate, element #10, paragraph [0017], rows 1-3) and to which a die is attached (Fig.1, die, element #20 is attached to the heat sink element #12, paragraph [0018], rows 2-4); and a primary heat dissipation path extending from the die, through the thermal dissipation structure, and to the package bottomside surface in a direction opposite lid (Fig.1, heat dissipation path is from the die towards the heat sink, which is a direction opposite the lid formed by element ##231 and #23, paragraph [0029], rows 3-13). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Su and disclose a thermal dissipation structure embedded in the package substrate and to which the die is attached; and a primary heat dissipation path extending from the die, through the thermal dissipation structure, and to the package bottomside surface in a direction opposite the electrically-routed lid. As disclosed by Su, this configuration increases the heat dissipation performance of the semiconductor package, and having the thermal dissipation structure embedded in the substrate eliminated the need for extra steps added in the manufacturing of the package (paragraph [0029], rows 3-13). Su does not teach the die is an RF power die. As noted above, the combination of Morihara and Ichitsubo teaches the die is an RF power die. Therebefore, a person skilled in the art before the effective filing date of the claimed invention, could easily substitute the die disclosed by Su with the RF power die disclosed by the combination of Morihara and Ichitsubo.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Morihara in view of Ichitsubo, Gavagnin and in view of Kang et al., (United States Patent Application Publication Number, US 2014/0160689 A1), hereinafter referenced as Kang.
Regarding claim 14, the combination of Morihara, Ichitsubo and Gavagnin teaches the package of claims 1 and 13 as set forth in the obviousness rejection. Morihara further teaches the package of claim 13, wherein the first peripheral lid sidewall is located opposite the second peripheral lid sidewall as taken along an axis perpendicular to the package height direction (Fig.1, the left sidewall is opposite the right sidewall). Ichitsubo further teaches wherein the RF circuitry comprises an RF power die located between the left and right sides of the substrate (Fig.1, element #20, paragraph [0022], rows 5-6). The combination of Morihara, Ichitsubo and Gavagnin does not teach wherein the RF circuitry comprises an RF power die located between the first peripheral lid sidewall and the second peripheral lid sidewall as further taken along the axis. Kang teaches the RF circuitry comprises an RF power die located between the left and right side of the substrate (Fig.1, element #110, paragraph [0028], row 1-3) where the input connections are on the left side (Fig.1, element #130a, paragraph [0025], row 3) and the output connections are on the right side (Fig.1, element #130b, paragraph [0025], row 4). Thus, by using a package substrate with inputs and output connections on two opposite sides of the substrate, and the RF power die located between the input and output connections of the two sides, and the lid disclosed by Morihara, will result in the RF power die being located between the first peripheral lid sidewall and the second peripheral lid sidewall as further taken along the axis. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings of Kang, Morihara, Ichitsubo and Gavagnin and disclose wherein the RF circuitry comprises an RF power die located between the first peripheral lid sidewall and the second peripheral lid sidewall as further taken along the axis. Disposing the input and output on opposite sides of the RF power die helps reduce the electrical interference between the two terminals and simplifies wiring path design.
Response to Arguments
Applicant’s arguments filed on 12/31/2025 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to claims have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chang et al. (United States Patent Application Publication Number US 2022/0320047 A1) teaches a bond layer system includes discrete bodies of electrically-conductive material between facing contacts of two devices and a dielectric bond layer formed of a polymer (Fig.2, element #210 and #275),
Hsu at al. (United States Patent Application Publication Number US 2023/0066395 A1) teaches a bond layer system includes discrete bodies of electrically-conductive epoxy between facing contacts of two substrates, and a dielectric bond layer formed of a polymer (Fig.2, element #120 and #132).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899