DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to “Response After Final Action”
The Response After Final Action filed on 05/12/2026 has been entered. Claims 1 and 7-20 remain pending in the application. Claims 2-6 have been cancelled. Applicant’s arguments with respect to the claims have been considered and found persuasive. Therefore, the finality of the office action filed on 03/12/2026 has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, 8, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Enquist et al., (United States Patent Application Publication Number, US 2018/0226375 A1) hereinafter referenced as Enquist, in view of Steeneken et al., (United States Patent Application Publication Number, US 2012/0286588 A1) hereinafter referenced as Steeneken, in view of Morihara et al., (United States Patent Application Publication Number, US 2014/0184352 A1) hereinafter referenced as Morihara and in view of Hunrath et al., (United States Patent Application Publication Number, US 2013/0062099 A1) hereinafter referenced as Hunrath.
Regarding claim 1, Enquist teaches a power amplifier package, comprising: a package body having a package topside surface and a package bottomside surface opposite the package topside surface in a package height direction (Fig.2F, entire structure), the package body comprising: an air cavity (Fig.2F, element #5), a package substrate having a populated side bounding a portion of the air cavity (Fig.2F, top side of element #2 is populated and bounds the air cavity #5), and lid-facing contacts provided on the populated side of the package substrate (Fig.2F, elements #2 must have lid facing contacts connected to interconnects #12 at the interface between element #2 and bottom layer #11), and an electrically-routed lid bonded to the package substrate to sealingly enclose the air cavity (Fig.2F, element #3 is routed, see traces #36, or elements #66 in Fig.2L), the electrically-routed lid comprising: an upper lid wall defining at least a portion of the package topside surface, peripheral lid sidewalls joined to the upper lid wall and bounding a periphery of the air cavity (Fig.2F, element #3 has a top wall and sidewalls bonding cavity #5), sidewall-embedded vias contained in the peripheral lid sidewalls and each extending essentially in the package height direction (Fig.2F, elements #36 and Fig.2L, elements #66), and substrate-facing lid contacts distributed along a lower edge of the peripheral lid sidewalls and electrically coupled to the sidewall-embedded vias (Fig.2L, the bottom side of the lid has substrate-facing contacts to connect vias #66 to elements #12, one contact corresponding to every element #66 and #65, Fig.2L and Fig.2M);
Enquist teaches a MEMS device with electronic circuitry inside the cavity attached to the populated side of the package substrate (Fig.2F, element #37B). Enquist does not teach the electronic circuitry is radio frequency (RF) circuitry. Steeneken teaches a MEMS device with radio frequency (RF) circuitry attached to the populated side of the package substrate (Fig.3). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Steeneken and disclose radio frequency (RF) circuitry attached to the populated side of the package substrate. As disclosed by Steeneken, populating the substrate with circuitry can be used to manufacture a switching circuit employing MEMS devices.
Enquist teaches a topside interface on the package topside surface and electrically interconnected with circuitry through the sidewall-embedded vias of the electrically-routed lid (Fig.2M, element #66 are connected to element #2 and #, paragraph [0063], rows 20-27). The combination of Enquist and Steeneken does not teach the interface is an input/output (I/O) interface. Morihara teaches a MEMS device with a topside input/output (I/O) interface on the package topside surface (Fig.1, external electrodes, elements #41a, #42a, #43a, #43b, #43c, #44a, #44b, #44c, #45a, #45b, #46a and #46b form the I/O interface and are connected to input or output, paragraph [0077], rows 1-4 and paragraph [0078], rows 5-7) and electrically interconnected with the circuitry on the substrate through the sidewall-embedded vias of the electrically-routed lid (paragraph [0077], rows 1-4 and paragraph [0078], rows 5-7). As noted above, Steeneken teaches RF circuitry attached to the circuitry of the substrate. Therefore, the combination of Morihara and Steeneken teaches the (I/O) interface on the packaged topside surface is electrically interconnected with the RF circuitry through the sidewall-embedded vias of the electrically-routed lid. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Morihara and Steeneken and disclose the topside interface on the package topside surface is an input/output (I/O) interface. Disposing the input and output on the topside interface allows the use of a single metal layer for pads/interconnects as compared to disposing them on multiple sides which reduces costs and manufacturing process complexity.
Enquist further teaches a bond layer system attaching the lower edge of the peripheral lid sidewalls to the populated side of the package substrate (Fig.2F, element #10, paragraph [0039], rows 1-10), wherein the bond layer system includes discrete bodies of electrically-conductive traces between the lid-facing contacts and the substrate-facing lid contacts (Fig.2F, elements #12), and a dielectric bond layer that attaches the electrically-routed lid to the package substrate and forms a 360 degree seal at an interface between the electrically-routed lid and the package substrate (Fig.2F, element #14, Fig.2B shows element #14 forming a 360 degree).
Enquist teaches the discrete bodies are formed of copper (paragraph [0032], rows 16-17). Enquist further teaches the package can be formed by bonding elements #2 and #3 using adhesives (paragraph [0060], rows 12-14). The combination of Enquist, Steeneken and Morihara does not teach the discrete bodies are formed of electrically-conductive epoxy and the adhesive is formed exclusively from a cured B-stage epoxy. Hunrath teaches a bond layer system (Fig.8 formed by elements #3 and #7), wherein the bond layer system includes discrete bodies of electrically-conductive epoxy between contacts (Fig.8, element #7 is made of conductive epoxy, paragraph [0089], rows 1-3, between contacts, element #4 and #10, multiple discrete bodies are shown in Fig. 9), and a dielectric bond layer formed exclusively from a cured B-stage epoxy (Fig.8, element #3, paragraph [0056], rows 1-5). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hunrath and disclose the discrete bodies are formed of electrically-conductive epoxy and the adhesive is formed exclusively from a cured B-stage epoxy. This provides a thin bond layer system that can be manufactured at reduce costs.
Regarding claim 7, the combination of Enquist, Steeneken, Morihara and Hunrath teaches the package of claim 1 as set forth in the obviousness rejection. Enquist further teaches wherein the lid-facing contacts align with corresponding ones of the substrate-facing lid contacts as taken along axes extending in the package height direction (Fig.2L, vias #66 and elements #12 are aligned in the package height direction and therefore contacts must be aligned in the same direction. Note that Morihara also teaches the lid-facing contacts align with corresponding ones of the substrate-facing lid contacts as taken along axes extending in the package height direction (Fig.24, elements #15 and #16 align with elements #55 and #56 in vertical direction).
Regarding claim 8, the combination of Enquist, Steeneken, Morihara and Hunrath teaches the package of claim 1 as set forth in the obviousness rejection. Enquist teaches the package of claim 1 wherein the top interface comprises electrically-conductive pads formed on a surface of the upper lid wall facing away from the package substrate and in contact with the sidewall-embedded vias (Fig.2L, elements #65). Note that Morihara also teaches the package of claim 1, wherein the topside I/O interface comprises electrically-conductive pads formed on a surface of the upper lid wall facing away from the package substrate and in contact with the sidewall-embedded vias (Fig.2, external electrodes, elements #41a, #42a, #43a, #43b, #43c, #44a, #44b, #44c, #45a, #45b, #46a and #46b are on the top surface of the upper lid, and in contact with sidewall vias).
Regarding claim 13, the combination of Enquist, Steeneken, Morihara and Hunrath teaches the package of claim 1 as set forth in the obviousness rejection. Morihara further teaches the package of claim 1, wherein the peripheral lid sidewalls comprise a first peripheral lid sidewall and a second peripheral lid sidewall (Fig.1, first peripheral wall is the left sidewall, and second peripheral wall is the right sidewall); wherein the topside I/O interface comprises an RF input terminal (Fig.1, located on the left sidewall, paragraph [0077], rows 1-4) and an RF output terminal (Fig.1, located on the left sidewall, paragraph [0078], rows 5-7); and wherein the sidewall-embedded vias comprise: a first sidewall-embedded via electrically coupled to the input terminal and extending within the first peripheral lid sidewall from the input terminal toward the package substrate (Fig.1, element #31, paragraph [0077], rows 1-4); and a second sidewall-embedded via electrically coupled to the output terminal and extending within the second peripheral lid sidewall from the output terminal toward the package substrate (Fig.1, element #32a, paragraph [0078], rows 1-5). As noted in the obviousness rejection of claim 1, Steeneken teaches the circuitry is RF circuitry, therefore the input and the output terminals are RF input and RF output terminals, respectively. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine incorporate the teaching of Morihara and Steeneken and disclose wherein the topside I/O interface comprises an RF input terminal and an RF output terminal; and wherein the sidewall-embedded vias comprise: a first sidewall-embedded via electrically coupled to the RF input terminal and extending within the first peripheral lid sidewall from the RF input terminal toward the package substrate; and a second sidewall-embedded via electrically coupled to the RF output terminal and extending within the second peripheral lid sidewall from the RF output terminal toward the package substrate. Disposing the input and output on opposite sides of the RF power die helps reduce the electrical interference between the two terminals and simplifies wiring path design.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Enquist in view of Steeneken, Morihara, Hunrath and in view of Holmberg, (United States Patent Number, US 7,381,906 B2), hereinafter referenced as Holmberg.
Regarding claim 9, the combination of Enquist, Steeneken, Morihara and Hunrath teaches the package of claim 1 as set forth in the obviousness rejection. Enquist teaches wherein the upper lid wall and the peripheral lid sidewalls are composed of ceramic or glass (paragraph [0033], rows 202-4), and wherein the sidewall-embedded vias are at least partly composed of a metallic material (Fig.2L, element #66, paragraph [0067], row 13). The combination of Enquist, Steeneken, Morihara and Hunrath does not teach wherein the lid walls are composed of a molded dielectric material. Holmberg teaches wherein the lid walls are composed of a molded dielectric material (Fig.8, sidewall, element #10 is made of silicone and molded, column 4, rows 49-51, cover, element #83 may be made of plastic and molded, column 7, rows 28-31). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Holmberg and disclose wherein the lid walls are composed of a molded dielectric material. As disclosed by Holmberg, molding provides a way to manufacture the lid walls as one or more pieces having different shapes that fit the substrate circuitry and can be combined together (column 8, rows 43-49).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Enquist in view of Steeneken, Morihara, Hunrath, Holmberg and in view of Ito, (United States Patent Application Publication Number, US 2002/0020916 A1), hereinafter referenced as Ito.
Regarding claim 10, the combination of Enquist, Steeneken, Morihara and Hunrath teaches the package of claim 1 as set forth in the obviousness rejection and the combination of Enquist, Steeneken, Morihara, Hunrath and Holmberg teaches the package of claim 9 as set forth in the obviousness rejection. The combination of Enquist, Steeneken, Morihara, Hunrath and Holmberg does not teach the package of claim 9, wherein sidewall-embedded vias comprise plated through holes formed in the peripheral lid sidewalls. Ito teaches wherein the sidewall-embedded vias comprise plated through holes formed in the peripheral lid sidewalls (Fig.2, element #26, paragraph [0037], rows 1-4). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ito and disclose wherein the sidewall-embedded vias comprise plated through holes formed in the peripheral lid sidewalls. Plated through holes enable electrical connections between electronic components located on top and bottom sides of the sidewall, while the sidewall can hold the components firmly attached on the two sides.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Enquist in view of Steeneken, Morihara, Hunrath, Holmberg, Ito and in view of Shuto, (United States Patent Application Publication Number, US 2017/0271277 A1), hereinafter referenced as Shuto.
Regarding claim 11, the combination of Enquist, Steeneken, Morihara and Hunrath teaches the package of claim 1 as set forth in the obviousness rejection, the combination of Enquist, Steeneken, Morihara, Hunrath and Holmberg teaches the package of claim 9 as set forth in the obviousness rejection, and the combination of Enquist, Steeneken, Morihara, Hunrath, Holmberg and Ito teaches the package of claim 10 as set forth in the obviousness rejection. Morihara further teaches a via comprises a cylindrical layer electrically coupling a terminal included in the topside I/O interface to a lid-facing contact included in the lid-facing contacts (paragraph [0077], rows 1-4) and a metallic cap covering the via (Fig.24 , element #40a, paragraph [0118], rows 3-4) electrically coupled to the tubular plated layer (Fig.24, element #40 is electrically coupled to via, element #35, paragraph [0118], rows 6-7) and forming a contact in the topside I/O interface of the package (Fig.24, element #40a forms contacts in the topside I/O interface of the package). The combination of Enquist, Steeneken, Morihara, Hunrath, Holmberg, and Ito does not teach the via is a plated through hole comprising a tubular plated layer, and a backfill material surrounded by the tubular plated layer and a metallic cap covering the plated through hole, electrically coupled to the tubular plated layer. Shuto teaches wherein the plated through holes (Fig.1, element #110b): each comprise a tubular plated layer (Fig.1, opening element #110c is plated with copper, paragraph [0030], rows 7-10) and a backfill material surrounded by the tubular plated layer (Fig.1, element #110d, paragraph [0030, rows 9-11); and a metallic cap covering the plated through hole, electrically coupled to the tubular plated layer (Fig.1, top element #110e, not numbered, paragraph [0044], rows 5-7). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Morihara and Shuto and disclose a plated through hole comprising a tubular plated layer, and a backfill material surrounded by the tubular plated layer and a metallic cap covering the plated through hole, electrically coupled to the tubular plated layer. Filling the plated through hole with a backfilled material can increase its electrical and thermal conductivity, while the metallic cap covering the plated through hole provides a pad for electrical connections of electronic components.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Enquist in view of, Steeneken, Morihara, Hunrath, in view of Hoekstra et al., (United States Patent Application Publication Number, US 2017/0374441 A1), hereinafter referenced as Hoekstra and in view of Su et al., (United States Patent Application Publication Number, US 2020/0312734 A1), hereinafter referenced as Su.
Regarding claim 12, the combination of Enquist, Steeneken, Morihara and Hunrath teaches the package of claim 1 as set forth in the obviousness rejection. As noted in the rejection of claim 1, Steeneken teaches a MEMS device with radio frequency (RF) circuitry attached to the populated side of the package substrate (Fig.3). Enquist also teaches circuit dies attached to the populated side of the package substrate (Fig.2F, element #37B). The combination of Enquist, Steeneken, Morihara and Hunrath does not teach the dies are RF power dies. Hoekstra teaches RF power dies attached to the populated side of the substrate (paragraph [0009], rows 1-6).It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Hoekstra and disclose RF power dies attached to the populated side of the substrate. Placing the RF power die inside the cavity, on the populate side of the substrate, may be used to buffer and amplify the output signal therefore providing the package with more functionality .
The combination of Enquist, Steeneken, Morihara, Hunrath and Hoekstra does not teach wherein the package body further comprises: a thermal dissipation structure embedded in the package substrate and to which the RF power die is attached; and a primary heat dissipation path extending from the RF power die, through the thermal dissipation structure, and to the package bottomside surface in a direction opposite the electrically-routed lid. Su teaches wherein the package body (Fig.1, element #1) further comprises: a thermal dissipation structure embedded in the package substrate (Fig.1, element #12 is a heat sink embedded in the substrate, element #10, paragraph [0017], rows 1-3) and to which a die is attached (Fig.1, die, element #20 is attached to the heat sink element #12, paragraph [0018], rows 2-4); and a primary heat dissipation path extending from the die, through the thermal dissipation structure, and to the package bottomside surface in a direction opposite lid (Fig.1, heat dissipation path is from the die towards the heat sink, which is a direction opposite the lid formed by element ##231 and #23, paragraph [0029], rows 3-13). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Su and disclose a thermal dissipation structure embedded in the package substrate and to which the die is attached; and a primary heat dissipation path extending from the die, through the thermal dissipation structure, and to the package bottomside surface in a direction opposite the electrically-routed lid. As disclosed by Su, this configuration increases the heat dissipation performance of the semiconductor package, and having the thermal dissipation structure embedded in the substrate eliminates the need for extra steps added in the manufacturing of the package (paragraph [0029], rows 3-13). Su does not teach the die is an RF power die. As noted above, Hoekstra teaches the die is an RF power die. A person skilled in the art, before the effective filing date of the claimed invention, would recognize that cooling structure as disclosed by Su, can be applied in the same way to any die, including RF power dies.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Enquist in view of Steeneken, Morihara, Hunrath and in view of Tabrizi et al., (United States Patent Application Publication Number, US 2010/0244161 A1), hereinafter referenced as Tabrizi.
Regarding claim 14, the combination of Enquist, Steeneken, Morihara, Hunrath teaches the package of claims 1 and 13 as set forth in the obviousness rejection. As noted in the rejection of claim 13, Morihara further teaches the package of claim 13, wherein the first peripheral lid sidewall is located opposite the second peripheral lid sidewall as taken along an axis perpendicular to the package height direction (Fig.1, first peripheral wall is the left sidewall, and second peripheral wall is the right sidewall). Furthermore, as noted in the rejection of claim 1, Steeneken teaches a MEMS device with radio frequency (RF) circuitry attached to the populated side of the package substrate (Fig.3). Enquist also teaches circuit dies located between the left sidewall and right sidewall as taken along an axis perpendicular to the package height direction (Fig.2F, element #37B). The combination of Enquist, Steeneken, Morihara, Hunrath does not teach wherein the dies are RF power dies. Tabrizi teaches a MEMS system with an RF power die (paragraph [0006] rows 1-4, paragraph [0043], rows 1-5 paragraph [0044], rows 5-8) located between the left sidewall and right sidewall as taken along an axis perpendicular to the package height direction (Fig.5b, element #100’ is located between the left and right sidewalls). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Tabrizi wherein the RF circuitry comprises an RF power die located between the first peripheral lid sidewall and the second peripheral lid sidewall as further taken along the axis. As disclosed by Tabrizi, placing the RF power die inside the cavity between the first peripheral lid sidewall and the second peripheral lid sidewall as further taken along the axis, may facilitate the production of smaller overall packages that could be provided if the same devices were packaged separately, and provide packages with more functionality (paragraph [0044]).
Response to Arguments
Applicant’s arguments filed on 05/12/2026 have been fully considered with respect to the rejections as set forth in this office action, but they are moot because the new grounds of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Viswanathan et al. (United States Patent Number US 9,922,894 B1) teaches a dielectric bond layer formed exclusively from a cured B-stage epoxy that attaches lid to the package substrate and forms a 360 degree seal at an interface between the electrically-routed lid and the package substrate (Fig.1, element #32, column 11, rows 45-51).
Tosaya et al. (United States Patent Application Publication Number, US 2016/0079093 A1 B1) teaches a bond layer system that includes discrete bodies of electrically-conductive connections between contacts of a substrate and a die, and dielectric bond layer formed exclusively from a cured B-stage epoxy that attaches a die to the package substrate (Fig.1).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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