DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the amendments filed on 05/11/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 05/11/2026 in reply to the non-final rejection mailed on 02/09/2026, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are Claims 1-15, 17, 18, & 20-22.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 & 22 are rejected under 35 U.S.C. 103 as being unpatentable over Sun (US 20230087367) in view of Ganesan (US 20140217579) and further in view of Wang (US 20230061167).
Regarding Claim 1, Sun (see, e.g., fig. 3), shows a microelectronic assembly, comprising:
a package substrate 104-1, 110, 148-1, & 148-2 (see, e.g., para.0038);
an integrated circuit (IC) die 114-2 (see, e.g., para.0038) coupled to a package-substrate surface (top surface of 148-2, see, e.g., annotated figure 1) of the package substrate by interconnects,
the interconnects comprising solder 130 (see, e.g., para.0032),
wherein: the interconnects further comprise
bumps 122 (see, e.g., para.) on the IC die
and bond-pads 196 (top portion of the conductive pathways 196, see, e.g., annotated figure 1) on the package-substrate surface,
with the solder coupled to the bumps and the bond-pads (see, e.g., fig. 3),
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Sun, however, fails to show
and lateral surfaces of the bumps have a coating of a material that prevents solder wicking;
and an insulator material on the package-substrate surface between the bond-pads,
wherein: for at least one interconnect of the interconnects,
an insulator surface of the insulator material facing the IC die is located between
a first bump surface of a corresponding bump facing the package substrate
and a second bump surface of the corresponding bump facing the IC die,
along a direction orthogonal to the package-substrate surface.
Ganesan (see, e.g., fig. 2, para.0023), in a similar device to Sun, teaches
and lateral surfaces of the bumps 114 have a coating 122 of a material that prevents solder wicking;
Ganesan teaches the coating 122 prevents solder wetting after reflowing the bumps.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the coating of Ganesan in the device of Sun, to prevent solder wetting after reflow.
Sun, in view of Ganesan, however, fails to show
and an insulator material on the package-substrate surface between the bond-pads,
wherein: for at least one interconnect of the interconnects,
an insulator surface of the insulator material facing the IC die is located between
a first bump surface of a corresponding bump facing the package substrate
and a second bump surface of the corresponding bump facing the IC die,
along a direction orthogonal to the package-substrate surface.
Wang (see, e.g., fig. 2b, para.0042), in a similar device to Sun, in view of Ganesan, shows a configuration wherein
and an insulator material 108 (see, e.g., para.0042) on the package-substrate surface (surface of 101) horizontally between the bond-pads 101c,
Wang (see, e.g., para.00) states the insulator material 108, a solder resist structure, between conductive interconnect structures (101c, 103, & 106c) would limit bridging or shorting of the conductive interconnect structures. The insulator material 108 of Wang is incorporated into the device of Sun, in view of Ganesan.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the insulator material of Wang in the device of Sun, in view of Ganesan, because the combination would limit bridging or shorting between conductive interconnect structures.
The combination of Sun, in view of Ganesan and further in view of Wang, teaches
wherein: for at least one interconnect of the interconnects,
an insulator surface (topmost surface) of the insulator material 108 facing the IC die 114-2 is located between (see, e.g., annotated figure 2)
a first bump surface (bottommost surface) of a corresponding bump 122 facing the package substrate
and a second bump surface (topmost surface) of the corresponding bump 122 facing the IC die 114-2,
along a direction (vertical direction) orthogonal to the package-substrate surface.
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Regarding Claim 2, Sun (see, e.g., para.0032), in view of Ganesan and further in view of Wang, shows the microelectronic assembly of claim 1,
wherein the solder 130 is one of lead solder or lead-free solder (see, e.g., para.0032).
Regarding Claim 3, Sun, in view of Ganesan (see, e.g., para.0019, para.0025) and further in view of Wang, shows the microelectronic assembly of claim 2,
wherein the coating 122 on the bumps is a compound comprising silicon and nitrogen (see, e.g., para.0019, para.0025).
Regarding Claim 4, Sun, in view of Ganesan and further in view of Wang, shows the microelectronic assembly of claim 1,
wherein: the bumps 122 on the IC die 114-2 protrude from a die surface (bottommost surface of 114-2, see, e.g., annotated figure 3) of the IC die.
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Regarding Claim 5, Sun (see, e.g., fig. 3, para.0030), in view of Ganesan and further in view of Wang, shows the microelectronic assembly of claim 1, further comprising
an underfill 127 (see, e.g., para.0030) between the IC die and the package substrate around the interconnects (see, e.g., fig. 3).
Regarding Claim 6, Sun, in view of Ganesan and further in view of Wang (see, e.g., para.0042), shows the microelectronic assembly of claim 1,
wherein the insulator material 108 comprises solder resist (see, e.g., para.0042).
Regarding Claim 7, Sun, in view of Ganesan and further in view of Wang, shows the microelectronic assembly of claim 1,
wherein the bond-pads (top portions of 196) are in openings in the insulator material (see, e.g., annotated figure 4).
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Regarding Claim 8, Sun (see, e.g., fig. 3, para.0020, para.0024, para.0026), in view of Ganesan and further in view of Wang, shows the microelectronic assembly of claim 1,
wherein: the interconnects comprise first interconnects and second interconnects,
the first interconnects conductively couple the IC die to a through-dielectric via (TDV) 152 (see, e.g., fig. 3, para.0020, para.0024) in the package substrate,
and the second interconnects conductively couple the IC die to a bridge die 114-1 (see, e.g., para.0026) in the package substrate.
Regarding Claim 22, Sun, in view of Ganesan and further in view of Wang, shows the microelectronic assembly of claim 1,
wherein: the bumps comprise
a first bump 122 (hereinafter “122a”)
and a second bump 122 (hereinafter “122b”),
a first portion 108c of the insulator material is between the first bump and the second bump,
and a second portion of the solder 130 (see, e.g., annotated figure 5) is between a lateral surface of the first bump and the first portion of the insulator material (see, e.g., annotated figure 5).
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Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Sun (US 20230087367) in view of Ganesan (US 20140217579) & Wang (US 20230061167) and further in view of Williamson (US 20200251436).
Regarding Claim 21, Sun, in view of Ganesan & Wang, shows the microelectronic assembly of claim 1,
wherein: the bond-pads comprise:
a first bond-pad 196 (top portion, hereinafter “196a”)
and a second bond-pad adjacent to the first bond-pad 196 (top portion, hereinafter “196b”),
a first portion 108a of the insulator material 108 is between the first bond-pad 196a and the second bond-pad 196b (see, e.g., annotated figure 6),
Sun, in view of Ganesan & Wang, however, fails to show
and a second portion of the solder is between a lateral surface of the first bond-pad and the first portion of the insulator material.
Williamson (see, e.g., fig. 5b), in a similar device to Sun, in view of Ganesan & Wang, teaches
and a second portion of the solder 511 is between a lateral surface (sidewall surface) of the first bond-pad 504 and a surrounding layer 518.
Williamson (see, e.g., para.0040) teaches the solder 511 flowing over a bonding pad 511 covering the sidewalls of a bonding pad 504 between the bonding pad and a surrounding layer 518 would form reliable solder joints and prevent solder wicking and solder bridges.
The configuration of flowing the solder to cover the sidewalls of the bonding pad is incorporated into the device of Sun, in view of Ganesan & Wang.
Sun, in view of Ganesan & Wang and further in view of Williamson, shows
and a second portion of the solder 130 is between a lateral surface (hereinafter “196s”) of the first bond-pad 196a and the first portion 108a of the insulator material 108 (see, e.g., annotated figure 6).
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It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Williamson in the device Sun, in view of Ganesan & Wang, to form reliable solder joints and prevent solder wicking and solder bridges.
Claims 9-14, 15, 17, & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sun (US 20230087367) in view of Williamson (US 20200251436).
Regarding Claim 9, Sun (see, e.g., fig. 3) shows a package substrate, comprising:
a core 104-1 (see, e.g., para.0026-0027) comprising
a first organic dielectric material 133 (see following paragraph)
and TDVs 152 (see, e.g., para.0020) in the first organic dielectric material;
a first layer 148-2 (see, e.g., para.0048) comprising
a second organic dielectric material (organic polymeric dielectric, see, e.g., para.0038)
and a conductive bond-pad (top portion of 196, hereinafter “196b”, see, e.g., annotated figure 7);
solder 130 (see, e.g., para.0032) is on the conductive bond-pad
Sun (see, e.g., fig. 1, para.0027) states first layer 104-1, interpreted as the core, is formed of an insulating material 133, made of an organic dielectric material, and “conductive pillars 152 may be embedded in the insulating material 133 in the first layer 104-1.” The insulating material 133 is interpreted as the first organic dielectric material.
Sun (see, e.g., para.0036) states “Many of the elements of the microelectronic assembly 100 of FIG. 1 are included in other ones of the accompanying drawings; the discussion of these elements is not repeated when discussing these drawings, and any of these elements may take any of the forms disclosed herein”
Therefore, the insulating material 133 described in the embodiment of fig. 1 is also present in the embodiment of fig. 3 as the first organic dielectric material, since both embodiments show the core 104-1.
Sun, however, fails to show
and the conductive bond-pad of a first diameter;
and a second layer on a first surface of the package substrate,
the second layer comprising an opening of a second diameter,
wherein:
the first layer is between the core and the second layer,
the conductive bond-pad is at an interface between the first layer and the second layer,
the conductive bond-pad is in the opening in the second layer,
the first diameter of the conductive bond-pad is smaller than the second diameter of the opening
solder is on the conductive bond-pad and in the opening,
and a second surface of the second layer facing away from the first layer is farther from the first layer than a third surface of the solder facing away from the conductive bond-pad,
along a direction orthogonal to the first surface of the package substrate.
Williamson (see, e.g., figs. 5a-b, para.0039-0040), in a similar device to Sun, teaches a configuration wherein
and the conductive bond-pad 504 of a first diameter Dpad (see, e.g., para.0039);
and a layer 518 on a first surface (top surface) of the package substrate 502,
the layer comprising an opening 517 of a second diameter Dnsmd,
wherein:
the first diameter of the conductive bond-pad is smaller than the second diameter of the opening (see, e.g., para.0039)s
the solder 511 is on the conductive bond-pad 504 and in the opening,
the conductive bond-pad is in the opening 517 in the layer 518,
Williamson teaches the configuration would allow for the solder to flow into a larger area around the conductive bond-pad 504 to form a reliable solder joint and prevent solder wicking.
The configuration of Williamson is incorporated into the device of Sun. Layer 518 is interpreted as the second layer.
The combination of Williamson, in the device of Sun, shows
wherein:
the first layer 148-2 is between the core 104-1 and the second layer 518 (see, e.g., annotated figure 7),
the conductive bond-pad is at an interface between the first layer 148-2 and the second layer 518,
the conductive bond-pad is in the opening in the second layer,
the first diameter of the conductive bond-pad is smaller than the second diameter of the opening (see, e.g., para.0039)s
the solder is on the conductive bond-pad and in the opening,
and a second surface of the second layer 518 facing away from the first layer 148-2 is farther from the first layer than a third surface of the solder (surface of 511 in direct contact with conductive bond pad, see, e.g., annotated figure 7) facing away from the conductive bond-pad,
along a direction (vertical direction) orthogonal to the first surface of the package substrate.
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It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Williamson in the device Sun to form reliable solder joints and prevent solder wicking and solder bridges.
Regarding Claim 10, Sun, in view of Williamson, shows the package substrate of claim 9, further comprising
a plurality of bond-pads (multiple top portions of 196b) and corresponding openings,
wherein some bond-pads are larger than other bond-pads (see, e.g., annotated figure 8).
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Regarding Claim 11, Sun (see, e.g., fig. 3, para.0038), in view of Williamson, shows the package substrate of claim 10,
wherein: the package substrate is coupled to an IC die 114-2 (see, e.g., fig. 3, para.0038) by the solder on individual bond-pads in the plurality of bond-pads,
the solder 130 conductively couples the individual bond-pads (some pads of 196b) to corresponding bumps 122 (see, e.g., annotated figure 8, para.0038) on the IC die 114-2,
and for at least one bond-pad of the individual bond-pads (one pad of multiple 196b),
the solder covers a lateral surface (130 sidewall) of the at least one bond-pad (196b sidewall )in a space between the at least one bond-pad and a sidewall of a corresponding opening (see, e.g., annotated figure 8).
Regarding Claim 12, Sun, in view of Williamson, shows the package substrate of claim 11,
wherein: a fourth surface of the solder (lateral sidewall of the solder in contact with sidewall of the bond pad) is between the lateral surface of the at least one bond-pad and the sidewall of the corresponding opening (see, e.g., annotated figure 8).
Regarding Claim 13, Sun (see, e.g., para.0027), in view of Williamson, shows the package substrate of claim 9,
wherein: the first organic dielectric material 133 comprises mold compound (“mold material, such as an organic polymer”, see, e.g., para.0027),
and the second organic dielectric material comprises polyimide or buildup film (can be either the polyimide or the buildup film, see, e.g., para.0038).
Regarding Claim 14, Sun (see, e.g., fig. 3, para.0026), in view of Williamson, shows the package substrate of claim 9, further comprising
a bridge die 114-1 (see, e.g., para.0026) in the core 104-1 (see, e.g., fig. 3),
wherein the TDVs are around the bridge die (TDVs 152 to the left and right of 114-1, see, e.g., fig. 3).
Regarding Claim 15, Sun (see, e.g., fig. 3) shows a package substrate, comprising:
a core 104-1 (see, e.g., para.0026-0027) comprising
a first organic dielectric material 133 (see following paragraph)
and TDVs 152 (see, e.g., para.0020) in the first organic dielectric material;
a first layer 148-2 (see, e.g., para.0048) comprising
a second organic dielectric material (organic polymer dielectric, see, e.g., para.0038)
and a conductive bond-pad (top portion of 196, hereinafter “196b”, see, e.g., annotated figure 9);
solder 130 (see, e.g., para.0032) is on the conductive bond-pad
Sun (see, e.g., fig. 1, para.0027) states first layer 104-1, interpreted as the core, is formed of an insulating material 133, made of an organic dielectric material, and “conductive pillars 152 may be embedded in the insulating material 133 in the first layer 104-1.” The insulating material 133 is interpreted as the first organic dielectric material.
Sun (see, e.g., para.0036) states “Many of the elements of the microelectronic assembly 100 of FIG. 1 are included in other ones of the accompanying drawings; the discussion of these elements is not repeated when discussing these drawings, and any of these elements may take any of the forms disclosed herein”
Therefore, the insulating material 133 described in the embodiment of fig. 1 is also present in the embodiment of fig. 3 as the first organic dielectric material, since both embodiments show the core 104-1.
Sun, however, fails to show
and the conductive bond-pad of a first diameter;
and a second layer on a first surface of the package substrate,
the second layer comprising an opening of a second diameter,
wherein:
the first layer is between the core and the second layer,
the conductive bond-pad is at an interface between the first layer and the second layer,
the conductive bond-pad is in the opening in the second layer,
the first diameter of the conductive bond-pad is larger than the second diameter of the opening
solder is on the conductive bond-pad and in the opening,
and a second surface of the second layer facing away from the first layer is farther from the first layer than a third surface of the solder facing away from the conductive bond-pad, along a direction orthogonal to the first surface of the package substrate.
Williamson (see, e.g., figs. 3a-b, para.0015), in a similar device to Sun, teaches a solder mask 318 over a substrate 302 between conductive bond-pads 304 and solders 311 would isolate and prevent shorting between adjacent conductive bond-pads and solders.
The solder mask 318 of Williamson is incorporated into the device of Sun as the second layer to isolate and prevent shorting between adjacent conductive bond-pads and solders.
Sun, in view of Williamson (see, e.g., fig. 3, para.0029), shows
and the conductive bond-pad 196b of a first diameter Dpad (the diameter of Williamson bond pad 304, see, e.g., para.0039);
and a second layer 318 on a first surface (topmost surface of 148-2) of the package substrate,
the second layer comprising an opening (hereinafter “318O” see, e.g., annotated figure 9) of a second diameter Dnsmd (second diameter corresponds to the position of opening 318O, see, e.g., annotated figure 9)
wherein:
the first layer 148-2 is between the core 104-1 and the second layer 318 (see, e.g., annotated figure 9),
the conductive bond-pad is at an interface (in opening 318O) between the first layer 148-2 and the second layer 318,
the conductive bond-pad 196b is in the opening 318O in the second layer,
the first diameter of the conductive bond-pad is larger than the second diameter of the opening (see, e.g., para.0029)s
the solder 130 is on the conductive bond-pad 196b and in the opening 318O,
and a second surface of the second layer facing away from the first layer is farther from the first layer than a third surface of the solder facing away from the conductive bond-pad, along a direction orthogonal to the first surface of the package substrate.
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It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the solder mask 318 of Williamson device of Sun as the second layer to isolate and prevent shorting between adjacent conductive bond-pads and solders.
Regarding Claim 17, Sun, in view of Williamson, shows the package substrate of claim 15, further comprising:
a plurality of conductive bond-pads (multiple top portions of 196b) and corresponding openings (hereinafter “318Oc”, each top portion 196b inherits a corresponding opening 318Oc, as modified by Williamson),
wherein: the package substrate is coupled to an IC die 114-2 (see, e.g., para.0038) by the solder on individual conductive bond-pads in of the plurality of conductive bond-pads (see, e.g., annotated figure 9),
the solder conductively couples the individual conductive bond-pads to corresponding bumps on the IC die,
and for at least one opening of the corresponding openings, the solder partially covers a lateral surface (sidewall surface in the opening directly in contact with solder as modified by Williamson, see, e.g., annotated figure 9) of the at least one opening.
Regarding Claim 20, Sun (see. e.g., fig. 3, para.0026), in view of Williamson, shows the package substrate of claim 15, further comprising
a bridge die 114-1 (see, e.g., para.0026) in the core,
wherein the TDVs (TDVs 152 to the left and right of 114-1, see, e.g., fig. 3) are around the bridge die.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Sun (US 20230087367) in view of Williamson (US 20200251436) and further in view of Ganesan (US 20140217579).
Regarding Claim 18, Sun, in view of Williamson, shows the package substrate of claim 17,
wherein lateral surfaces of the corresponding bumps are coated with a material that inhibits solder wicking.
Ganesan (see, e.g., fig. 2, para.0023), in a similar device to Sun, in view of Williamson, teaches
and lateral surfaces of the bumps 114 have a coating 122 of a material that inhibits solder wicking;
Ganesan teaches the coating 122 prevents solder wetting after reflowing the bumps.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the coating of Ganesan in the device of Sun, in view of Williamson, to prevent solder wetting after reflow.
Response to Arguments
Applicant’s arguments, see pages 7-9, filed 05/11/2026, with respect to the rejection(s) of claim(s) 1-15, 17, 18, & 20-22 under 35 U.S.C. 102 & 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Sun, Ganesan, Wang, Williamson .
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2818
Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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