DETAILED ACTION
This Office action responds to the application filed on 10/07/2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election with traverse of Species 1, in the reply filed on 12/01/2025, is acknowledged. The traversal is on the grounds that Claims 1-8 are generic to all species. Examiner concedes, and the restriction filed on10/17/2025 is withdrawn. Applicant cancels claims 16 & 19. Claims 1-15, 17, 18, & 20-22 will be examined in this Office action.
Claim Rejections - 35 USC § 102 & 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 21, & 22 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma (US 20230209800) in view of Ganesan (US 20140217579).
Regarding Claim 1, Sharma (see, e.g., fig. 9, annotated figure 9, para.0059) shows a microelectronic assembly 900, comprising:
a package substrate 902 (see, e.g., para.0059);
and an integrated circuit (IC) die 930 coupled to a surface of the package substrate 902 (surface near 913, see, e.g., annotated figure 9) by first interconnects 932a, 914, & 912 (see, e.g., annotated figure 9) and second interconnects 932b, 924, & 922 (see, e.g., annotated figure 9),
the first interconnects and the second interconnects comprising solder 914 & 924,
wherein: the first interconnects are larger than the second interconnects (see, e.g., fig. 9),
the first interconnects and the second interconnects further comprise
bumps 932a & 932b on the IC die and bond-pads 912 & 922 on the surface of the package substrate,
with the solder coupled to the bumps and the bond-pads (see, e.g., fig. 9),
and an insulator material 913 (solder resist) on the surface of the package substrate between the bond-pads.
Sharma, however, fails to show
lateral surfaces of the bumps have a coating of a material that prevents solder wicking
Ganesan (see, e.g., fig. 2, para.0023), in a similar device to Sharma, teaches lateral surface of bumps 112 having a coating, would prevent solder wetting after reflow.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the coating of Ganesan in the device of Sharma, to prevent solder wetting after reflow.
Regarding Claim 2, Sharma (see, e.g., para.0059), in view of Ganesan, shows the microelectronic assembly of claim 1,
wherein the solder is one of lead solder or lead-free solder.
Regarding Claim 3, Sharma, in view of Ganesan (see, e.g., fig. 3d, para.0025), shows the microelectronic assembly of claim 2,
wherein the coating on the bumps is a compound comprising silicon and nitrogen.
Ganesan (see, e.g., fig. 3d, para.0025) states that the coating on the bumps 214 can be silicon nitride.
Regarding Claim 4, Sharma (see, e.g., annotated figure 9), in view of Ganesan, shows the microelectronic assembly of claim 1,
wherein the surface of the package substrate is a first surface (see, e.g., annotated figure 9),
and wherein the bumps on the IC die protrude from a second surface of the IC die 930 near 932a & 932b (see, e.g., annotated figure 9).
Regarding Claim 5, Sharma (see, e.g., fig. 9, para.0060), in view of Ganesan, shows the microelectronic assembly of claim 1, further comprising
an underfill 940 (see, e.g., para.0060) between the IC die and the package substrate around the first interconnects and the second interconnects.
Regarding Claim 6, Sharma (see, e.g., fig. 9, para.0059), in view of Ganesan, shows the microelectronic assembly of claim 1,
wherein the insulator material comprises solder resist (see, e.g., para.0059).
Regarding Claim 7, Sharma (see, e.g., fig. 9, para.0059), in view of Ganesan, shows the microelectronic assembly of claim 1,
wherein the bond-pads 912 & 914 are in openings in the insulator material 913.
Regarding Claim 8, Sharma (see, e.g., fig. 9, para.0059-0060), in view of Ganesan, shows the microelectronic assembly of claim 1,
wherein: the first interconnects conductively couple the IC die to a through-dielectric via (TDV) 910 in the package substrate,
and the second interconnects conductively couple the IC die to a bridge die 904 (see, e.g., para.0059) in the package substrate.
Regarding Claim 21, Sharma (see, e.g., fig. 9, annotated figure 9, para.0059), in view of Ganesan, shows the microelectronic assembly of claim 1,
wherein: the bond-pads 912 & 922 comprise:
a first bond-pad 912 and a second bond-pad 922 adjacent to the first bond-pad,
a first portion of the insulator material 913 (see, e.g., annotated figure 9) is between the first bond-pad 912 and the second bond-pad 922,
and a second portion of the solder is between a lateral surface (left) of the first bond-pad and the first portion of the insulator material 913 (see, e.g., annotated figure 9).
Regarding Claim 22, Sharma (see, e.g., fig. 9, annotated figure 9, para.0059), in view of Ganesan, shows the microelectronic assembly of claim 1,
wherein: the bumps comprise a first bump 914 of first interconnect and a second bump 914 of second interconnect,
a first portion of the insulator material 913 is between the first bump and the second bump,
and a second portion of the solder is between a lateral surface of the first bump and the first portion of the insulator material (the same rejection for claim 21 applies, see, e.g., annotated figure 9).
Claims 9, 10, 13, & 14 are rejected under 35 U.S.C. 103 as being unpatentable over Huang T (US 20200381325) in view of Huang K (US 20190067231).
Regarding Claim 9, Huang T (see, e.g., fig. 7) shows a package substrate 210, comprising:
a core 130 (see, e.g., fig. 15) comprising a first organic dielectric material (epoxy, see, e.g., para.0039) and TDVs 116 (see, e.g., para.0039) in the first organic dielectric material;
a first layer 112 comprising a second organic dielectric material (polyimide, see, e.g., para.0023) and a conductive bond-pad 110 (see, e.g., para.0022)
and a second layer 108 (see, e.g., para.0021) on a surface of the package substrate (see, e.g., annotated figure 17),
the second layer comprising an opening (see, e.g., fig.17) ,
wherein: the first layer 112 is between the core 130 and the second layer 108 (see, e.g., fig. 17),
the conductive bond-pad is at an interface between the first layer and the second layer,
the conductive bond-pad is in the opening in the second layer,
Also, Huang T, however, fails to show
and the conductive bond-pad of a first diameter;
the second layer comprising the opening of a second diameter,
and the first diameter of the conductive bond-pad is smaller than the second diameter of the opening.
Huang K (see, e.g., fig. 2d, para.0023-0024), in a similar device to Huang T, teaches a configuration wherein the diameter of the opening 161 is wider than the diameter of the bond pad 121 would be an obvious configuration for the bond opening and would help avoid forming a cold joint and bridging.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Huang K in the device of Huang T as an obvious configuration for the bond opening and to help avoid forming a cold joint and bridging.
Regarding Claim 10, Huang T, in view of Huang K (see, e.g., fig. 2d, para.0023), shows the package substrate of claim 9, further comprising
a plurality of bond-pads 110 (multiple elements in 100a & 100b) and corresponding openings,
wherein some bond-pads are larger than other bond-pads.
Huang K (see, e.g., fig. 2d, para.0023) states that bond pads having different sizes would be beneficial by preventing a cold join and bridging.
Regarding Claim 13, Huang T (see, e.g., para.0023, para.0039), in view of Huang K, shows the package substrate of claim 9,
wherein: the first organic dielectric material comprises mold compound (epoxy, see, e.g., para.0039),
and the second organic dielectric material comprises polyimide or buildup film (polyimide, see, e.g., para.0023).
Regarding Claim 14, Huang T (see, e.g., fig. 17), in view of Huang K, shows the package substrate of claim 9, further comprising
a bridge die 50 (see, e.g., para.0009) in the core,
wherein the TDVs 116 are around the bridge die.
Claims 11 & 12 are rejected under 35 U.S.C. 103 as being unpatentable over Huang T (US 20200381325) in view of Huang K (US 20190067231) and further in view of Williamson (US 20200251436).
Regarding Claim 11, Huang, in view of Huang K, shows package substrate of claim 10,
wherein: the package substrate is coupled to an IC die 930 by solder 914 & 924 on individual bond-pads in the plurality of bond-pads,
the solder conductively couples the individual bond-pads to corresponding bumps 932a & 932b on the IC die,
Huang, in view of Huang K, however, fails to show
and the solder covers lateral surfaces of the individual bond-pads in a space between the individual bond-pads and the corresponding openings.
Williamson (see, e.g., fig. 5d, para.0040), in a device similar to Huang T, in view of Huang K, teaches a configuration wherein the solder covering lateral surfaces of the individual bond-pads in a space between the individual bond-pads and the corresponding openings would allow solder to flow into a larger area around the pads to prevent solder wicking and bridging.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Williamson in the device of Huang T, in view of Huang K, to allow solder to flow into a larger area around the pads to prevent solder wicking and bridging.
Regarding Claim 12, Huang T, in view of Huang K and further in view of Williamson, shows the package substrate of claim 11,
wherein the surface of the package substrate is a first surface (near 108, see, e.g., fig. 17),
and wherein a second surface of the solder is between the lateral surfaces of the individual bond-pads and the corresponding openings.
Williamson addresses why the second surface of the solder between lateral surfaces would be beneficial, see paragraphs above.
Claims 15 & 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang T (US 20200381325).
Regarding Claim 15, Huang T (see, e.g., fig. 17) shows a package substrate, comprising:
a core 130 (see, e.g., fig. 15) comprising a first organic dielectric material (epoxy, see, e.g., para.0039) and TDVs 116 (see, e.g., para.0039) in the first organic dielectric material;
a first layer 112 comprising a second organic dielectric material (polyimide, see, e.g., para.0023) and a conductive bond-pad 110 (see, e.g., para.0022) of a first diameter;
and a second layer 108 (see, e.g., para.0021) on a surface of the package substrate (see, e.g. fig. 17),
the second layer comprising an opening (see, e.g., fig.17) of a second diameter,
wherein: the first layer 112 is between the core 130 and the second layer 108 (see, e.g., fig. 17),
the conductive bond-pad is at an interface between the first layer and the second layer,
the conductive bond-pad is in the opening in the second layer,
and the first diameter of the conductive bond-pad 110 is larger than the second diameter of the opening (see, e.g., fig. 17).
Regarding Claim 20, Huang T (see, e.g., fig. 17), shows package substrate of claim 15, further comprising
a bridge die 50 (see, e.g., para.009) in the core,
wherein the TDVs 116 are around the bridge die.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Huang T (US 20200381325) in view of Williamson (US 20200251436).
Regarding Claim 17, Huang T (see, e.g., fig. 17) shows the package substrate of claim 15, further comprising:
a plurality of bond-pads 110 and corresponding openings,
wherein: the package substrate is coupled to an IC die 200 & 204a (see, e.g., para.0059) by solder 160 (see, e.g., para.0062) on individual bond-pads in the plurality of bond-pads,
the solder conductively couples the individual bond-pads to corresponding bumps 210 on the IC die,
Huang T, however, fails to show
and the solder partially covers lateral surfaces of the corresponding openings without overflowing out of the corresponding openings in the second layer
Williamson (see, e.g., fig. 5d, para.0040), in a device similar to Huang T, teaches a configuration wherein solder partially covering lateral surfaces of the corresponding openings without overflowing out of the corresponding openings in the second layer would allow solder to flow into a larger area around the pads to prevent solder wicking and bridging.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Williamson in the device of Huang T, to allow solder to flow into a larger area around the pads to prevent solder wicking and bridging.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Huang T (US 20200381325) in view of Williamson (US 20200251436) and further in view of Ganesan (US 20140217579).
Regarding Claim 18, Huang T, in view of Williamson, shows the package substrate of claim 17,
Huang T, in view of Williamson, however, fails to show
wherein the lateral surfaces of the corresponding bumps are coated with a material that inhibit solder wicking.
Ganesan (see, e.g., fig. 2, para.0023), in a similar device to Sharma, teaches lateral surface of bumps 112 having a coating, would prevent solder wetting after reflow.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the coating of Ganesan in the device of Huang T, in view of Williamson, to prevent solder wetting after reflow.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2814
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814