DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. US 2021/0020574 A1 in view of Kikuchi et al. US 2014/0077391 A1.
Regarding claims 1-5, 7-9 and 13-15, Yu discloses:
A semiconductor package (Figs. 7 and 19), comprising:
a bottom package comprising a substrate (58) and a semiconductor die (26 including 128, 130) mounted on a top surface of the substrate, wherein the semiconductor die has an active surface (top) and a rear surface (bottom) coupled to the top surface of the substrate, wherein the semiconductor die comprises through silicon vias (134), and wherein the semiconductor die and the top surface of the substrate are encapsulated by a first molding compound (38);
a top package (46A) stacked on the bottom package, wherein the top package comprises a memory component (para 0033; High Bandwidth Memory stack); and
a middle re-distribution layer (RDL) structure (40) disposed between the top package and the bottom package, wherein the active surface of the semiconductor die is directly connected to the middle RDL structure through connecting elements (28), wherein the middle RDL structure comprises dielectric layers (44) and interconnect structures (42), wherein the memory component is electrically connected to the substrate via the interconnect structures of the middle RDL structure and the through silicon vias of the semiconductor die (Fig. 7 para 0042; and Fig. 19 para 0055).
Yu does not disclose:
wherein a center of the memory component is aligned with a center of the semiconductor die in a cross-sectional view.
Kikuchi discloses a publication from a similar field of endeavor in which:
wherein a center of the memory component (MC) is aligned with a center of the semiconductor die (LC) in a cross-sectional view (MC aligned within the center of LC with intervening RDC) (Fig. 4).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the semiconductor package configuration of Kikuchi as an alternative design criterion where one overlying component is required in the semiconductor package thereby reducing the scaling of the overall package structure.
(claim 2) Yu: para 0020; “The respective circuits in bridge die 26 may include memory circuits, logic circuits, and/or the like.”
(claim 3) Yu: a re-distribution layer (58 redistribution structure).
(claim 4) Yu: 62 shown with connection and ball pads (top and bottom pads) and intervening conductive traces (middle trace) (para 0038 in view of similar element 42 in para 0032).
(claim 5) Yu: a plurality of solder balls (64 electrical connectors para 0038).
(claim 7) Yu: micro-bumps (28 metal pillars para 0023).
(claim 8) Yu: an underfill material (29 polymer layer para 0025).
(claim 9) Yu: through mold vias in first molding compound (24 within 38).
(claim 13) Yu: a second molding compound (52 encapsulant para 0035).
(claim 14) Yu: inside edge of 46A is aligned with the center of 26.
(claim 15) Yu: sidewall of top package (52) is vertically flush with sidewall of bottom package (38).
Regarding claim 6, although Yu does not specifically disclose “wherein power and ground to the memory component is provided through the through silicon vias”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand that power delivery would be occur through through-vias 134 of Yu from the external connectors 63 since Yu notes in para 0042 that the through-vias function to interconnect the RDL layers 42 and 62.
Regarding claims 10-12, Yu discloses:
(claim 10) wherein the memory component is a High-Bandwidth Memory (HBM) (para 0033; High Bandwidth Memory stack).
Although Yu does not specifically disclose “(claim 10) multiple DRAM dies are stacked on one another, wherein the stacked DRAM dies are vertically interconnected; (claim 11) wherein the memory component further comprises a DRAM base; and (claim 12) wherein the DRAM base is electrically coupled to the middle RDL structure”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine from the similar claimed stacked structure and the disclosure of Yu para 0033 that DRAM devices are commonly employed memory devices within stacked memory semiconductor packages. Furthermore, although Yu does not specifically disclose “wherein power or ground signals are transmitted to the solder balls on the bottom surface of the substrate via a conductive path comprised of the interconnect structures of the middle RDL structure, the connecting elements, the through silicon vias of the semiconductor die, and the conductive traces of the substrate”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand that power delivery would be occur through through-vias 134 of Yu from the external connectors 63 since Yu notes in para 0042 that the through-vias function to interconnect the RDL layers 42 and 62.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on (571) 270-30423042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERROL V FERNANDES/Primary Examiner, AU 2893
Prosecution Insights