DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species I Fig. 1, claims 1-15, in the reply filed on 10/14/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-9 and 13-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. US 2021/0020574 A1.
Regarding claims 1-5, 7-9 and 13-15, Yu discloses:
A semiconductor package (Figs. 7 and 19), comprising:
a bottom package comprising a substrate (58) and a semiconductor die (26 including 128, 130) mounted on a top surface of the substrate, wherein the semiconductor die has an active surface (top) and a rear surface (bottom) coupled to the top surface of the substrate, wherein the semiconductor die comprises through silicon vias (134), and wherein the semiconductor die and the top surface of the substrate are encapsulated by a first molding compound (38);
a top package (46A) stacked on the bottom package, wherein the top package comprises a memory component (para 0033; High Bandwidth Memory stack); and
a middle re-distribution layer (RDL) structure (40) disposed between the top package and the bottom package, wherein the active surface of the semiconductor die is directly connected to the middle RDL structure through connecting elements (28), wherein the middle RDL structure comprises dielectric layers (44) and interconnect structures (42), wherein the memory component is electrically connected to the substrate via the interconnect structures of the middle RDL structure and the through silicon vias of the semiconductor die (Fig. 7 para 0042; and Fig. 19 para 0055).
(claim 2) para 0020; “The respective circuits in bridge die 26 may include memory circuits, logic circuits, and/or the like.”
(claim 3) a re-distribution layer (58 redistribution structure).
(claim 4) 62 shown with connection and ball pads (top and bottom pads) and intervening conductive traces (middle trace) (para 0038 in view of similar element 42 in para 0032).
(claim 5) a plurality of solder balls (64 electrical connectors para 0038).
(claim 7) micro-bumps (28 metal pillars para 0023).
(claim 8) an underfill material (29 polymer layer para 0025).
(claim 9) through mold vias in first molding compound (24 within 38).
(claim 13) a second molding compound (52 encapsulant para 0035).
(claim 14) inside edge of 46A is aligned with the center of 26.
(claim 15) sidewall of top package (52) is vertically flush with sidewall of bottom package (38).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. US 2021/0020574 A1.
Regarding claim 6, although Yu does not specifically disclose “wherein power and ground to the memory component is provided through the through silicon vias”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand that power delivery would be occur through through-vias 134 of Yu from the external connectors 63 since Yu notes in para 0042 that the through-vias function to interconnect the RDL layers 42 and 62.
Regarding claims 10-12, Yu discloses:
(claim 10) wherein the memory component is a High-Bandwidth Memory (HBM) (para 0033; High Bandwidth Memory stack).
Although Yu does not specifically disclose “(claim 10) multiple DRAM dies are stacked on one another, wherein the stacked DRAM dies are vertically interconnected; (claim 11) wherein the memory component further comprises a DRAM base; and (claim 12) wherein the DRAM base is electrically coupled to the middle RDL structure”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine from the similar claimed stacked structure and the disclosure of Yu para 0033 that DRAM devices are commonly employed memory devices within stacked memory semiconductor packages. Furthermore, although Yu does not specifically disclose “wherein power or ground signals are transmitted to the solder balls on the bottom surface of the substrate via a conductive path comprised of the interconnect structures of the middle RDL structure, the connecting elements, the through silicon vias of the semiconductor die, and the conductive traces of the substrate”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand that power delivery would be occur through through-vias 134 of Yu from the external connectors 63 since Yu notes in para 0042 that the through-vias function to interconnect the RDL layers 42 and 62.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
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/ERROL V FERNANDES/Primary Examiner, AU 2893