Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant’s arguments, filed 8/7/25, with respect to the rejection(s) of claim(s) 12-20 under 35 U.S.C. 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of.
Information Disclosure Statement
The information disclosure statements filed 8/7/25 have been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 12, 14-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. Patent Publication No. 2009/0039371) in view of Gruber et al. (U.S. Patent Publication No. 2021/0143108) or Inoue (U.S. Patent Publication No. 2015/0214183).
Referring to figures 1-6, Kim et al. teaches a semiconductor device, comprising:
a semiconductor chip including a first semiconductor layer of a first conductivity type (140) and a second semiconductor layer of a second conductivity type (160);
a first electrode (180) provided on a back surface of the semiconductor at a side opposite to a front surface of the semiconductor chip, a second electrode (175) provided on the front surface of the semiconductor, the second semiconductor layer (160) being provided between the first semiconductor layer (140) and the second electrode (175, see figure 2).
However, the reference does not clearly teach the first electrode has a plate-like shape and extends beyond an outer edge of the back surface of the semiconductor chip in all directions in a plane.
Gruber et al. teaches a semiconductor device having the first electrode (120) has a plate-like shape and extends beyond an outer edge of the back surface of the semiconductor chip in all directions in a plane (see figure 2, meeting claim 12); the extension of the first electrode extends in a direction parallel to the back surface of the semiconductor chip (see figure 2, meeting claim 17). Or Inoue teaches a semiconductor device having the first electrode (1) has a plate-like shape and extends beyond an outer edge of the back surface of the semiconductor chip in all directions in a plane (see figure 2), the extension of the first electrode extends in a direction parallel to the back surface of the semiconductor chip (see figure 2, meeting claim 17).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would a semiconductor device having the first electrode (120) has a plate-like shape and extends beyond an outer edge of the back surface of the semiconductor chip in all directions in a plane in Kim et al. as taught by Gruber et al. or Inoue because it is known in the semiconductor art to enhance device performance.
Regarding to claim 14, the extension of the first electrode (180) surrounds a region of the first electrode, the region contacting the back surface of the semiconductor chip (110/120/130/140/150/160/170, see figure 2).
Regarding to claim 15, the first electrode (180) contacts an entirety of the back surface of the semiconductor chip (110/120/130/140/150/160/170, see figure 2).
Regarding to claim 16, the first electrode (180) contacts the outer edge of the back surface of the semiconductor chip (110/120/130/140/150/160/170, see figure 2).
Regarding to claim 18, the first electrode includes (180) a first surface and a second surface, the first surface contacting the back surface of the semiconductor chip (110/120/130/140/150/160/170, see figure 2), the second surface being at a side opposite to the first surface and having a first surface area, the back surface of the semiconductor chip has a second surface area, and the front surface of the semiconductor chip has a third surface area, and wherein the first surface area is greater than the second surface area and the third surface area (see figure 2).
Claim(s) 12, 14-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akagi et al. (U.S. Patent Publication No. 2009/0114985) in view of Gruber et al. (U.S. Patent Publication No. 2021/0143108) or Inoue (U.S. Patent Publication No. 2015/0214183).
Referring to figures 1-26, Akagi et al. teaches a semiconductor device, comprising:
a semiconductor including a first semiconductor layer of a first conductivity type (20) and a second semiconductor layer of a second conductivity type (13);
a first electrode (21) provided on a back surface of the semiconductor at a side opposite to a front surface of the semiconductor wafer, a second electrode (18) provided on the front surface of the semiconductor, the second semiconductor layer (13) being provided between the first semiconductor layer (20) and the second electrode (18), wherein the first electrode (21) comprises an extension that extends laterally beyond an outer edge of the back surface of the semiconductor (see figure 2).
However, the reference does not clearly teach the first electrode has a plate-like shape and extends beyond an outer edge of the back surface of the semiconductor chip in all directions in a plane.
Gruber et al. teaches a semiconductor device having the first electrode (120) has a plate-like shape and extends beyond an outer edge of the back surface of the semiconductor chip in all directions in a plane (see figure 2, meeting claim 12); the extension of the first electrode extends in a direction parallel to the back surface of the semiconductor chip (see figure 2, meeting claim 17). Or Inoue teaches a semiconductor device having the first electrode (1) has a plate-like shape and extends beyond an outer edge of the back surface of the semiconductor chip in all directions in a plane (see figure 2), the extension of the first electrode extends in a direction parallel to the back surface of the semiconductor chip (see figure 2, meeting claim 17).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would a semiconductor device having the first electrode (120) has a plate-like shape and extends beyond an outer edge of the back surface of the semiconductor chip in all directions in a plane in Kim et al. as taught by Gruber et al. or Inoue because it is known in the semiconductor art to enhance device performance.
Regarding to claim 14, the extension of the first electrode (21) surrounds a region of the first electrode that contacts the back surface of the semiconductor (see figure 2).
Regarding to claim 15, the first electrode (21) contacts an entirety of the back surface of the semiconductor (see figure 2).
Regarding to claim 16, the first electrode (21) contacts the outer edge of the back surface of the semiconductor (20/13/16, see figure 2).
Regarding to claim 17, the extension of the first electrode (21) extends in a direction parallel to the back surface of the semiconductor (20/16/13, see figure 2).
Regarding to claim 18, the first electrode includes (21) a first surface and a second surface, the first surface contacting the back surface of the semiconductor (20/16/13, see figure 2), the second surface being at a side opposite to the first surface and having a first surface area, the back surface of the semiconductor has a second surface area, and the front surface of the semiconductor has a third surface area, and wherein the first surface area is greater than the second surface area and the third surface area (see figure 2).
Regarding to claim 19, a control electrode (19) provided between the first electrode (21) and the second electrode (18), the control electrode (19) being provided in the semiconductor, the control electrode (19) facing the first semiconductor layer and the second semiconductor layer with a first insulating film (32) interposed, the semiconductor further including a third semiconductor layer of the first conductivity type, the third semiconductor layer (16) being partially provided between the second electrode (18) and the second semiconductor layer (13), the third semiconductor layer contacting the first insulating film (32, see figures 13-14).
Claims 13, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. Patent Publication No. 2009/0039371) or Akagi et al. (U.S. Patent Publication No. 2009/0114985) in view of Gruber et al. (U.S. Patent Publication No. 2021/0143108) or Inoue (U.S. Patent Publication No. 2015/0214183) applied in claim(s) 12, 14-19 above.
Referring to figures 1-26, Akagi et al. teaches a semiconductor device, comprising:
a semiconductor including a first semiconductor layer of a first conductivity type (20) and a second semiconductor layer of a second conductivity type (13);
a first electrode (21) provided on a back surface of the semiconductor at a side opposite to a front surface of the semiconductor wafer, a second electrode (18) provided on the front surface of the semiconductor, the second semiconductor layer (13) being provided between the first semiconductor layer (20) and the second electrode (18), wherein the first electrode (21) comprises an extension that extends laterally beyond an outer edge of the back surface of the semiconductor (see figure 2).
However, the reference does not clearly teach the first electrode has a first surface facing the back surface of the semiconductor, a first surface area of the first surface is between about five percent and about fifteen percent larger than a second surface area of the back surface (in claim 13); the first surface area is between about five percent and about fifteen percent larger than both of the second surface area and the third surface area (in claim 20).
In re claims 13, 20, the selection of the surface areas is obvious because it is a matter of
determining optimum process condition by routine experimentation with a limited number of
species. ln re Jones, 162 USPQ 224 (CCPA 1955) (the selection of optimum ranges within prior
art general conditions is obvious) and In re Boesch, 205 USPQ 215 (CCPA 1980) (discovery of
optimum value of result effective variable in a known process is obvious). In such a situation, applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to prior art range. See M.P.E.P 2144.05 III.
In particular, Kim et al. or Akagi et al. suggest that the selection of the surface areas can be optimized (see figure 2).
Therefore, one of ordinary skill in the requisite art at the time the invention was filed would have used any specific surface area in Kim or Akagi et al. in order to optimize the process to form a desired semiconductor device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893