DETAILED ACTION
This action is responsive to the application No. 17/939,303 filed on September 07, 2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 09/09/2025 responding to the Office action mailed on 07/11/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Claim 6 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Accordingly, pending in this Office action are claims 1-12, 19-21, and newly added claims 22-26.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US 2016/0172488) in view of Chandrasekhar (US 2021/0305161).
Regarding Claim 10, Oh (see, e.g., Fig. 4D) teaches a semiconductor element comprising:
a substrate 101 comprising a trench 105, a source region 117, and a drain region 118, the source region 117 and the drain region 118 separated apart from each other by the trench 105 (see, e.g., par. 0034);
a gate insulating layer 106 covering a bottom surface and a sidewall of the trench 105 (see, e.g., par. 0034);
a gate electrode 107 comprising a barrier layer 110, a material layer 114, and a conductive layer 111/115 (see, e.g., pars. 0042, 0044, 0074, 0080); and
a capping layer 116 on the gate electrode 107 (see, e.g., par. 0042),
wherein the gate insulating layer 106 surrounds the barrier layer 110,
the barrier layer 110 is in the trench 105,
the barrier layer 110 covers a bottom surface of the gate insulating layer 106 and a lower region of a sidewall of the gate insulating layer 106,
the material layer 114 covers an upper region of the sidewall of the gate insulating layer 106 in the trench 105, and
the conductive layer 111/115 is in the trench 105 and includes a first conductive layer 111 surrounded by the barrier layer 110 and a second conductive layer 115 surrounded by the material layer 114,
wherein the barrier layer 110 does not overlap the source region 117 and the drain region 118,
the material layer 114 overlaps the source region 117 and the drain region 118, and
a material in the first conductive layer 111 is different from a material in the second conductive layer 115 (see, e.g., par. 0053).
Oh does not teach that the material layer is a two-dimensional material layer.
Chandrasekhar (see, e.g., Fig. 2), on the other hand, teaches a barrier layer comprising a two-dimensional material, such as graphene, to provide improved electrical properties and lower electromigration failures (see, e.g., par. 0043).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Oh’s device, the barrier layer comprising a two-dimensional material, as taught by Chandrasekhar, to provide improved electrical properties and lower electromigration failures.
Regarding Claim 11, Oh and Chandrasekhar teach all aspects of claim 10. Oh (see, e.g., Fig. 4D), teaches that the second conductive layer 115 comprises at least one of aluminum (Al), titanium (Ti), Chromium (Cr), gold (Au), nickel (Ni), and platinum (Pt) (see, e.g., par. 0054).
Regarding Claim 12, Oh and Chandrasekhar teach all aspects of claim 1. Chandrasekhar (see, e.g., Fig. 2), teaches that the two-dimensional material layer 214 comprises at least one of graphene, black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, and a transition metal dichalcogenide (see, e.g., par. 0029).
Claims 10, 19, 20, 23, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2016/0315088) in view of Chandrasekhar (US 2021/0305161).
Regarding Claim 10, Kang (see, e.g., Fig. 10B) teaches a semiconductor element comprising:
a substrate 301 comprising a trench 305, a source region 313, and a drain region 314, the source region 313 and the drain region 314 separated apart from each other by the trench 305 (see, e.g., par. 0149);
a gate insulating layer 306 covering a bottom surface and a sidewall of the trench 305 (see, e.g., par. 0150);
a gate electrode BG2 comprising a barrier layer 310H, a material layer 310L, and a conductive layer 307/308M (see, e.g., par. 0168); and
a capping layer 309 on the gate electrode BG2 (see, e.g., par. 0168),
wherein the gate insulating layer 306 surrounds the barrier layer 310H,
the barrier layer 310H is in the trench 305,
the barrier layer 310H covers a bottom surface of the gate insulating layer 306 and a lower region of a sidewall of the gate insulating layer 306,
the material layer 310L covers an upper region of the sidewall of the gate insulating layer 306 in the trench 305, and
the conductive layer 307/308M is in the trench 305 and includes a first conductive layer 307 surrounded by the barrier layer 310H and a second conductive layer 308M surrounded by the material layer 310L,
wherein the barrier layer 310H does not overlap the source region 313 and the drain region 314,
the material layer 310L overlaps the source region 313 and the drain region 314, and
a material in the first conductive layer 307 is different from a material in the second conductive layer 308M (see, e.g., par. 0169).
Kang does not teach that the material layer is a two-dimensional material layer.
Chandrasekhar (see, e.g., Fig. 2), on the other hand, teaches a barrier layer comprising a two-dimensional material, such as graphene, to provide improved electrical properties and lower electromigration failures (see, e.g., par. 0043).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Kang’s device, the barrier layer comprising a two-dimensional material, as taught by Chandrasekhar, to provide improved electrical properties and lower electromigration failures.
Regarding Claim 20, Kang (see, e.g., Fig. 10A) teaches a semiconductor element comprising:
a substrate 301 comprising a trench 305, a source region 313, and a drain region 314, the source region 313 and the drain region 314 separated apart from each other by the trench 305 (see, e.g., par. 0149);
a gate insulating layer 306 covering a bottom surface and a sidewall of the trench 305 (see, e.g., par. 0150);
a gate electrode BG1 comprising a lower buried portion 307M/310H and an upper buried portion 308M/310L with the gate insulating layer 306 therearound (see, e.g., par. 0165),
the lower buried portion 307M/310H filling a lower region of the trench 305, and
the upper buried portion 308M/310L being on the lower buried portion 307M/310H and filling an upper region of the trench 305; and
a capping layer 309 on the gate electrode BG1 (see, e.g., par. 0150),
wherein the lower buried portion 307M/310H comprises a barrier layer 310H and a first conductive layer 307M (see, e.g., pars. 0150, 0166),
the barrier layer 310H is in the trench 305,
the barrier layer 310H covers a bottom surface of the gate insulating layer 306 and a lower region of a sidewall of the gate insulating layer 306,
the barrier layer 310H surrounds the first conductive layer 307M,
the first conductive layer 307M fills the lower region of the trench 305, and
the lower buried portion 307M/310H does not overlap the source region 313 and the drain region 314, and
wherein the upper buried portion 308M/310L comprises a material layer 310L and a second conductive layer 308M (see, e.g., pars. 0150, 0166),
the material layer 310L is in the trench 305,
the material layer 310L covers an upper surface of the first conductive layer 307M and an upper region of the sidewall of the gate insulating layer 306,
the material layer 310L surrounds the second conductive layer 308M,
the second conductive layer 308M fills the upper region of the trench 305, and
the upper buried portion 308M/310L overlaps the source region 313 and the drain region 314,
wherein the material layer 310L directly contacts the gate insulating layer 306.
Kang does not teach that the material layer is a two-dimensional material layer.
Chandrasekhar (see, e.g., Fig. 2), on the other hand, teaches a barrier layer comprising a two-dimensional material, such as graphene, to provide improved electrical properties and lower electromigration failures (see, e.g., par. 0043).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Kang’s device, the barrier layer comprising a two-dimensional material, as taught by Chandrasekhar, to provide improved electrical properties and lower electromigration failures.
Regarding Claim 19, Kang and Chandrasekhar teach all aspects of claim 20. Chandrasekhar (see, e.g., Fig. 2), teaches that the two-dimensional material layer 214 comprises at least one of graphene, black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, and a transition metal dichalcogenide (see, e.g., par. 0029).
Regarding Claim 23, Kang and Chandrasekhar teach all aspects of claim 10. Kang and Chandrasekhar teach that the two-dimensional material layer 310L (214 of Chandrasekhar) directly contacts the gate insulating layer 306.
Regarding Claim 24, Kang and Chandrasekhar teach all aspects of claim 20. Kang (see, e.g., Fig. 10B), teaches that:
a work function of the second conductive layer 308M (i.e., WF(TiN) ≈ 4.2 – 4.7 eV) is less than a work function of the first conductive layer 307 (i.e., WF(W) ≈ 4.5 – 5.3 eV) (see, e.g., par. 0169),
wherein the second conductive layer 308M comprises at least one of aluminum (Al), titanium (Ti), chromium (Cr), gold (Au), nickel (Ni), and platinum (Pt) (see, e.g., par. 0169).
Allowable Subject Matter
Claims 1-5, 7-9, and 22 are allowed.
Claims 21, 25, and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
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/Nelson Garces/Primary Examiner, Art Unit 2814