DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-25 remain pending in this application. Acknowledgement is made of the amendment received 08/22/2025. Claims 1, 3, and 8 are amended.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-4, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (US 20220157981 A1, hereafter Gupta) in view of Okita et al (US 20230411506 A1, hereafter Okita).
Regarding claim 1, Gupta, in at least one embodiment, teaches: A semiconductor device (Gupta 200, 330, fig 2, fig 3D, ¶0071), comprising:
a semiconductor region (Gupta 14, 15, 82, 83) having a plurality of two-dimensional carrier channel (Gupta 15a, 19a, 15b, 19b, ¶0041) of a first conductivity type (Gupta, “2-dimensional electron gas (2DEG)”, ¶0041, n-type), the first conductivity type being one of a n-type (n-type) or a p-type conductivity, the plurality of two-dimensional carrier channels (Gupta 15a, 19a, 15b, 19b) having a net charge (Gupta ¶0046, “ionized positive charge in the channel layer 15”, ¶0051), the semiconductor region including a first semiconductor region (Gupta 14a, 14b, 15a, 15b, 83, as best shown by fig 2) coupled with a drain terminal (Gupta 22)(Gupta fig 2, 3D) and a second semiconductor region (Gupta 14a, 14b, 15a, 15b, 82, as best shown by fig 2) coupled with a source terminal (Gupta 21)(Gupta fig 2, 3D);
a third semiconductor region (Gupta 16, 81, 83, as best shown by fig 2) of a second conductivity type (Gupta ¶0049, p-type) electrically coupled with a gate terminal (Gupta 23, ¶0056), the second conductivity type being the other of the n-type or the p-type conductivity (p-type), the third semiconductor region having a gate region (Gupta 16, 81) and a net charge region (Gupta 16, 83, ¶0047), the gate region being disposed between the first semiconductor region (Gupta 14a, 14b, 15a, 15b, 83) and the second semiconductor region (Gupta 14a, 14b, 15a, 15b, 82)(Gupta 16, 81, at least laterally between), where the first and second semiconductor (Gupta 14a, 14b, 15a, 15b, Gupta 14, 15, 82, respectively) regions are separated on opposite sides of the gate region (Gupta 16, 81)(Gupta fig 2, region 81 separating 82 and 83), and the net charge region (Gupta 16, 83) disposed over the first semiconductor region (Gupta 14a, 14b, 15a, 15b)(Gupta fig 2).
Gupta does not explicitly teach: the net charge region disposed over the first semiconductor region, the net charge region having a net charge in a depletion region that is substantially equal to the net charge of the plurality of two-dimensional carrier channels in the first semiconductor region when the semiconductor device is in an off-state.
Gupta further teaches: a net charge region (Gupta 16, 83) having a net charge (Gupta, “areal density of ionized negative charge in the depleting layer 16”, ¶0051, therefore, at least having a net charge) in a depletion region (Gupta ¶0046-0047, 0051, region of 16 that is fully or partially depleted within 83) that is substantially equal to the net charge in the first semiconductor region (Gupta 14a, 14b, 15a, 15b, 83)(Gupta, “ratio between ionized negative charge and ionized positive charge can be between 90% and 110%”, ¶0051, a ratio of 90-110% being ±10% of 100% (equal), therefore meeting a broadest reasonable interpretation of “substantially equal”, further see applicant spec ¶0033) when the semiconductor device is in an off-state (Gupta, “when operated in the off-state”, ¶0051).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the net charge of the net charge region of Gupta, such that “the net charge region having a net charge in a depletion region that is substantially equal to the net charge of the plurality of two-dimensional carrier channels in the first semiconductor region when the semiconductor device is in an off-state”, in order to block high voltages and/or improve electric field uniformity (Gupta ¶0052).
Gupta does not teach: the gate region extending through the first semiconductor region and the second semiconductor region.
Okita, in the same field of endeavor of semiconductor device manufacturing, teaches: a gate region (Okita 11, ¶0064) extending through a first semiconductor region (Okita a region of 3, 4, 8, between 10 and 12, similar to Gupta 14a, 14b, 15a, 15b, fig 1, ¶0063) and a second semiconductor region (Okita a region of 3, 4, 8, between 9 and 12, similar to Gupta 14, 15, 81, fig 1, ¶0063)(Okita fig 1).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the gate region of Gupta to extend through the first and the second semiconductor regions, as taught by Okita, in order to reduce the on resistance and/or increase the maximum drain current of the device (Okita ¶0072).
Regarding claim 2, Gupta in view of Okita teaches: The semiconductor device of claim 1, wherein the net charge of the net charge region (Gupta 16, 83) is a function of a thickness of the depletion region (Gupta, region of 16 that is fully or partially depleted within 83) of the net charge region and an acceptor/donor concentration in the depletion region of the net charge region (Gupta ¶0049-0055, Gupta discloses adjusting the acceptor doping concentration and/or the thickness of the depleting layer 16 to obtain a desired profile).
Regarding claim 3, Gupta in view of Okita teaches: The semiconductor device of claim 2.
Gupta in view of Okita does not teach: a fourth semiconductor region of the first conductivity type positioned between the first semiconductor region and the third semiconductor region and between the second semiconductor region and the third semiconductor region, the fourth semiconductor region being in contact with the plurality of two-dimensional carrier channels in each of the first semiconductor region and the second semiconductor region.
Okita further teaches: a fourth semiconductor region (Okita 8, ¶0063-0064) of the first conductivity type (n-type) positioned between a first semiconductor region (Okita a region of 3, 4, 8, between 10 and 12, similar to Gupta 14a, 14b, 15a, 15b, fig 1, ¶0063) and a third semiconductor region (Okita 11, ¶0064, p-type)(Okita fig 1) and between a second semiconductor region (Okita a region of 3, 4, 8, between 9 and 12, similar to Gupta 14, 15, 81, fig 1, ¶0063) and the third semiconductor region (Okita fig 1), the fourth semiconductor region (Okita 8, ¶0063-0064) being in contact with a two-dimensional channel (Okita 3, 5, ¶0062) in each of the first semiconductor region and the second semiconductor region (Okita fig 1, best shown in fig 8 by 15 and 16, wherein 8 contacts 5).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Gupta in view of Okita to include the fourth semiconductor region of Okita, between the first and third, and the second and third semiconductor regions, and in contact with the two-dimensional carrier channels within each of the first and second semiconductor regions, in order to prevent the formation of a two-dimensional electron gas below the gate region, thereby reducing gate leakage and/or reducing on-resistance (Okita ¶0029, 0051, 0067).
Regarding claim 4, Gupta in view of Okita teaches: The semiconductor device of claim 3, wherein the net charge region (Gupta 16, 83) extends over the first semiconductor region (Gupta 14a, 14b, 15a, 15b) between the gate terminal (Gupta 23) and the drain terminal (Gupta 22)(Gupta fig 2, ¶0047).
Gupta in view of Okita does not explicitly teach: wherein the net charge region extends over an entirety of the first semiconductor region.
Gupta, in at least one embodiment, further teaches: the net charge region (region below Gupta 16) extends over a first semiconductor region (Gupta 14, 15, between 23 and 28, fig 3A) between a gate terminal (Gupta 23) and the drain terminal (Gupta 22, 22a, 28, 29, ¶0065)(Gupta fig 3A, ¶0065).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the drain terminal of Gupta in view of Okita, such the third semiconductor region contacts the drain terminal, therefore the net charge region extends over the entirety of the first semiconductor region, in order to improve electrical contact between the source and drain (Gupta ¶0064) and/or to reduce buffer dispersion (Gupta ¶0065).
Regarding claim 8, Gupta in view of Okita teaches: The semiconductor device of claim 3, wherein the fourth semiconductor region (Gupta as modified to include Okita 8) is positioned between a top surface of the first semiconductor region (Gupta 14a, 14b, 15a, 15b, 83, similar to the region of Okita 3, 4, 8, between 10 and 12) and the third semiconductor region (Gupta 16, 81, 83, as modified by Okita 11)(Okita fig 1), and wherein the fourth semiconductor region (Gupta as modified to include Okita 8) is also positioned over the second semiconductor region (Gupta 14, 15, 82, similar to the region of Okita 3, 4, 8, between 9 and 12)(Okita fig 1).
Gupta in view of Okita does not explicitly teach: wherein the net charge region has the net charge in the depletion region that is substantially equal to a sum of the net charge of the plurality of two-dimensional carrier channels in the first semiconductor region and a net charge of the fourth semiconductor region when the semiconductor device is in the off-state.
Gupta, in at least one embodiment, further teaches: a fourth semiconductor region (Gupta 625) fully depleting a two-dimensional channel (Gupta 19 within 610, fig 6A) when the device is an off-state (“enhancement-mode”, ¶0087).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify to the fourth semiconductor region of Gupta, such that “wherein the net charge region has the net charge in the depletion region that is substantially equal to a sum of the net charge of the plurality of two-dimensional carrier channels in the first semiconductor region and a net charge of the fourth semiconductor region when the semiconductor device is in the off-state”, in order to realize an enhancement mode transistor (Gupta ¶0087).
Claims 5, 9, 14-17, and 20-23 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (US 20220157981 A1, hereafter Gupta) in view of Okita et al (US 20230411506 A1, hereafter Okita), as applied to claims 1, 3 or 8 above, and further in view of Zhang et al (US 20200373383 A1, here after Zhang).
Regarding claim 5, Gupta in view of Okita teaches: The semiconductor device of claim 3, wherein the net charge region (Gupta 16, 83) extends between the gate terminal (Gupta 23) and the drain terminal (Gupta 22).
Gupta in view of Okita does not teach: wherein the net charge region includes a plurality of segments that extend between the gate terminal and the drain terminal.
Zhang, in the same field of endeavor of semiconductor device manufacturing, teaches: a net charge region (Zhang fig 3C, ¶0044-0045, a region formed by 13 and 25 wherein charges from a 2DEG channel are balanced with charges within a p-type semiconductor layer, therefore meeting a BRI of a “net charge region”) comprising a plurality of segments (Zhang 25, fig 3C) that extends between a gate terminal (Zhang 17) and a drain terminal (Zhang 18).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the net charge region of Gupta in view of Okita, such that the net charge region include a plurality of segments, as taught by Zhang, in order to reshape and/or manage the electric field, thereby improving the breakdown voltage of the device (Zhang ¶0046).
Regarding claim 9, Gupta in view of Okita teaches: The semiconductor device of claim 8.
Gupta in view of Okita does not teach: wherein the net charge region and the underlying fourth semiconductor region include a plurality of segments.
Zhang, in the same field of endeavor of semiconductor device manufacturing, teaches: a net charge region (Zhang fig 3C, ¶0044-0045, a region formed by 13 and 25 wherein charges from a 2DEG channel are balanced with charges within a p-type semiconductor layer, therefore meeting a BRI of a “net charge region”) comprising a plurality of segments (Zhang 25, fig 3C) that extends between a gate terminal (Zhang 17) and a drain terminal (Zhang 18).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the net charge region fourth semiconductor region of Gupta in view of Okita, such that the regions include a plurality of segments, as taught by Zhang, in order to reshape and/or manage the electric field, thereby improving the breakdown voltage of the device (Zhang ¶0046).
Regarding claim 14, Gupta in view of Okita teaches: The semiconductor device of claim 1, wherein the net charge region (Gupta 16, 83, ¶0047) extends between the gate terminal (Gupta 23) and the drain terminal (Gupta 22)(Gupta fig 2, ¶0047).
Gupta in view of Okita does not teach: wherein the gate region includes a plurality of sub-regions, any two sub-regions of the plurality of sub-regions separated by portions of the semiconductor region.
Zhang, in the same field of endeavor of semiconductor device manufacturing, teaches:
a gate region (Zhang fig 3C, 25 below 17, similar to Gupta 16, 81) includes a plurality of sub-regions (Zhang fig 3C, multiple instances of 25 below 17), any two sub-regions of the plurality of sub-regions separated by portions of a semiconductor region (Zhang 12, 13, 14, similar to Gupta 14, 15, 82, 83)(Zhang fig 3C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the gate region of Gupta in view of Okita, such that it includes a plurality of subregions separated by portions of the semiconductor region, as taught by Zhang, in order to reshape and/or manage the electric field, thereby improving the breakdown voltage of the device (Zhang ¶0046).
Regarding claim 15, Gupta in view of Okita and Zhang teaches: The semiconductor device of claim 14.
Gupta in view of Okita and Zhang does not explicitly teach: wherein the net charge region includes a plurality of segments.
Zhang further teaches: a net charge region (Zhang fig 3C, ¶0044-0045, a region formed by 13 and 25 wherein charges from a 2DEG channel are balanced with charges within a p-type semiconductor layer, therefore meeting a BRI of a “net charge region”) comprising a plurality of segments (Zhang 25, fig 3C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the net charge region of Gupta in view of Okita and Zhang, such that the net charge region include a plurality of segments, as taught by Zhang, in order to reshape and/or manage the electric field, thereby improving the breakdown voltage of the device (Zhang ¶0046).
Regarding claim 16, Gupta in view of Okita teaches: The semiconductor device of claim 1, wherein the net charge region (Gupta 16, 83) extends between the gate terminal (Gupta 23) and a first intermediate position (Gupta fig 2, left side of 25) between the gate terminal (Gupta 23) and the drain terminal (Gupta 22)(Gupta fig 2).
Gupta in view of Okita does not teach: wherein the gate region includes a plurality of sub-regions, any two sub-regions of the plurality of sub-regions separated by portions of the semiconductor region.
Zhang, in the same field of endeavor of semiconductor device manufacturing, teaches:
a gate region (Zhang fig 3C, 25 below 17, similar to Gupta 16, 81) includes a plurality of sub-regions (Zhang fig 3C, multiple instances of 25 below 17), any two sub-regions of the plurality of sub-regions separated by portions of a semiconductor region (Zhang 12, 13, 14, similar to Gupta 14, 15, 82, 83)(Zhang fig 3C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the gate region of Gupta in view of Okita, such that they includes a plurality of subregions separated by portions of the semiconductor region, as taught by Zhang, in order to reshape and/or manage the electric field, thereby improving the breakdown voltage of the device (Zhang ¶0046).
Regarding claim 17, Gupta in view of Okita and Zhang teaches: The semiconductor device of claim 16.
Gupta in view of Okita and Zhang does not explicitly teach: wherein the net charge region includes a plurality of segments.
Zhang further teaches: a net charge region (Zhang fig 3C, ¶0044-0045, a region formed by 13 and 25 wherein charges from a 2DEG channel are balanced with charges within a p-type semiconductor layer, therefore meeting a BRI of a “net charge region”) comprising a plurality of segments (Zhang 25, fig 3C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the net charge region Gupta in view of Okita and Zhang, such that the net charge region include a plurality of segments, as taught by Zhang, in order to reshape and/or manage the electric field, thereby improving the breakdown voltage of the device (Zhang ¶0046).
Regarding claim 20, Gupta in view of Okita teaches: The semiconductor device of claim 1, wherein the net charge region (Gupta 16, 83) extends between the gate terminal (Gupta 23) and the drain terminal (Gupta 22).
Gupta in view of Okita does not teach: wherein the gate region includes a plurality of sub-regions, any two sub-regions of the plurality of sub-regions separated by portions of the semiconductor region, the semiconductor device further comprising: a metal-oxide material disposed over sidewalls of the plurality of sub-regions.
Zhang, in the same field of endeavor of semiconductor device manufacturing, teaches:
a gate region (Zhang fig 2A, 13, 15 below 17, similar to Gupta 16, 81) includes a plurality of sub-regions (Zhang fig 3C, multiple instances of 15 below 17), any two sub-regions of the plurality of sub-regions separated by portions of a semiconductor region (Zhang 12, 13, 14, similar to Gupta 14, 15, 82, 83)(Zhang fig 2A, 2B), the semiconductor device further comprising: a metal-oxide material (Zhang, “nickel oxide and copper oxide”, ¶0040) disposed over sidewalls of the plurality of sub-regions (Zhang fig 2A, 2B, the material of 15 at least covers the side walls formed by the cavity it fills).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the gate region of Gupta in view of Okita, such that they includes a plurality of subregions separated by portions of the semiconductor region, as taught by Zhang, in order to reshape and/or manage the electric field, thereby improving the breakdown voltage of the device (Zhang ¶0046).
Regarding claim 21, Gupta in view of Okita and Zhang teaches: The semiconductor device of claim 20.
Gupta in view of Okita and Zhang does not explicitly teach: wherein the net charge region includes a plurality of segments.
Zhang further teaches: a net charge region (Zhang fig 3C, ¶0044-0045, a region formed by 13 and 25 wherein charges from a 2DEG channel are balanced with charges within a p-type semiconductor layer, therefore meeting a BRI of a “net charge region”) comprising a plurality of segments (Zhang 25, fig 3C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the net charge region of Gupta in view of Okita and Zhang, such that the net charge region include a plurality of segments, as taught by Zhang, in order to reshape and/or manage the electric field, thereby improving the breakdown voltage of the device (Zhang ¶0046).
Regarding claim 22, Gupta in view of Okita teaches: The semiconductor device of claim 1, wherein the net charge region (Gupta 16, 83) extends between the gate terminal (Gupta 23) and an intermediate position (Gupta fig 2, left side of 25) and the drain terminal (Gupta 22)(Gupta fig 2).
Gupta in view of Okita does not teach: wherein the gate region includes a plurality of sub-regions, any two sub-regions of the plurality of sub-regions separated by portions of the semiconductor region, the semiconductor device further comprising: a metal-oxide material disposed over sidewalls of the plurality of sub-regions.
Zhang, in the same field of endeavor of semiconductor device manufacturing, teaches:
a gate region (Zhang fig 2A, 13, 15 below 17, similar to Gupta 16, 81) includes a plurality of sub-regions (Zhang fig 3C, multiple instances of 15 below 17), any two sub-regions of the plurality of sub-regions separated by portions of a semiconductor region (Zhang 12, 13, 14, similar to Gupta 14, 15, 82, 83)(Zhang fig 2A, 2B), the semiconductor device further comprising: a metal-oxide material (Zhang, “nickel oxide and copper oxide”, ¶0040) disposed over sidewalls of the plurality of sub-regions (Zhang fig 2A, 2B, the material of 15 at least covers the side walls formed by the cavity it fills).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the gate region of Gupta in view of Okita, such that they includes a plurality of subregions separated by portions of the semiconductor region, as taught by Zhang, in order to reshape and/or manage the electric field, thereby improving the breakdown voltage of the device (Zhang ¶0046).
Regarding claim 23, Gupta in view of Okita and Zhang teaches: The semiconductor device of claim 22.
Gupta in view of Okita and Zhang does not explicitly teach: wherein the net charge region includes a plurality of segments.
Zhang further teaches: a net charge region (Zhang fig 3C, ¶0044-0045, a region formed by 13 and 25 wherein charges from a 2DEG channel are balanced with charges within a p-type semiconductor layer, therefore meeting a BRI of a “net charge region”) comprising a plurality of segments (Zhang 25, fig 3C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the net charge region of Gupta in view of Okita and Zhang, such that the net charge region include a plurality of segments, as taught by Zhang, in order to reshape and/or manage the electric field, thereby improving the breakdown voltage of the device (Zhang ¶0046).
Claims 6, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (US 20220157981 A1, hereafter Gupta) in view of Okita et al (US 20230411506 A1, hereafter Okita), as applied to claim 3 or 8 above, and further in view of Mishra et al (20190198615 A1, here after Mishra).
Regarding claim 6, Gupta in view of Okita teaches: The semiconductor device of claim 3, wherein the net charge region (Gupta 16, 83) includes a gate-side portion (Gupta fig 2, 16 in 83 left of 25), wherein the gate-side portion extends between the gate terminal (Gupta 23) and a first intermediate position (Gupta fig 2, left side of 25).
Gupta in view of Okita does not teach: wherein the net charge region includes a drain-side portion, wherein the drain-side portion extends between the drain terminal and a second intermediate position.
Mishra, in the same field of endeavor of semiconductor device manufacturing, teaches: a net charge region (Mishra 20, 420, 83, ¶0034-0036, 0043, 20 is a p-type semiconductor layer, “electrically neutral … equal to the concentration of bulk polarization charge throughout the layer 20”, therefore at least having a net charge, similar to Gupta 16, 83) includes a gate-side portion (Mishra 20, 420) and a drain-side portion (Mishra 20’, 420’), wherein the gate-side portion extends between a gate terminal (Mishra 88, 81) and a first intermediate position (Mishra fig 20, at least 20 extends between 88 and 33), and the drain-side portion extends between a drain terminal (Mishra 75, 86) and a second intermediate position (Mishra fig 20, at least 20’ extends between 75 and 33)(Mishra fig 20).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the net charge region of Gupta in view of Okita to include a drain-side region, such that “the net charge region includes a gate-side portion and a drain-side portion, wherein the gate-side portion extends between the gate terminal and a first intermediate position, and the drain-side portion extends between the drain terminal and a second intermediate position”, as taught by Mishra, in order to reduce the dynamic on-resistance of the device, thereby improving device performance (Mishra ¶0069).
Regarding claim 10, Gupta in view of Okita teaches: The semiconductor device of claim 8.
Gupta in view of Okita does not teach: wherein the net charge region and the underlying fourth semiconductor region extend between the gate terminal and a first intermediate position between the gate terminal and the drain terminal.
Mishra, in the same field of endeavor of semiconductor device manufacturing, teaches: a net charge region (Mishra 20, 420, 83, ¶0034-0036, 0043, 20 is a p-type semiconductor layer, “electrically neutral … equal to the concentration of bulk polarization charge throughout the layer 20”, therefore at least having a net charge, similar to Gupta 16, 83) and an underlying semiconductor region (Mishra 20, 20’) extend between the gate terminal (Mishra 88, 81) and a first intermediate position (Mishra fig 20, at least 20 extends between 88 and 33) between the gate terminal and the drain terminal (Mishra 75, 86)(Mishra fig 20).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the net charge region of Gupta in view of Okita to include a break between the gate and drain regions, such that “wherein the net charge region and the underlying fourth semiconductor region extend between the gate terminal and a first intermediate position between the gate terminal and the drain terminal”, as taught by Mishra, in order to reduce the dynamic on-resistance of the device, thereby improving device performance (Mishra ¶0069).
Regarding claim 12, Gupta in view of Okita teaches: The semiconductor device of claim 8.
Gupta in view of Okita does not teach: wherein the net-charge region and the underlying fourth semiconductor region includes a gate-side portion and a drain-side portion, wherein the gate-side portion extends between the gate terminal and a first intermediate position, and the drain-side portion extends between the drain terminal and a second intermediate position.
Mishra, in the same field of endeavor of semiconductor device manufacturing, teaches: a net charge region (Mishra 20, 420, 83, ¶0034-0036, 0043, 20 is a p-type semiconductor layer, “electrically neutral … equal to the concentration of bulk polarization charge throughout the layer 20”, therefore at least having a net charge, similar to Gupta 16, 83) and an underlying semiconductor region (Mishra 20, 20’) includes a gate-side portion (Mishra 20, 420) and a drain-side portion (Mishra 20’, 420’), wherein the gate-side portion extends between a gate terminal (Mishra 88, 81) and a first intermediate position (Mishra fig 20, at least 20 extends between 88 and 33), and the drain-side portion extends between a drain terminal (Mishra 75, 86) and a second intermediate position (Mishra fig 20, at least 20’ extends between 75 and 33)(Mishra fig 20).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the net charge region of Gupta in view of Okita to include a break between the gate and drain regions, such that “net-charge region and the underlying fourth semiconductor region includes a gate-side portion and a drain-side portion, wherein the gate-side portion extends between the gate terminal and a first intermediate position, and the drain-side portion extends between the drain terminal and a second intermediate position”, as taught by Mishra, in order to reduce the dynamic on-resistance of the device, thereby improving device performance (Mishra ¶0069).
Claims 7, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (US 20220157981 A1, hereafter Gupta) in view of Okita et al (US 20230411506 A1, hereafter Okita) and Mishra et al (20190198615 A1, here after Mishra), as applied to claim 6, 10, or 12 above, and further in view of Zhang et al (US 20200373383 A1, here after Zhang).
Regarding claim 7, Gupta in view of Okita and Mishra teaches: The semiconductor device of claim 6.
Gupta in view of Okita and Mishra does not teach: wherein the gate-side portion and the drain-side portions each includes a plurality of segments.
Zhang, in the same field of endeavor of semiconductor device manufacturing, teaches: a net charge region (Zhang fig 3C, ¶0044-0045, a region formed by 13 and 25 wherein charges from a 2DEG channel are balanced with charges within a p-type semiconductor layer, therefore meeting a BRI of a “net charge region”) comprising a plurality of segments (Zhang 25, fig 3C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the net charge region of Gupta in view of Okita and Mishra, such that the gate and drain side portion each include a plurality of segments, as taught by Zhang, in order to reshape and/or manage the electric field, thereby improving the breakdown voltage of the device (Zhang ¶0046).
Regarding claim 11, Gupta in view of Okita and Mishra teaches: The semiconductor device of claim 10.
Gupta in view of Okita and Mishra does not teach: wherein the net charge region and the underlying fourth semiconductor region include a plurality of segments.
Zhang, in the same field of endeavor of semiconductor device manufacturing, teaches: a net charge region (Zhang fig 3C, ¶0044-0045, a region formed by 13 and 25 wherein charges from a 2DEG channel are balanced with charges within a p-type semiconductor layer, therefore meeting a BRI of a “net charge region”) comprising a plurality of segments (Zhang 25, fig 3C) that extends between a gate terminal (Zhang 17) and a drain terminal (Zhang 18).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the net charge region fourth semiconductor region of Gupta in view of Okita and Mishra, such that the regions include a plurality of segments, as taught by Zhang, in order to reshape and/or manage the electric field, thereby improving the breakdown voltage of the device (Zhang ¶0046).
Regarding claim 13, Gupta in view of Okita and Mishra teaches: The semiconductor device of claim 12.
Gupta in view of Okita and Mishra does not teach: wherein the gate-side portion and the drain-side portions each includes a plurality of segments.
Zhang, in the same field of endeavor of semiconductor device manufacturing, teaches: a net charge region (Zhang fig 3C, ¶0044-0045, a region formed by 13 and 25 wherein charges from a 2DEG channel are balanced with charges within a p-type semiconductor layer, therefore meeting a BRI of a “net charge region”) comprising a plurality of segments (Zhang 25, fig 3C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the net charge region of Gupta in view of Okita and Mishra, such that the gate and drain side portion each include a plurality of segments, as taught by Zhang, in order to reshape and/or manage the electric field, thereby improving the breakdown voltage of the device (Zhang ¶0046).
Claims 18, 19, 24, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (US 20220157981 A1, hereafter Gupta) in view of Okita et al (US 20230411506 A1, hereafter Okita), as applied to claim 1 above, and further in view of Mishra et al (20190198615 A1, here after Mishra) and Zhang et al (US 20200373383 A1, here after Zhang).
Regarding claim 18, Gupta in view of Okita teaches: The semiconductor of claim 1, wherein the net charge region (Gupta 16, 83) includes a gate-side portion (Gupta fig 2, 16 in 83 left of 25), wherein the gate-side portion extends between the gate terminal (Gupta 23) and a first intermediate position (Gupta fig 2, left side of 25).
Gupta in view of Okita does not teach: wherein the net charge region includes a drain-side portion, wherein the drain-side portion extends between the drain terminal and a second intermediate position.
Mishra, in the same field of endeavor of semiconductor device manufacturing, teaches: a net charge region (Mishra 20, 420, 83, ¶0034-0036, 0043, 20 is a p-type semiconductor layer, “electrically neutral … equal to the concentration of bulk polarization charge throughout the layer 20”, therefore at least having a net charge, similar to Gupta 16, 83) includes a gate-side portion (Mishra 20, 420) and a drain-side portion (Mishra 20’, 420’), wherein the gate-side portion extends between a gate terminal (Mishra 88, 81) and a first intermediate position (Mishra fig 20, at least 20 extends between 88 and 33), and the drain-side portion extends between a drain terminal (Mishra 75, 86) and a second intermediate position (Mishra fig 20, at least 20’ extends between 75 and 33)(Mishra fig 20).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the net charge region of Gupta to include a drain-side region, such that “the net charge region includes a gate-side portion and a drain-side portion, wherein the gate-side portion extends between the gate terminal and a first intermediate position, and the drain-side portion extends between the drain terminal and a second intermediate position”, as taught by Mishra, in order to reduce the dynamic on-resistance of the device, thereby improving device performance (Mishra ¶0069).
Gupta in view of Okita and Mishra does not teach: wherein the gate region includes a plurality of sub-regions, any two sub-regions of the plurality of sub-regions separated by portions of the semiconductor region.
Zhang, in the same field of endeavor of semiconductor device manufacturing, teaches: a gate region (Zhang fig 3C, 25 below 17, similar to Gupta 16, 81) includes a plurality of sub-regions (Zhang fig 3C, multiple instances of 25 below 17), any two sub-regions of the plurality of sub-regions separated by portions of a semiconductor region (Zhang 12, 13, 14, similar to Gupta 14, 15, 82, 83)(Zhang fig 3C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the gate region of Gupta in view of Okita and Mishra, such that it includes a plurality of subregions separated by portions of the semiconductor region, as taught by Zhang, in order to reshape and/or manage the electric field, thereby improving the breakdown voltage of the device (Zhang ¶0046).
Regarding claim 19, Gupta in view of Okita, Mishra, and Zhang teaches: The semiconductor device of claim 19.
Gupta in view of Okita, Mishra, and Zhang does not teach: wherein the gate-side portion and the drain-side portions each includes a plurality of segments.
Zhang, further teaches: a net charge region (Zhang fig 3C, ¶0044-0045, a region formed by 13 and 25 wherein charges from a 2DEG channel are balanced with charges within a p-type semiconductor layer, therefore meeting a BRI of a “net charge region”) comprising a plurality of segments (Zhang 25, fig 3C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the net charge region of Gupta in view of Okita, Mishra, and Zhang, such that the gate and drain side portion each include a plurality of segments, as taught by Zhang, in order to reshape and/or manage the electric field, thereby improving the breakdown voltage of the device (Zhang ¶0046).
Regarding claim 24, Gupta in view of Okita teaches: The semiconductor device of claim 1, wherein the net charge region (Gupta 16, 83) includes a gate-side portion (Gupta fig 2, 16 in 83 left of 25), wherein the gate-side portion extends between the gate terminal (Gupta 23) and a first intermediate position (Gupta fig 2, left side of 25).
Gupta in view of Okita does not teach: wherein the net charge region includes a drain-side portion, wherein the drain-side portion extends between the drain terminal and a second intermediate position.
Mishra, in the same field of endeavor of semiconductor device manufacturing, teaches: a net charge region (Mishra 20, 420, 83, ¶0034-0036, 0043, 20 is a p-type semiconductor layer, “electrically neutral … equal to the concentration of bulk polarization charge throughout the layer 20”, therefore at least having a net charge, similar to Gupta 16, 83) includes a gate-side portion (Mishra 20, 420) and a drain-side portion (Mishra 20’, 420’), wherein the gate-side portion extends between a gate terminal (Mishra 88, 81) and a first intermediate position (Mishra fig 20, at least 20 extends between 88 and 33), and the drain-side portion extends between a drain terminal (Mishra 75, 86) and a second intermediate position (Mishra fig 20, at least 20’ extends between 75 and 33)(Mishra fig 20).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the net charge region of Gupta to include a drain-side region, such that “the net charge region includes a gate-side portion and a drain-side portion, wherein the gate-side portion extends between the gate terminal and a first intermediate position, and the drain-side portion extends between the drain terminal and a second intermediate position”, as taught by Mishra, in order to reduce the dynamic on-resistance of the device, thereby improving device performance (Mishra ¶0069).
Gupta in view of Okita and Mishra does not teach: wherein the gate region includes a plurality of sub-regions, any two sub-regions of the plurality of sub-regions separated by portions of the semiconductor region, the semiconductor device further comprising: a metal-oxide material disposed over sidewalls of the plurality of sub-regions.
Zhang, in the same field of endeavor of semiconductor device manufacturing, teaches: a gate region (Zhang fig 2A, 13, 15 below 17, similar to Gupta 16, 81) includes a plurality of sub-regions (Zhang fig 3C, multiple instances of 15 below 17), any two sub-regions of the plurality of sub-regions separated by portions of a semiconductor region (Zhang 12, 13, 14, similar to Gupta 14, 15, 82, 83)(Zhang fig 2A, 2B), the semiconductor device further comprising: a metal-oxide material (Zhang, “nickel oxide and copper oxide”, ¶0040) disposed over sidewalls of the plurality of sub-regions (Zhang fig 2A, 2B, the material of 15 at least covers the side walls formed by the cavity it fills).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the gate region of Gupta in view of Okita and Mishra, such that they includes a plurality of subregions separated by portions of the semiconductor region, as taught by Zhang, in order to reshape and/or manage the electric field, thereby improving the breakdown voltage of the device (Zhang ¶0046).
Regarding claim 25, Gupta in view of Okita, Mishra, and Zhang teaches: The semiconductor device of claim 24.
Gupta in view of Okita, Mishra, and Zhang does not teach: wherein the gate-side portion and the drain-side portions each includes a plurality of segments.
Zhang, further teaches: a net charge region (Zhang fig 3C, ¶0044-0045, a region formed by 13 and 25 wherein charges from a 2DEG channel are balanced with charges within a p-type semiconductor layer, therefore meeting a BRI of a “net charge region”) comprising a plurality of segments (Zhang 25, fig 3C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the net charge region of Gupta in view of Okita, Mishra, and Zhang, such that the gate and drain side portion each include a plurality of segments, as taught by Zhang, in order to reshape and/or manage the electric field, thereby improving the breakdown voltage of the device (Zhang ¶0046).
Response to Arguments
Applicant's arguments filed 08/22/2025 have been fully considered but they are not persuasive.
Applicant alleges at pages 10 and 11:
Gupta does not teach that the Ill-N depleting layer 16 (i.e., the alleged third semiconductor region) includes a gate region disposed between and separating the first semiconductor region and the second semiconductor region, where the first and second semiconductor regions are on opposite sides of the gate region.
Examiner’s response:
The examiner respectfully disagrees. As can clearly be seen in fig 2, at least a portion of Gupta 16 is within Gupta 81, where Gupta 81 separates two other regions, Gupta 82 and Gupta 83, which are on opposite sides of Gupta 81. Gupta 82 and 83 are regions that at least comprise semiconductor layers, therefore at least meet a broadest reasonable interpretation of “a semiconductor region”, and Gupta discloses 81 is a “gate region” (Gupta ¶0047, 0004). Thus, Gupta teaches that “the third semiconductor region includes a gate region disposed between and separating the first semiconductor region and the second semiconductor region, where the first and second semiconductor regions are on opposite sides of the gate region”.
Regarding claims 6, 10, and 12, Applicant alleges at pages 14 and 15:
Gupta in view of Okita further in view of Mishra fails to disclose, teach, or suggest at least the features emphasized below.
Examiner’s response:
The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Applicant’s arguments with respect to the remaining claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/Mounir S Amer/Primary Examiner, Art Unit 2818