DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 1/20/2026, responding to the Office action mailed on 10/20/2025, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/29/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6-7, 10-11, and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie (US 11101217 B2).
Re Claim 1 Xie teaches a semiconductor device (FIG. 20, col 11 line 31), comprising:
a transistor (50, col 4 line 12) disposed on a semiconductor substrate (110, col 5 line 1), wherein the transistor comprises a source/drain region (240, col 10 line 43) disposed on a first side (above top of 110) of the semiconductor substrate (110);
a via (270, “buried contact”, col 11 line 21) extending through the semiconductor substrate (110, 270 shows as part of it being above the top of the substrate 110 and vertically extending into the top part of the substrate through a top edge of 110), and wherein the via (270) connects a power element (215 and 212, col 9 line 5) disposed on a second side (under top of 110) of the semiconductor substrate (110) to the source/drain region (240), and wherein the via (270) is disposed below (bottom part of 270 is lower than bottom part of 240 in FIG. 20) and in (mechanical, 270 and the bottom part of 240 are in the same structure and are therefore in “mechanically contact”) contact with a bottom surface of the source/drain region (240); and
a dielectric spacer (229, col 11 line 16) disposed between the via (270) and the semiconductor substrate (110, FIG. 20).
Re Claim 2 Xie teaches the semiconductor device of claim 1, wherein the power element (215 and 212) comprises a power rail (212, col 9 line 6, FIG. 20 ).
Re Claim 6 Xie teaches the semiconductor device of claim 1, further comprising an inter-layer dielectric layer (172, col 7 line 23) disposed on the second side of the semiconductor substrate (110) adjacent the power element (215 and 212), wherein at least a portion of the dielectric spacer (229) contacts the inter-layer dielectric layer (172, 172 and 229 are thermally connected as they are part of the same chip, FIG. 20).
Re Claim 7 Xie teaches the semiconductor device of claim 1, wherein at least a portion of the dielectric spacer (229) contacts the power element (215 and 212, FIG. 20).
Re Claim 10 Xie teaches the semiconductor device of claim 1, wherein the dielectric spacer (229) extends from the power element (215 and 212) along a sidewall of the via (270, FIG. 19).
Re Claim 11 Xie teaches the semiconductor device of claim 1, further comprising:
one or more additional transistors (col 4 line 12 states, “In one or more embodiments, multiple device cells 50 can be adjacent to each other on a substrate, where the device cells can include transistor devices.”) on the semiconductor substrate (110), wherein the one or more additional transistors (50) comprise one or more additional source/drain regions (240); and
one or more additional vias (295, col 11 lines 60) disposed on the one or more additional source/drain regions (240), wherein the one or more additional vias are disposed on the first side (above top of 110) of the semiconductor substrate (FIG. 20).
Re Claim 16 Xie teaches a semiconductor device (FIG. 20, col 11 line 31), comprising:
a source/drain region (240, col 10 line 43) disposed on a first side (above top of 110) of a semiconductor layer (110, col 5 line 1);
a power element (215 and 212, col 9 line 5) disposed on a second side (under top of 110) of the semiconductor layer (110); and
a via (270, “buried contact”, col 11 line 21) extending through the semiconductor layer (110, 270 shows as part of it being above the top of the substrate 110 and vertically extending into the top part of the substrate through a top edge of 110) and between the power element (215 and 212) and the source/drain region (240), and wherein the via (270) connects a power element (215 and 212, col 9 line 5) disposed on a second side (under top of 110) of the semiconductor substrate (110) to the source/drain region (240);
wherein the via (270) is disposed below (bottom part of 270 is lower than bottom part of 240 in FIG. 20) and in (mechanical, 270 and the bottom part of 240 are in the same structure and are therefore in “mechanically contact”) contact with a bottom surface of the source/drain region (240, FIG. 20).
Re Claim 17 Xie teaches the semiconductor device of claim 16, wherein the power element (215 and 212, col 9 line 6, FIG. 20) comprises a power rail (212, col 9 line 6, FIG. 20).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Xie (US 11101217 B2) in view of Chen (US 20180337112 A1).
Re Claim 3 Xie teaches the semiconductor device of claim 1, wherein:
the dielectric spacer (229) is disposed on a sidewall of the via (270, FIG. 20).
Xie does not teach the dielectric spacer is vertically aligned with a gate sidewall spacer of a gate structure of the transistor.
Chen teaches the dielectric spacer (44) [0017] is vertically aligned (in FIG. 4) with a gate sidewall spacer (27 in FIG. 1) [0014] of a gate structure (26) [0014] of the transistor (24) [0014].
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chen into the structure of Xie since Chen integrates a via contact through the substrate.
The ordinary artisan would have been motivated to modify Cannon in combination with Xie in the above manner for the motivation of optimally arranging the gate spacer and dielectric spacer in relation to each other to allow one to build a transistor that functions at peak levels and can still be scaled down in size as the industry continues to improve integrated density. [0002] states, “Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.).”
Re Claim 18 Xie teaches the semiconductor device of claim 16, further comprising a dielectric spacer (229, col 11 line 16) disposed between the via (270) and the semiconductor layer (110) and on a sidewall of the via (270, FIG. 19).
Xie does not teach the dielectric spacer is vertically aligned with a gate sidewall spacer of a gate structure of the transistor.
Chen teaches the dielectric spacer (44) [0017] is vertically aligned (in FIG. 4) with a gate sidewall spacer (27 in FIG. 1) [0014] of a gate structure (26) [0014] of the transistor (24) [0014].
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chen into the structure of Xie since Chen integrates a via contact through the substrate.
The ordinary artisan would have been motivated to modify Cannon in combination with Xie in the above manner for the motivation of optimally arranging the gate spacer and dielectric spacer in relation to each other to allow one to build a transistor that functions at peak levels and can still be scaled down in size as the industry continues to improve integrated density. [0002] states, “Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.).”
Claims 4-5 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Xie (US 11101217 B2) in view of Cannon (US 7965540 B2).
Re Claim 4 Xie teaches the semiconductor device of claim 1, but does not teach an isolation region disposed between the dielectric spacer and the semiconductor substrate.
Cannon teaches an isolation region (710, col 9 line 28) disposed between the dielectric spacer (214, col 5 line 8) and the semiconductor substrate (210, col 5 line 4, FIG. 7c).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Cannon into the structure of Xie since both inventions are transistors with power rails in the chips, col 7 line 55).
The ordinary artisan would have been motivated to modify Cannon in combination with Xie in the above manner for the motivation of adding an isolation region to the chip to help optimize the resistance and current in the device. The abstract states, “…the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).”
Re Claim 5 Xie in view of teaches the semiconductor device of claim 4, wherein the isolation region (Cannon, 710) comprises a shallow trench isolation region (714, col 9 line 32, FIG, 7d).
Re Claim 12 Xie teaches an integrated circuit (FIG. 20, col 11 line 31) comprising:
a transistor (50, col 4 line 12) disposed on a semiconductor layer (110, col 5 line 1), wherein the transistor comprises a source/drain region (240, col 10 line 43) disposed on a first side (above top of 110) of the semiconductor layer (110, FIG. 20); and
a via (270, “buried contact”, col 11 line 21) extending through the semiconductor layer (110, 270 shows as part of it being above the top of the substrate 110 and vertically extending into the top part of the substrate through a top edges of 110), and wherein the via (270) connects a power element (215 and 212, col 9 line 6, FIG. 19) disposed on a second side (under top of 110) of the semiconductor layer (110) to the source/drain region (240, FIG. 20), and wherein the via (270) is disposed below (bottom part of 270 is lower than bottom part of 240 in FIG. 20) and in (mechanical, 270 and the bottom part of 240 are in the same structure and are therefore in “mechanically contact”) contact with a bottom surface of the source/drain region (240);
Xie does not teach an isolation region disposed in the semiconductor layer, and
wherein the isolation region is disposed between the via and the semiconductor layer.
Cannon teaches an isolation region (714, col 9 line 32) disposed in the semiconductor layer (210, col 5 line 4, FIG. 7c),
wherein the isolation region (714) is disposed between the via (248, col 7 line 5, “gate conductors”) and the semiconductor layer (210, col 5 line 4, FIG. 7c).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Cannon into the structure of Xie since both inventions are transistors with power rails in the chips, col 7 line 55).
The ordinary artisan would have been motivated to modify Cannon in combination with Xie in the above manner for the motivation of adding an isolation region to the chip to help optimize the resistance and current in the device. The abstract states, “…the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).”
Re Claim 13 Xie in view of Cannon teaches the integrated circuit of claim 12, wherein the power element (Xie, 215 and 212) comprises a power rail (212, col 9 line 6, FIG. 20).
Re Claim 14 Xie in view of Cannon teaches the integrated circuit of claim 12, further comprising:
a dielectric spacer (Cannon, 250, col 7 line 5) disposed between the via (248) and the isolation region (714, FIG. 7e); and
an inter-layer dielectric layer (Xie, 172, col 7 line 23) disposed on the second side (under top of 110) of the semiconductor layer (110) adjacent the power element (215 and 212), wherein
at least a portion of the dielectric spacer (229) contacts the inter- layer dielectric layer (172, 172 and 229 are thermally connected as they are part of the same chip, FIG. 20).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Xie (US 11101217 B2) in view of Xie (US 20210217654 A1), Xie2 hereafter.
Re Claim 8 Xie teaches the semiconductor device of claim 1, but does not teach the transistor comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and the source/drain region is connected to the plurality of channel layers.
Xie2 teaches the transistor (100) [0039] comprises a plurality of gate structures (706) [0069] alternately stacked with a plurality of channel layers (208) [0044], and the source/drain region (602) [0061] is connected to the plurality of channel layers (208, FIG. 9B).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Xie2 into the structure of Xie since both patents teach source and drain region in a similar schematic design.
The ordinary artisan would have been motivated to modify Xie2 in combination with Xie in the above manner for the motivation of integrating the nanosheet structure to the device reducing parasitic capacitance helping the device reach peak performance. [0001] states, “The present invention generally relates to fabrication methods and resulting structures for semiconductor devices, and more specifically, to a nanosheet transistor architecture having a self-aligned dielectric pillar for reducing parasitic capacitance”
Re Claim 9 Xie in view of Xie 2 teaches the semiconductor device of claim 8, wherein the source/drain region (602) is positioned on a lateral side of the plurality of gate structures (706) and the plurality of channel layers (208, FIG. 9B).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Xie (US 11101217 B2) in view of Cannon (US 7965540 B2) as applied to claim 14 above, and further in view of Chen (US 20180337112 A1).
Re Claim 15 Xie in view of Cannon teaches the integrated circuit of claim 14, wherein the dielectric spacer (Xie, 229) extends from the power element (215 and 212) along a sidewall of the via (270, FIG. 20).
Xie in view of Cannon does not teach the dielectric spacer is vertically aligned with a gate sidewall spacer of a gate structure of the transistor.
Chen teaches the dielectric spacer (44) [0017] is vertically aligned (in FIG. 4) with a gate sidewall spacer (27 in FIG. 1) [0014] of a gate structure (26) [0014] of the transistor (24) [0014].
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chen into the structure of Xie in view of Cannon since Chen integrates a via contact through the substrate.
The ordinary artisan would have been motivated to modify Cannon in combination with Xie in view of Cannon in the above manner for the motivation of optimally arranging the gate spacer and dielectric spacer in relation to each other to allow one to build a transistor that functions at peak levels and can still be scaled down in size as the industry continues to improve integrated density. [0002] states, “Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.).”
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Xie (US 11101217 B2) in view of Chen (US 20180337112 A1) as applied to claim 18 above, and further in view of Cannon (US 7965540 B2).
Re Claim 19 Xie in view of Chen teaches the semiconductor device of claim 18, but does not teach an isolation region disposed between the dielectric spacer and the semiconductor layer.
Cannon teaches an isolation region (714, FIG. 7e) disposed between the dielectric spacer (250, col 7 line 5) and the semiconductor layer (210, col 5 line 4, FIG. 7c).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Cannon into the structure of Xie in view of Chen since Cannon teaches transistors with power rails in the chips, col 7 line 55)
The ordinary artisan would have been motivated to modify Cannon in combination with Xie in view of Chen in the above manner for the motivation of adding an isolation region to the chip to help optimize the resistance and current in the device. The abstract states, “…the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).”
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Xie (US 11101217 B2) in view of Chen (US 20180337112 A1) and Cannon (US 7965540 B2) as applied to claim 19 above, and further in view of Venigalla (US 20200075428 A1).
Re Claim 20 Xie in view of Chen and Cannon teaches the semiconductor device of claim 19, but does not teach the dielectric spacer extends along a side of the isolation region.
Venigalla teaches the dielectric spacer (712) [0058] extends along a side of the isolation region (402, FIG. 7A) [0045].
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Venigalla into the structure of Xie in view of Chen and Cannon since Venigalla teaches transistors with power rails in the chips [0065].
The ordinary artisan would have been motivated to modify Venigalla in combination with Xie in view of Chen and Cannon the above manner for the motivation of having the dielectric spacer extend along the isolation region to help the device maintain current path integrity and function optimally.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant Arguments/Remarks Made in an Amendment on page 5 (of text printed on page) the applicant argues in the 2nd to last paragraph, “…Xie does not disclose or suggest a semiconductor device comprising, e.g., a via extending through the semiconductor substrate, wherein the via connects a power element disposed on a second side of the semiconductor substrate to the source drain region, and wherein the via is disposed below and in contact with a bottom surface of the source drain region, as recited in claim 1.”
Examiner response: Xie FIG. 20 shows via (270, col 11 line 21) breaks the plan of the top surface of substrate (110, col 5 line 1). Therefore, the via extends through the substrate. The via (270) is directly connected to a power element (215 and 212, col 9 line 5) disposed on a second side (under top of 110) of the semiconductor substrate (110) to the source/drain region (240). The via (270) has a bottom surface lower than source/drain (240, col 10 line 43), therefore the via is exposed “below” the source/drain region. The bottom of the source/drain region (240) is in the same semiconductor structure as the via (270). Therefore, the via (270) and the bottom of the source/drain region (240) is in mechanical contact.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 4/8/26