Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Specification Objection Withdrawal
Applicant’s amendment of the title of the invention is acknowledged. Thus, the objection to specification is withdrawn.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 9, 13 and 14 rejected under 35 U.S.C. 103 as being unpatentable over Tanaka (U.S. Patent Pub. No. 2011/0049575) of record, in view of Kim (U.S. Patent Pub. No. 2021/0193657) of record.
Regarding Claim 1
FIG. 14 of Tanaka discloses a semiconductor integrated circuits comprising: in a standard cell where power source lines and active regions are disposed, a first power supply line (31D1) and a second power source line (31S) disposed to extend in a first direction and to be separated from each other; a third power source line (31D0) disposed to be adjacent to and in parallel to the first power supply line in a second direction orthogonal to the first direction, the third power source line having an electric potential (VSS) equivalent to an electric potential of the second power source line; a fourth power source line (31D2) disposed to be adjacent to and in parallel to the second power supply line in a negative direction of the second direction, the fourth power source line having an electric potential equivalent to that of the first power source line (VDD); a first transistor (PMOS) disposed below the first power supply line, first transistor including a first conductivity-type first active region (11P) extending in the second direction and the negative direction of the second direction; a second transistor (NMOS) disposed below the second power source line, the second transistor including a second conductivity-type second active region (12N) extending in the second direction and the minus direction of the second direction; a third transistor (NMOS) disposed between the first active region and the third power source line, the third transistor including a second conductivity-type third active region (10N); and a fourth transistor (PMOS) disposed between the second active region and the fourth power source line, the fourth transistor including a first conductivity-type fourth active region (12P); and a first common electrode (38) connecting the first active region, the second active region, the third active region, and the fourth active region.
FIG. 14 of Tanaka is silent with respect to “the first active region overlaps with the first power source line when viewed from a normal direction normal to a plane extending in the first and second directions, and the second active region overlaps with the second power source line when viewed from the normal direction”. However, FIG. 7 of Tanaka discloses an alternative embodiment, wherein the first active region overlaps with the first power source line when viewed from a normal direction normal to a plane extending in the first and second directions. It would have been obvious to one of ordinary skill in the art that to modify FIG. 14 of Tanaka such that the second active region overlaps with the second power source line when viewed from the normal direction, because said configuration was a matter of choice, as evidenced by various embodiments of Tanaka, which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant. In re Dailey 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton 97 US 3,24 (USSC 1878). MPEP 2144.04.
Furthermore, FIG. 3 of Kim disclose a similar semiconductor integrated circuits, comprising a first power supply line (POR3) and a second power source line (POR2) disposed to extend in a first direction and to be separated from each other; a third power source line (POR4) disposed to be adjacent to and in parallel to the first power supply line in a second direction orthogonal to the first direction, the third power source line having an electric potential (VSS) equivalent to that of the second power source line; a fourth power source line (POR1) disposed to be adjacent to and in parallel to the second power supply line in a negative direction of the second direction, the fourth power source line having an electric potential equivalent to that of the first power source line (VDD); a first transistor (PMOS) disposed below the first power supply line, first transistor including a first conductivity-type first active region (PR2) extending in the second direction and the negative direction of the second direction; a second transistor (NMOS) disposed below the second power source line, the second transistor including a second conductivity-type second active region (NR1) extending in the second direction and the minus direction of the second direction; a third transistor (NMOS) disposed between the first active region and the third power source line, the third transistor including a second conductivity-type third active region (NR2); and a fourth transistor (PMOS) disposed between the second active region and the fourth power source line, the fourth transistor including a first conductivity-type fourth active region (PR1), wherein the first active region overlaps with the first power source line when viewed from a normal direction normal to a plane extending in the first and second directions, and the second active region overlaps with the second power source line when viewed from the normal direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Tanaka, as taught by Kim. The ordinary artisan would have been motivated to modify Tanaka in the above manner for purpose of high reliability, high speed and multi-functionality ([0003] of Kim).
Regarding Claim 9
FIG. 5 of Kim discloses with respect to the substrate, the first common electrode (AC3) is disposed as a first metal layer, and the first power supply line, the second power source line, the third power source line, and the fourth power source line are disposed as a second metal layer.
Regarding Claim 13
FIG. 4 of Kim discloses a first control electrode (GE) disposed to extend in the second direction on the first active region, the second active region, the third active region, and the fourth active region.
Regarding Claim 14
FIG. 4 of Kim discloses a third control electrode which are disposed to be adjacent to and in parallel to the first control electrode so as to extend in the second direction.
Claim 2 rejected under 35 U.S.C. 103 as being unpatentable over Tanaka and Kim, in view of Kinoshita (U.S. Patent Pub. No. 2006/0131609) of record.
Regarding Claim 2
Tanaka as modified by Kim discloses Claim 1, further comprising: a substrate [0004].
Tanaka as modified by Kim is silent with respect to “a second conductivity-type first well region disposed on the substrate, the first well region including the first active region; a first conductivity-type second well region disposed on the substrate, the second well region including the second active region; a first conductivity-type third well region disposed on the substrate, the third well region including the third active region; and a second conductivity-type fourth well region disposed on the substrate, the fourth well region including the fourth active region”.
FIGS. 1-2 of Kinoshita disclose a similar semiconductor integrated circuits, comprising a second conductivity-type first well region (NWELL) disposed on the substrate, the first well region including the first active region (PSD); a first conductivity-type second well region (PWELL) disposed on the substrate, the second well region including the second active region (NSD); a first conductivity-type third well region disposed on the substrate, the third well region including the third active region; and a second conductivity-type fourth well region disposed on the substrate, the fourth well region including the fourth active region.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Tanaka, as taught by Kinoshita. The ordinary artisan would have been motivated to modify Tanaka in the above manner for purpose of taking measures against the fluctuations ([0011] of Kinoshita).
Claims 15 and 16 rejected under 35 U.S.C. 103 as being unpatentable over Tanaka and Kim, in view of Hart (U.S. Patent No. 8,351,248) of record.
Regarding Claim 15
Tanaka as modified by Kim discloses Claim 1.
Tanaka as modified by Kim is silent with respect to “gate widths of the first transistor and the second transistor are greater than gate widths of the third transistor and the fourth transistor”.
FIG. 5 of Hart discloses a similar semiconductor integrated circuit, wherein gate widths of the first transistor and the second transistor are greater than gate widths of the third transistor and the fourth transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Tanaka, as taught by Hart. The ordinary artisan would have been motivated to modify Tanaka in the above manner for purpose of minimizing the layout of an ESD protection device (Abstract of Hart).
Regarding Claim 16
FIG. 5 of Hart discloses the gate widths of the first transistor and the second transistor are approximately 3 times larger than the gate widths of the third transistor and the fourth transistor. Furthermore, said ratio is related to the current and device size (Col. 2, Lines 30-40 of Hart). Therefore, said ratio is considered to be a result effective variable. The claim to a specific ratio therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Claim 17 rejected under 35 U.S.C. 103 as being unpatentable over Tanaka, Kim and Kinoshita, in view of Ham (KR 19980033872) of record.
Regarding Claim 17
Tanaka as modified by Kim and Kinoshita discloses Claim 2.
Tanaka as modified by Kim and Kinoshita is silent with respect to “the first active region is disposed on the first well region, the second active region is disposed on the second well region, the third active region is disposed on the third well region, and the fourth active region is disposed on the fourth well region”.
FIG. 2 of Ham discloses a similar semiconductor integrated circuit, wherein the first active region is disposed on the first well region, the second active region is disposed on the second well region, the third active region is disposed on the third well region, and the fourth active region is disposed on the fourth well region.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Tanaka, as taught by Ham. The ordinary artisan would have been motivated to modify Tanaka in the above manner for purpose of minimizing the layout of an ESD protection device (Abstract of Ham).
Pertinent Art
US 20080023792 discloses the first active region overlaps with the first power source line when viewed from a normal direction normal to a plane extending in the first and second directions, and the second active region overlaps with the second power source line when viewed from the normal direction. CN 104142591 discloses the first common electrode is disposed as a first metal layer, and the first power supply line, the second power source line, the third power source line, and the fourth power source line are disposed as a second metal layer. US 20100090283 discloses the first active region is disposed on the first well region, the second active region is disposed on the second well region, the third active region is disposed on the third well region, and the fourth active region is disposed on the fourth well region.
Response to Arguments
Applicant’s arguments with respect to Claim 1 have been considered but they are not persuasive. FIG. 14 of Tanaka discloses a first common electrode (38) connecting the first active region, the second active region, the third active region, and the fourth active region. FIG. 7 of Tanaka discloses an alternative embodiment, wherein the first active region overlaps with the first power source line when viewed from a normal direction normal to a plane extending in the first and second directions. It would have been obvious to one of ordinary skill in the art that to modify FIG. 14 of Tanaka such that the second active region overlaps with the second power source line when viewed from the normal direction, because said configuration was a matter of choice, as evidenced by various embodiments of Tanaka, which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant. In re Dailey 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton 97 US 3,24 (USSC 1878). MPEP 2144.04. FIG. 3 of Kim is used to modify Tanaka such that the first active region overlaps with the first power source line when viewed from a normal direction normal to a plane extending in the first and second directions, and the second active region overlaps with the second power source line when viewed from the normal direction. One of ordinary skill in the art would have been motivated to modify Tanaka in the above manner for purpose of high reliability, high speed and multi-functionality ([0003] of Kim).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897