DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 1/27/2025, responding to the Office action mailed on 10/27/2025, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1- 20 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 20220271171 A1) in view of Ko et al. (KR 20220091756 A).
Re Claim 1 Su teaches an integrated circuit (FIG. 19) comprising:
Su teaches a first semiconductor body (222) [0027] and a second semiconductor body (222) each extending lengthwise in a first direction (horizontal) between a first epitaxial region (310) [0040] and a second epitaxial region (310), the first semiconductor body (222) over the second semiconductor body (222) in a second direction (vertical);
a gate structure (340, 350) [0045] at least partially around the first and second semiconductor bodies (222); and
a spacer structure (301) [0038] comprising a first inner spacer (301) adjacent to an end sidewall of the first semiconductor body (222) and a second inner spacer (301) adjacent to an end sidewall of the second semiconductor body (222), wherein the end sidewall of the first semiconductor body (222) is laterally inward of an outermost sidewall of the first inner spacer (301), and the end sidewall of the second semiconductor body (222) is laterally inward of an outermost sidewall of the second inner spacer (301).
Modified FIG. 19 shown below
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Su does not teach the second inner spacer is wider than the first inner spacer along the first direction.
Ko teaches the second inner spacer (131, page 3 par 6) is wider than the first inner spacer (132) along the first direction (see image below, boxes are inner spacers are the same size, 2nd spacer is wider in second/horizontal direction).
Modified FIG. 13 shown below
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It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Ko into the structure of Su since Ko teaches a gate all around transistor.
The ordinary artisan would have been motivated to modify Ko in combination with Su in the above manner for the motivation of optimally forming the inner spacers to help suppress a short channel effect to help optimize the drain voltage. Page 3 par 3 states, “…it is possible to effectively suppress a short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage.” A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Re Claim 3 Su in view of Ko teaches the integrated circuit of claim 1, wherein the second epitaxial regions (Su, 310) has a protruding portion and an indented portion, the protruding portion laterally extending toward the gate structure (340, 350) and between the first inner spacer (301) and the second inner spacer (301), and the indented portion having the second inner spacer (301) extending therein (see Su modified FIG. 19 under claim 1).
Re Claim 4 Su in view of Ko teaches the integrated circuit of claim 1, wherein the spacer structure is a first spacer structure (Su, 301) on one side of the gate structure (340, 350), and the integrated circuit further comprises a second spacer structure (301) on an opposite side of the gate structure (340, 350), the second spacer structure extending in the second direction (vertical) around opposite ends of the first and second semiconductor bodies (222, see Su modified FIG. 19 under claim 1).
Re Claim 5 Su in view of Ko teaches the integrated circuit of claim 1, wherein portions of the first epitaxial region (Su, 310) contact the end sidewalls of the first and second semiconductor bodies (222), such that the spacer structure (301) extends in the second direction (vertical) around the portions of the first epitaxial region (310, see Su modified FIG. 19 under claim 1).
Re Claim 6 Su in view of Ko teaches the integrated circuit of claim 1, but does not explicitly teach the first inner spacer has a lateral thickness in the first direction between 3 nm and 5 nm, and the second inner spacer has a lateral thickness in the first direction between 6 nm and 10 nm.
Ko page 6 par 3 states, “…gate insulating layer111 may include a ferroelectric material layer…”, and page 7 par 6 states, “…the ferroelectric material layer may be, for example, 0.5 to 10 nm…” Use 1.25 nm for 111 from FIG. 19. The first inner spacer 132 is roughly 4x the length of 111 in the first/horizontal direction, and the second inner spacer 131 is roughly 20% longer than 132 in the first/horizontal direction. Therefore, the lateral thickness in the first direction for the first inner spacer is about 5nm, and the lateral thickness in the first direction for the second inner spacer is about 6nm.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Ko into the structure of Su in view of Ko.
The ordinary artisan would have been motivated to modify Ko in combination with Su in view of Ko in the above manner for the motivation of finding optimal inner spacer lateral thickness in the first direction. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach optimal inner spacer lateral thickness.
Re Claim 7 Su in view of Ko teaches the integrated circuit of claim 1, but does not explicitly teach the end sidewalls of the first and second semiconductor bodies are offset from the outermost sidewalls of the first and second inner spacers, respectively, by between 2 nm and 4 nm.
Su does teach in [0002], “Each of the nanosheets may have a thickness in a scale ranging from, e.g., about 1 nanomter (nm) to about 100 nm.” The nanosheet thickness can be set to have the spacers and nanosheets ends are laterally offset by 2nm to 4nm.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Su into the structure of Su in view of Ko.
The ordinary artisan would have been motivated to modify Su in combination with Su in view of Ko in the above manner for the motivation of finding optimal length to have the epitaxial regions extend into the spacer regions. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach optimal epitaxial region lengths into the spacers.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 20220271171 A1) in view of Ko et al. (KR 20220091756 A) as applied to claim 1 above, and further in view of Rachmady et al. (US 20200098757 A1).
Re Claim 2 Su in view of Ko teaches the integrated circuit of claim 1, wherein the first and second semiconductor bodies (Su, 222) comprise germanium, silicon [0027], or any combination thereof.
Su in view of Ko does not teach the first and second semiconductor bodies are nanoribbons.
Rachmady teaches the first and second semiconductor bodies (132) [0032] are nanoribbons [0033] (FIG. 1).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Rachmady into the structure of Su in view of Ko since both applications are transistors with similar architecture between them.
The ordinary artisan would have been motivated to modify Rachmady in combination with Su in view of Ko in the above manner for the motivation of using nanoribbons for the semiconductor bodies to optimize the voltage and current in the semiconductor device. [0028] states , “In general, the techniques allow transistors to be further scaled with diverse channel materials, while ensuring higher operating voltage, higher drive currents, and thereby improved performance.”
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Su (US 20220271171 A1) in view of Ko et al. (KR 20220091756 A) as applied to claim 1 above, and further in view of Lilak et al. (US 20200098756 A1).
Re Claim 8 Su in view of Ko does not teach a printed circuit board comprising the integrated circuit of claim 1.
Lilak teaches a printed circuit board (1002) [0097] comprising the integrated circuit (1006) [0099] of claim 1 (FIG. 13).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Lilak into the structure of Su in view of Ko since both patents are about semiconductor devices with epitaxial source/drain regions.
The ordinary artisan would have been motivated to modify Lilak in combination with Su in view of Ko in the above manner for the motivation of putting the chip onto a circuit board, so the chip can communicate with a computing system. [0099] states, “The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000.”
Claims 9-13 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 20220271171 A1) in view of Rachmady et al. (US 20200098757 A1) and Ko et al. (KR 20220091756 A).
Re Claim 9 Su teaches an electronic device (FIG. 19), comprising:
a chip package comprising one (200) [0025] or more dies, at least one of the one or more dies comprising a plurality of semiconductor nanosheets (222) [0027] extending lengthwise in a first direction (horizontal) between a first epitaxial region (310) and a second epitaxial region (310);
a gate structure (340,350) [0045] around the plurality of semiconductor nanosheets (222), the plurality of semiconductor nanosheets being over one another in a second (vertical) direction; and
a spacer structure (301) [0038] comprising a first inner spacer adjacent (301) to an end sidewall of a first nanosheet (222) of the plurality of semiconductor nanosheets, and a second inner spacer (301) adjacent to an end sidewall of a second nanosheet (222) of the plurality of semiconductor nanosheets, the first nanosheet (222) being over the second nanosheet (222) in the second direction (vertical), wherein the end sidewall of the first nanosheet (222) is laterally offset from an outermost sidewall of the first inner spacer (301), and the end sidewall of the second nanosheet (222) is laterally offset from an outermost sidewall of the second nanosheet (222, see modified FIG. 19 below).
Modified FIG. 19 shown below
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Su does not teach a plurality of semiconductor nanoribbons
Rachmady teaches a plurality of semiconductor nanoribbons (132, FIG. 1) [0033].
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Rachmady into the structure of Su since both applications are transistors with similar architecture between them.
The ordinary artisan would have been motivated to modify Rachmady in combination with Su in the above manner for the motivation of using nanoribbons to optimize the voltage and current in the semiconductor device. [0028] states , “In general, the techniques allow transistors to be further scaled with diverse channel materials, while ensuring higher operating voltage, higher drive currents, and thereby improved performance.”
Su in view of Rachmady does not teach the second inner spacer is wider than the first inner spacer along the first direction.
Ko teaches the second inner spacer (131, page 3 par 6) is wider than the first inner spacer (132) along the first direction (see image below, boxes around inner spacers are the same size, 2nd spacer is wider in second/horizontal direction than the 1st spacer).
Modified FIG. 13 shown below
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It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Ko into the structure of Su in view of Rachmady since Ko teaches a gate all around transistor.
The ordinary artisan would have been motivated to modify Ko in combination with Su in view of Rachmady in the above manner for the motivation of optimally forming the inner spacers to help suppress a short channel effect to help optimize the drain voltage. Page 3 par 3 states, “…it is possible to effectively suppress a short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage.” A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Re Claim 10 Su in view of Rachmady and Ko teaches the electronic device of claim 9, wherein the spacer structure is a first spacer structure (Su, 301) on one side of the gate structure (340,350), and the at least one of the one or more dies (200) further comprises a second spacer (301) structure on an opposite side of the gate structure (340, 350), the second spacer structure extending in the second (vertical) direction around opposite ends of the semiconductor nanoribbons (222, see modified FIG. 19 under claim 9, and nanoribbons taught by Rachmady).
Re Claim 11 Su in view of Rachmady and Ko teaches the electronic device of claim 10, wherein the opposite ends of the semiconductor nanoribbons (Su, 222) are laterally recessed from an outermost sidewall of the second spacer structure (301, see modified FIG. 19 under claim 9).
Re Claim 12 Su in view of Rachmady and Ko teaches the electronic device of claim 9, wherein the end sidewalls of the first and second semiconductor nanoribbons (Su, 222) are substantially aligned along the second direction (vertical, FIG. 19).
Re Claim 13 Su in view of Rachmady and Ko teaches the electronic device of claim 9, wherein portions of the first epitaxial region (Su, 310) contact the end sidewalls of the first and second nanoribbons (222),
such that the spacer structure (301) extends in the second direction (vertical) around the portions of the first epitaxial region (310, FIG. 19).
Re Claim 15 Su teaches an integrated circuit comprising:
a plurality of semiconductor nanosheets (222) [0027] extending lengthwise in a first direction (horizontal) between a first epitaxial region (310) [0040] and a second epitaxial region (310), the plurality of semiconductor nanosheets (222) being over one another in a second direction (vertical);
a first inner spacer (301) [0038] adjacent to an end sidewall of a first nanosheets (222) of the plurality of semiconductor nanosheets (222);
a second inner spacer (301) adjacent to an end sidewall of a second nanosheet (222) of the plurality of semiconductor nanosheets, the first nanosheet being over the second nanosheet (vertically); and
a gate structure (340,350) [0045] around the plurality of semiconductor nanosheets (222);
wherein a first portion of the first epitaxial region (310) extends laterally in the first direction (horizontal) to contact the end sidewall of the first nanosheets (222) and also contacts a top surface of the first inner spacer (301), and a second portion of the first epitaxial region (310) extends laterally in the first direction (horizontal) to contact the end sidewall of the second nanosheet (222) and also contacts a top surface of the second inner spacer (301, see modified FIG. 19 under claim 9).
Su does not teach a plurality of semiconductor nanoribbons.
Rachmady teaches a plurality of semiconductor nanoribbons (132, FIG. 1) [0033].
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Rachmady into the structure of Su since both applications are transistors with similar architecture between them.
The ordinary artisan would have been motivated to modify Rachmady in combination with Su in the above manner for the motivation of using nanoribbons for the channel layers in the semiconductor device. [0028] states , “In general, the techniques allow transistors to be further scaled with diverse channel materials, while ensuring higher operating voltage, higher drive currents, and thereby improved performance.”
Su in view of Rachmady does not teach the second inner spacer is wider than the first inner spacer along the first direction.
Ko teaches the second inner spacer (131, page 3 par 6) is wider than the first inner spacer (132) along the first direction (see modified FIG. 13 under claim 9, boxes around inner spacers are the same size, 2nd spacer is wider in second/horizontal direction than the 1st spacer).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Ko into the structure of Su in view of Rachmady since Ko teaches a gate all around transistor.
The ordinary artisan would have been motivated to modify Ko in combination with Su in view of Rachmady in the above manner for the motivation of optimally forming the inner spacers to help suppress a short channel effect to help optimize the drain voltage. Page 3 par 3 states, “…it is possible to effectively suppress a short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage.” A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Re Claim 16 Su in view of Rachmady and Ko teaches the integrated circuit of claim 15, wherein the first portion (see drawing below) of the first epitaxial region (Su, 310) and the second portion of the first epitaxial region (310) are aligned over one another in the second direction (vertical).
Modified Su FIG. 19 shown below
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Re Claim 17 Su in view of Rachmady and Ko teaches the integrated circuit of claim 15, wherein the end sidewall of the first nanoribbons (Su, 222, and nanoribbons taught by Rachmady) is laterally recessed from an outermost sidewall of the first inner spacer (Su, 301), and the end sidewall of the second nanoribbons (222) is laterally recessed from an outermost sidewall of the second inner spacer (301, see modified FIG. 19 below claim 9).
Re Claim 18 Su in view of Rachmady and Ko teaches the integrated circuit of claim 15, but does not explicitly teach the first inner spacer has a lateral thickness in the first direction between about 3 nm and about 5 nm and the second inner spacer has a lateral thickness in the first direction between about 6 nm and about 10 nm.
Ko page 6 par 3 states, “…gate insulating layer111 may include a ferroelectric material layer…”, and page 7 par 6 states, “…the ferroelectric material layer may be, for example, 0.5 to 10 nm…” Use 1.25 nm for 111 from FIG. 19. The first inner spacer 132 is roughly 4x the length of 111 in the first/horizontal direction, and the second inner spacer 131 is roughly 20% longer than 132 in the first/horizontal direction. Therefore, the lateral thickness in the first direction for the first inner spacer is about 5nm, and the lateral thickness in the first direction for the second inner spacer is about 6nm.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Ko into the structure of Su in view of Rachmady and Ko.
The ordinary artisan would have been motivated to modify Ko in combination with Su in view of Rachmady and Ko in the above manner for the motivation of finding optimal inner spacer lateral thickness in the first direction. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach optimal inner spacer lateral thickness.
Re Claim 19 Su in view of Rachmady and Ko teaches the integrated circuit of claim 15, but does not explicitly teach the first and second portions of the first epitaxial region extend laterally in the first direction by between about 2 nm and about 4 nm.
Su does teach in [0002], “Each of the nanosheets may have a thickness in a scale ranging from, e.g., about 1 nanomter (nm) to about 100 nm.” The nanosheet thickness can be set to have the spacers and nanosheets ends are laterally offset by 2nm to 4nm.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Su into the structure of Su in view of Rachmady and Ko.
The ordinary artisan would have been motivated to modify Su in combination with Su in view of Rachmady and Ko in the above manner for the motivation of finding optimal length to have the epitaxial regions extend into the spacer regions. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach optimal epitaxial region lengths into the spacers.
Claims 14 and 20 and rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 20220271171 A1) in view of Rachmady et al. (US 20200098757 A1) and Ko et al. (KR 20220091756 A) as applied to claims 9 and 15, and further in view of Lilak et al. (US 20200098756 A1).
Re Claim 14 Su in view of Rachmady and Ko teaches the electronic device of claim 9, but does not teach a printed circuit board, wherein the chip package is attached to the printed circuit board.
Lilak teaches a printed circuit board (1002) [0097], wherein the chip package (1006) [0099] is attached to the printed circuit board (1002, FIG. 13).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Lilak into the structure of Su in view of Rachmady and Ko since Lilak and Su are about semiconductor devices with epitaxial source/drain regions.
The ordinary artisan would have been motivated to modify Lilak in combination with Su in view of Rachmady and Ko in the above manner for the motivation of putting the chip onto a circuit board, so the chip can communicate with a computing system. [0099] states, “The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000.”
Re Claim 20 Su in view of Rachmady and Ko does not teach a printed circuit board comprising the integrated circuit of claim 15.
Lilak teaches a printed circuit board (10g02) [0097] comprising the integrated circuit (1006) [0099] of claim 15 (FIG. 13).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Lilak into the structure of Su in view of Rachmady and Ko since Lilak and Su are about semiconductor devices with epitaxial source/drain regions.
The ordinary artisan would have been motivated to modify Lilak in combination with Su in view of Rachmady and Ko in the above manner for the motivation of putting the chip onto a circuit board, so the chip can communicate with a computing system. [0099] states, “The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000.”
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 5/12/26
Prosecution Insights