DETAILED ACTION
This action is responsive to the application No. 17/940,195 filed on September 08, 2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 01/30/2026 responding to the Office action mailed on 10/31/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin (US 2023/0067988).
Regarding Claim 1, Lin (see, e.g., Figs. 16A-16B and Annotated Fig. 16A), teaches an integrated circuit comprising:
a first semiconductor material 206 extending between a first source region 260 and a first drain region 260 (see, e.g., pars. 0018, 0035);
a first subregion F1 below the first semiconductor material 206 (see, e.g., pars. 0016-0017);
a second semiconductor material 206 extending between a second source region 260 and a second drain region 260 (see, e.g., pars. 0018, 0035);
a second subregion F2 below the second semiconductor material 206 (see, e.g., pars. 0016-0017);
a dielectric fill 208 directly between the first subregion F1 and the second subregion F2, wherein the first semiconductor material 206 and the second semiconductor material 206 are above a top surface of the dielectric fill 208 (see, e.g., par. 0023);
a gate structure 294/296 extending over the first semiconductor material 206, the gate structure 294/296 comprising a gate dielectric 294 and a gate electrode 296 (see, e.g., par. 0046); and
a layer 292 directly on the top surface of the dielectric fill 208 and extending an entire distance between the first subregion F1 and the second subregion F2, wherein the gate dielectric 294 is on the layer 292 and has a different material composition than the layer 292 (see, e.g., par. 0046).
Regarding Claim 2, Lin teaches all aspects of claim 1. Lin (see, e.g., Figs. 16A-16B and Annotated Fig. 16A), teaches that the firs semiconductor material 206 comprises one or more first nanoribbons and the second semiconductor material 206 comprises one or more second nanoribbons (see, e.g., pars. 0002, 0013, 0019).
Regarding Claim 3, Lin teaches all aspects of claim 2. Lin (see, e.g., Figs. 16A-16B and Annotated Fig. 16A), teaches that the one or more first and second nanoribbons comprise silicon, germanium, or a combination thereof (see, e.g., par. 0018).
Regarding Claim 9, Lin teaches all aspects of claim 1. Lin (see, e.g., Figs. 16A-16B and Annotated Fig. 16A), teaches that the gate dielectric 294 comprises high-k dielectric material (see, e.g., par. 0046).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2023/0067988) in view of Wang (US 2023/0395696).
Regarding Claim 4, Lin teaches all aspects of claim 1. Lin is silent with respect to the claim limitation that the layer comprises a metal and oxygen.
Lin discloses the claimed invention except for the use of silicon oxide for the layer instead of metal and oxygen (see, e.g., par. 0046). Wang (see, e.g., par. 0043), on the other hand teaches that aluminum oxide and silicon oxide are equivalent materials known in the art. Therefore, because these interfacial materials were art-recognized equivalents at the time of the invention, one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to substitute aluminum oxide for silicon oxide since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007).
Regarding Claim 5, Jung teaches all aspects of claim 1. Jung is silent with respect to the claim limitation that the layer comprises oxygen and any one of aluminum, titanium, or zinc.
Lin discloses the claimed invention except for the use of silicon oxide for the layer instead of oxygen and aluminum (see, e.g., par. 0046). Wang (see, e.g., par. 0043), on the other hand teaches that aluminum oxide and silicon oxide are equivalent materials known in the art. Therefore, because these interfacial materials were art-recognized equivalents at the time of the invention, one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to substitute aluminum oxide for silicon oxide since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2023/0067988) in view of Wen (US 2019/0157159).
Regarding Claim 6, Lin teaches all aspects of claim 1. Lin does not show a gate cut through a portion of the gate structure, the gate cut interrupting the gate structure between the first semiconductor material and the second semiconductor material, wherein the gate cut comprises a dielectric material.
Wen (see, e.g., Fig. 13), on the other hand, teaches a gate cut 114 through a portion of the gate structure 112, the gate cut 114 interrupting the gate structure 112 between the first semiconductor material 104 and the second semiconductor material 104, wherein the gate cut 114 comprises a dielectric material. The metal gate is cut into two or more portions and each portion functions as a metal gate for an individual transistor (see, e.g., pars. 0010-0012).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Lin’s device, a gate cut through a portion of the gate structure, the gate cut interrupting the gate structure between the first semiconductor material and the second semiconductor material and comprising a dielectric material, as taught by Wen, to separate the metal gate into two or more portions, such that each portion functions as a metal gate for an individual transistor.
Regarding Claim 7, Lin and Wen teach all aspects of claim 6. Wen (see, e.g., Fig. 13), teaches that the gate cut 114 is on the layer 106 (see, e.g., par. 0011).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2023/0067988) in view of Mukherjee (US 2014/0070320).
Regarding Claim 10, Lin teaches all aspects of claim 1. Lin is silent with respect to the claim limitation of a printed circuit board.
Mukherjee (see, e.g., Figs. 10-11), on the other hand, teaches a printed circuit board and a component coupled to the board to achieve a mobile computing platform which employs logic and analog FinFETs (see, e.g., pars. 0039-0045).
It would have been obvious to one of ordinary skill in the art at the time of filing to include a printed board comprising the integrated circuit of Lin’s device, as taught by Mukherjee, to achieve a mobile computing platform which employs logic and analog FinFETs.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2023/0067988) in view of Mukherjee (US 2014/0070320) and Zhi-Chang (US 2023/0369456).
Regarding Claim 16, Lin (see, e.g., Figs. 16A-16B and Annotated Fig. 16A), teaches an electronic device, comprising:
at least one of the one or more dies comprising a first semiconductor material 206 extending between a first source region 260 and a first drain region 260 (see, e.g., pars. 0018, 0035);
a first subregion F1 below the first semiconductor material 206 and adjacent to a dielectric fill 208 (see, e.g., pars. 0018, 0023);
a second semiconductor material 206 extending between a second source region 260 and a second drain region 260 (see, e.g., pars. 0018, 0035);
a second subregion F2 below the second semiconductor material 206 and adjacent to the dielectric fill 208 (see, e.g., pars. 0018, 0023); and
a gate structure 294/296 extending over the first semiconductor material 206, the gate structure 294/296 comprising a gate electrode 296 and a gate dielectric 294 (see, e.g., par. 0046); and
a barrier layer 292 directly on the top surface of the dielectric fill 208 and extending an entire distance between the first subregion F1 and the second subregion F2, wherein the gate dielectric 294 is on the barrier layer 292 and has a different material composition than the barrier layer 292 (see, e.g., par. 0046).
Lin is silent with respect to the claim limitations of a chip package comprising one or more dies and that the barrier layer comprises oxygen and a metal. Mukherjee (see, e.g., Figs. 10-11), on the other hand, teaches a chip package comprising one or more dies, at least one of the one or more dies comprising a semiconductor device, to achieve a mobile computing platform which employs logic and analog FinFETs (see, e.g., pars. 0039-0045).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in the integrated circuit of Jung, a chip package comprising one or more dies, at least one of the one or more dies comprising a semiconductor device, as taught by Mukherjee, to achieve a mobile computing platform which employs logic and analog FinFETs.
Lin discloses the claimed invention except for the use of silicon oxide for the barrier layer instead of oxygen and a metal (see, e.g., par. 0046). Zhi-Chang (see, e.g., par. 0032), on the other hand teaches that aluminum oxide and silicon oxide are equivalent materials known in the art. Therefore, because these barrier materials were art-recognized equivalents at the time of the invention, one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to substitute aluminum oxide for silicon oxide since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007).
Regarding Claim 17, Lin, Mukherjee, and Zhi-Chang teach all aspects of claim 16. Zhi-Chang teaches that the metal of the barrier layer 128B comprises aluminum (see, e.g., par. 0032).
Regarding Claim 18, Lin, Mukherjee, and Zhi-Chang teach all aspects of claim 16. Lin (see, e.g., Figs. 16A-16B and Annotated Fig. 16A), teaches that the gate dielectric 294 is on the first semiconductor material 206 and the gate electrode 296 is on the gate dielectric 294.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2023/0067988) in view of Mukherjee (US 2014/0070320), Zhi-Chang (US 2023/0369456), and further in view of Wen (US 2019/0157159).
Regarding Claim 19, Lin, Mukherjee, and Zhi-Chang teach all aspects of claim 16. They do not teach that at least one of the one or more dies further comprises a gate cut structure, the gate cut structure interrupting the gate structure between the first semiconductor material and the second semiconductor material, wherein the gate cut structure comprises a dielectric material.
Wen (see, e.g., Fig. 13), on the other hand, teaches that at least one of the one or more dies further comprises a gate cut structure 114, the gate cut structure 114 interrupting the gate structure 112 between the first semiconductor material 104 and the second semiconductor material 104, wherein the gate cut structure 114 comprises a dielectric material. The metal gate is cut into two or more portions and each portion functions as a metal gate for an individual transistor (see, e.g., pars. 0010-0012).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Lin’s et. al., device, a gate cut structure, the gate cut structure interrupting the gate structure between the first semiconductor material and the second semiconductor material and comprising a dielectric material, as taught by Wen, to separate the metal gate into two or more portions, such that each portion functions as a metal gate for an individual transistor.
Allowable Subject Matter
Claims 11-15 are allowed.
Claims 8 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments filed on 01/30/2026 with respect to the rejection of claims 1 and 16 have been fully considered but are moot in view of the new grounds of rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nelson Garces/
Primary Examiner, Art Unit 2814