DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/01/2025 has been entered.
Claim Objections
Claim 1 is objected to because of the following informalities: line 10 recites: “a plurality of capacitors, each of the plurality of capacitors electrically connected…”. It is recommended to change the limitation to “a plurality of capacitors, each capacitor of the plurality of capacitors electrically connected…”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, lines 5-7 recite: “a plurality of first conductive patterns extending in a third direction, perpendicular to the first direction and the second direction, on the plurality of semiconductor patterns and intersecting the plurality of semiconductor patterns”. It is unclear how a plurality of first conductive patterns can be on the plurality of semiconductor patterns AND intersect the plurality of semiconductor patterns, since the claim also requires the plurality of first conductive patterns to extend in a direction perpendicular to an extension direction of the semiconductor patterns (intersect is understood as piercing or dividing by passing through or across).
Claim 11, lines 7-9 recite: “a capacitor spaced apart from the vertical conductive pattern in a second direction, parallel to the upper surface of the substrate interesting the first direction”. It is unclear what is meant by “a capacitor spaced apart from the vertical conductive pattern in a second direction, parallel to the upper surface of the substrate interesting the first direction”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, and 6, as best understood, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee in U.S. Patent Publication US 2021/0257366 (hereinafter, Lee).
Regarding claim 1, Lee teaches in FIG. 14 and related text, a semiconductor device (800, [0117]) comprising:
a plurality of semiconductor patterns (ACT, [0137]) stacked to be spaced apart from each other in a first direction (D1), perpendicular to an upper surface of a substrate (LS, [0039]), and extending in a second direction (D2), parallel to the upper surface of the substrate (LS);
a plurality of first conductive patterns (WL, [0138]) extending in a third direction (D3), perpendicular to the first direction (D1) and the second direction (D2), on the plurality of semiconductor patterns (ACT) and intersecting the plurality of intersecting patterns (ACT), respectively (intersecting inasmuch as shown in Applicant’s FIG. 3) ;
a second conductive pattern (BL/BR, [0120]/[0124]) extending in the first direction (D1) on the substrate (LS) and disposed to be adjacent to first end surfaces (right side surfaces) of the plurality of semiconductor patterns (ACT);
a plurality of capacitors (CAP, [0118]), each of the plurality of capacitors (CAP) electrically connected to a corresponding one of the plurality of semiconductor patterns (ACT; [0122]); and
at least one epitaxial layer (SD1/SD2, [0122]) disposed to be in contact with at least one of both end surfaces of at least one semiconductor pattern (ACT) of the plurality of semiconductor patterns (ACT) and including an impurity ([0122]).
wherein the at least one epitaxial layer (SD1/SD2) includes a plurality of first epitaxial layers (SD1) disposed between the first end surfaces of the plurality of semiconductor patterns (ACT) and the second conductive pattern (BL/BR),
wherein the plurality of first epitaxial layers (SD1) overlap the second conductive pattern (BL/BR) in the first direction (D1, noting “overlap” can mean to cover part of the same space, or to extend over or past and cover a part of), and
wherein the second conductive pattern (BL/BS) includes at least a first portion (see annotated FIG. 14 below) disposed above the plurality of first epitaxial layers (SD1) and at least a second portion disposed below the plurality of first epitaxial layers (SD1).
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Annotated FIG. 14 (Lee)
Regarding claim 2, Lee teaches the semiconductor device of claim 1, wherein the at least one epitaxial layer (SD1/SD2) has a facet shape grown according to a crystal orientation of a semiconductor material layer of the at least one semiconductor pattern (ACT).
One definition of a facet is a flat face on a geometric shape. As epitaxial layers SD1/SD2 are formed by epitaxial growth of the semiconductor layer ACT ([0122]), they necessarily share a crystal orientation of the semiconductor material from which they are grown. Thus, the epitaxial layers SD1/SD2 have a facet shape grown according to a crystal orientation of a semiconductor material layer of the semiconductor pattern (ACT).
Regarding claim 6, Lee teaches the semiconductor device of claim 1, wherein the at least one epitaxial layer (SD1/SD2) further includes:
a plurality of second epitaxial layers (SD2) disposed between second end surfaces of the plurality of semiconductor patterns (left end surfaces of ACT) and the plurality of capacitors (CAP).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 4, and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in U.S. Patent Publication US 2021/0257366 (hereafter, Lee) and in view of Rubin in U.S. Patent Application Publication 2020/0126987 (hereafter Rubin).
Regarding claim 3, Lee teaches the semiconductor device of claim 1. Lee does not teach:
wherein the at least one epitaxial layer (SD1) has a first side surface inclined with respect to an upper surface of the at least one semiconductor pattern (ACT) and a second side surface inclined with respect to a lower surface of the at least one semiconductor pattern (ACT).
Rubin teaches in Fig. 5 and related text (also refer to annotated Fig. 5 below): at least one epitaxial layer (270, [0059]) has a first side surface (annotated Fig. 5) inclined with respect to an upper surface (annotated Fig. 5) of a semiconductor pattern (N2/N4, annotated Fig. 5, [0035]) and a second side surface (annotated Fig. 5) inclined with respect to a lower surface (annotated Fig. 5) of a semiconductor pattern (N2/N4, annotated Fig. 5). Rubin’s epitaxial layers are grown in this manner and embedded into conductive contacts in order to decrease resistance ([0072]).
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Annotated Fig. 5 (Rubin)
Lee and Rubin are analogous art because they both are directed towards semiconductor device manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify the invention of Lee in view of Rubin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device as taught by Lee such that at least one epitaxial layer has a first side surface inclined with respect to an upper surface of the semiconductor pattern and a second side surface inclined with respect to a lower surface of the semiconductor pattern, as taught by Rubin, with the purpose of decreasing electrical resistance of the contact (Rubin, [0072]), since Lee is concerned at least with electrical resistance in the capacitance area ([Lee, 0012]) and bit line area (Lee, [0124]) and thus in the overall device.
Regarding claim 4, Lee as modified by Rubin teaches the semiconductor device of claim 3. Lee does not teach wherein an angle between the first side surface of the at least one epitaxial layer (SD1) and the upper surface of the at least one semiconductor pattern (ACT) is an obtuse angle, and
wherein an angle between the second side surface of the at least one epitaxial layer (SD1) and the lower surface of the at least one semiconductor pattern (ACT) is an obtuse angle.
Rubin teaches in Fig. 5 and related text (also refer to annotated Fig. 5 in the rejection of claim 3 above): wherein an angle between a first side surface (annotated Fig. 5) of at least one epitaxial layer (270, annotated Fig. 5) and an upper surface (annotated Fig. 5) of the semiconductor pattern (N2/N4) is an obtuse angle (annotated Fig. 5), and
wherein an angle between a second side surface (annotated Fig. 5) of at least one epitaxial layer (270, annotated Fig. 5) and a lower surface (annotated Fig. 5) of a semiconductor pattern (N2/N4) is an obtuse angle (annotated Fig. 5). Rubin’s epitaxial layers are grown in this manner and embedded into conductive contacts in order to decrease resistance ([0072]).
Lee and Rubin are analogous art because they both are directed towards semiconductor device manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify the invention of Lee in view of Rubin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device as taught by Lee such that an angle between the first side surface of the at least one epitaxial layer and the upper surface of the at least one semiconductor pattern is an obtuse angle, and wherein an angle between the second side surface of the at least one epitaxial layer and the lower surface of the at least one semiconductor pattern is an obtuse angle, as taught by Rubin, with the purpose of decreasing electrical resistance of the contact (Rubin, [0072]), since Lee is concerned at least with electrical resistance in the capacitance area ([Lee, 0012]) and bit line area (Lee, [0124]) and thus in the overall device.
Regarding claim 7, Lee teaches the semiconductor device of claim 6, further comprising:
a plurality of first metal-semiconductor compound layers (metal silicide layers included on BL, [0124]) disposed between the plurality of first epitaxial layers (SD1) and the second conductive pattern (BL/BR), respectively (metal silicide layers included on BL are disposed between BL and SD1).
Lee does not teach a plurality of second metal-semiconductor compound layers disposed between the plurality of second epitaxial layers (SD2) and the plurality of capacitors (CAP), respectively.
Rubin teaches in FIG. 6 and related text, a plurality of metal-semiconductor compound layers (275, [0068]) disposed on epitaxial layers (270, [0059]), in which the epitaxial layers (270) are embedded into conductive contacts (280/290, [0068]) in order to decrease resistance ([0072]).
Lee and Rubin are analogous art because they both are directed towards semiconductor device manufacturing, and one of ordinary skill in the art would have had a reasonable expectation of success to modify the invention of Lee in view of Rubin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device as taught by Lee to include a plurality of second metal-semiconductor compound layers disposed on the plurality of second epitaxial layers, as taught by Rubin, with the purpose of decreasing electrical resistance of the contact (Rubin, [0072]), since Lee is concerned at least with electrical resistance in the capacitance area ([Lee, 0012]) and bit line area (Lee, [0124]) and thus in the overall device.
Regarding claim 8, Lee teaches the semiconductor device of claim 1.
Lee does not teach that the second conductive pattern (BL/BS) has inclined inner side surfaces facing inclined side surfaces of the plurality of first epitaxial layers (SD1).
Rubin teaches in FIG. 6 and related text, a conductive pattern (290, [0068]) has inclined inner side surfaces facing inclined side surfaces of a plurality of epitaxial layers (270, [0062]). Rubin’s epitaxial layers (270) are embedded into the conductive pattern (290) in order to decrease resistance ([0072]).
Lee and Rubin are analogous art because they both are directed towards semiconductor device manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify the invention of Lee in view of Rubin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device as taught by Lee such that the second conductive pattern has inclined inner side surfaces facing inclined side surfaces of the plurality of first epitaxial layers, with the purpose of decreasing electrical resistance of the contact (Rubin, [0072]), since Lee is concerned at least with electrical resistance in the capacitance area ([Lee, 0012]) and bit line area (Lee, [0124]) and thus in the overall device.
Regarding claim 9, Lee teaches the semiconductor device of claim 6, wherein each of the plurality of capacitors (CAP) includes a first electrode (SN, [0123]), a dielectric layer (DE, [0123]) on the first electrode (SN), and a second electrode (PN/PL, [0123]) on the dielectric layer (DE), and
wherein the first electrode (SN) includes a portion protruding toward the second electrode (PN/PL).
Lee does not teach wherein first electrode (SN) covers an inclined side surface of a corresponding one of the plurality of second epitaxial layers (SD2).
Rubin teaches in FIG. 6 and related text, an electrode (280, [0068]) covers an inclined side surface of a corresponding one of a plurality of epitaxial layers (270, [0062]), in which the epitaxial layers (270) are embedded into the electrode (280) in order to decrease resistance ([0072]).
Lee and Rubin are analogous art because they both are directed towards semiconductor device manufacturing, and one of ordinary skill in the art would have had a reasonable expectation of success to modify the invention of Lee in view of Rubin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device as taught by Lee such that the first electrode covers an inclined side surface of a corresponding one of the plurality of second epitaxial layers, as taught by Rubin, with the purpose of decreasing electrical resistance of the contact (Rubin, [0072]), since Lee is concerned at least with electrical resistance in the capacitance area ([Lee, 0012]) and bit line area (Lee, [0124]) and thus in the overall device.
Claims 11-15 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in U.S. Patent Application Publication US 2021/0249415 (hereinafter Kang) and in view of Rubin in U.S. Patent Application Publication 2020/0126987 (hereinafter Rubin).
Regarding claim 11, Kang teaches in Fig. 34 and related text (also refer to annotated Fig. 34 below):
A semiconductor device (500, [0162]) comprising:
a plurality of structures (see annotated figure below) and a plurality of first insulating layers (206, [0162]) alternately stacked on a substrate (200, [0116]); and
a vertical conductive pattern (375/370, [0145]) extending vertically in a first direction (Z-direction), perpendicular to an upper surface of the substrate (200), on the substrate (200),
wherein each of the plurality of structures includes:
a capacitor (182/184/186, [0098], see annotated figure below) spaced apart from the vertical conductive pattern in a second direction (x), parallel to the upper surface of the substrate (200) intersecting the first direction (z), on the substrate (200);
a semiconductor pattern (117/115/119, [0161]/[0138]/[0144], see annotated figure below) extending in the second direction (x) including a first impurity region (119, [0144]) electrically connected to the vertical conductive pattern, a second impurity region (117, [0161]) electrically connected to the capacitor (182/184/186), and a channel region (115 formed from channel layer 270, [0138]) between the first impurity region (119) and the second impurity region (117);
a gate electrode (120, [0093]) disposed between the channel region (115) of the semiconductor pattern (117/115/119) and the plurality of first insulating layers (206), the gate electrode (206) intersecting the vertical conductive pattern (375/370) to extend in a third direction (in/out of plane of figure, see FIG. 4) intersecting the first direction (z) and the second direction (x);
a gate dielectric layer (140, [0093]) between the gate electrode (120) and the semiconductor pattern (117/115/119);
a gate capping layer (230, [0136]) between the gate electrode (120) and the vertical conductive pattern (375/370); and
a second insulating layer (410, [0162]) between the gate electrode (120) and the capacitor electrode (182/184/186).
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Annotated Fig. 34 (Kang)
Kang does not teach an epitaxial layer disposed to be in contact with the second impurity region (117) of the semiconductor pattern (117/115/119) and including an impurity having a concentration greater than both a concentration of the first impurity region (119) and a concentration of the second impurity region (117), and
wherein the capacitor (182/184/186) overlaps the epitaxial layer in the first direction (Z direction).
Rubin teaches (Figs. 3-6 and related text; also refer to annotated Fig. 6 below) epitaxial layers (270, Fig. 6, [0062]) disposed to be in contact with semiconductor patterns (N2/N4, [0063]), in which the epitaxial layers (270, Fig. 6) are in-situ doped with impurities ([0063]). Rubin further teaches the epitaxial layers (270) are thermally annealed, thereby injecting some of the impurities from the epitaxial layers into the semiconductor pattern N2/N4 to create impurity regions in the semiconductor pattern N/N4 ([0063], annotated Fig. 6 below), which would create an impurity concentration gradient between the epitaxial layers (270) and the semiconductor patterns (N2/N4). In other words, Rubin teaches an impurity concentration in the epitaxial layers (270) is greater than an impurity concentration of the first impurity region and an impurity concentration of the second impurity region (refer to annotated FIG. 6 below). Rubin’s epitaxial layers are grown in this manner and overlap conductive contacts (280/290, FIG. 6, [0068]) in order to decrease resistance ([0072]).
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Annotated Fig. 6 (Rubin)
Kang and Rubin are analogous art because they both are directed towards semiconductor device manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify the invention of Kang in view of Rubin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device as taught by Kang such that the at least one epitaxial layer, as taught by Rubin, is disposed to be in contact with the second impurity region of the semiconductor pattern and including an impurity having a concentration greater than both a concentration of the first impurity region and a concentration of the second impurity region, and wherein the capacitor overlaps the epitaxial layer in the first direction, with the purpose of decreasing electrical resistance of the contact (Rubin, [0072]), since Kang is concerned at least with electrical resistance in the bit line area (Kang, [0147]) and thus in the overall device.
Regarding claim 12, Kang as modified by Rubin teaches the semiconductor device of claim 11. Kang does not teach wherein the epitaxial layer has a cross-section having a triangle, a quadrangle, a pentagon, a hexagon, an octagon, a rhombus, a circle, or an ellipse.
However, Rubin teaches in Figs 3-6 an epitaxial layer (270, Fig. 6) has a cross-section having a triangle, a quadrangle, a pentagon, a hexagon, an octagon, a rhombus, a circle, or an ellipse. Rubin’s epitaxial layers (270) are grown in this manner and embedded into conductive contacts (280/290, FIG. 6, [0068]) in order to decrease resistance ([0072]).
Kang and Rubin are analogous art because they both are directed towards semiconductor device manufacturing, and one of ordinary skill in the art would have had a reasonable expectation of success to modify the invention of Kang in view of Rubin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device as taught by Kang such that the epitaxial layer has a cross-section having a triangle, a quadrangle, a pentagon, a hexagon, an octagon, a rhombus, a circle, or an ellipse, as taught by Rubin, with the purpose of decreasing electrical resistance of the contact (Rubin, [0072]), with the purpose of decreasing electrical resistance of the contact (Rubin, [0072]), since Kang is concerned at least with electrical resistance in the bit line area (Kang, [0147]) and thus in the overall device.
Regarding claim 13, Kang as modified by Rubin teaches the semiconductor device of claim 11. Kang does not teach wherein each of the plurality of structures further includes a metal-semiconductor compound layer surrounding a surface of the epitaxial layer.
However, Rubin teaches in Figs. 3-6: a metal-semiconductor compound layer (275, Fig. 6) surrounding a surface of an epitaxial layer (270, Fig. 6). Rubin’s epitaxial layers (270) are grown in this manner and embedded into conductive contacts (280/290, FIG. 6, [0068]) in order to decrease resistance ([0072]).
Kang and Rubin are analogous art because they both are directed towards semiconductor device manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify the invention of Kang in view of Rubin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device as taught by Kang such that each of the plurality of structures further includes a metal-semiconductor compound layer surrounding a surface of the epitaxial layer, as taught by Rubin, with the purpose of decreasing electrical resistance of the contact (Rubin, [0072]), since Kang is concerned at least with electrical resistance in the bit line area (Kang, [0147]) and thus in the overall device.
Regarding claim 14, Kang as modified by Rubin teaches the semiconductor device of claim 11. Kang does not teach wherein a length between an upper end and a lower end of the epitaxial layer is longer than a length between an upper surface and a lower surface of the semiconductor pattern in the first direction.
However, Rubin teaches in Figs. 3-6 (also refer to annotated Fig. 5 below): a length between an upper end and a lower end of an epitaxial layer (270, annotated Fig. 5) is longer than a length between an upper surface and a lower surface of a semiconductor pattern (N2/N4, annotated Fig. 5) in the first direction. Rubin’s epitaxial layers (270) are grown in this manner and embedded into conductive contacts (280/290, FIG. 6, [0068]) in order to decrease resistance ([0072]).
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Annotated Fig. 5 (Rubin).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have constructed the epitaxial layer such that a length between an upper end and a lower end of the epitaxial layer is longer than a length between an upper surface and a lower surface of the semiconductor pattern in the first direction, as taught by Rubin. Although the drawings are not to scale, they may be relied upon for what they would reasonably teach one of ordinary skill in the art when interpreted in view of the specification. (MPEP 2125(II); In re Wright, 569 F.2d 1124, 1127-28, 193 USPQ 332, 335-36 (CCPA 1977)).
Regarding claim 15, Kang as modified by Rubin teaches the semiconductor device of claim 11. Kang does not teach wherein the epitaxial layer includes an impurity, and wherein the impurity includes at least one of P, As, B, C, and Ga.
However, Rubin teaches an epitaxial layer (270, Fig. 6, [0062]) includes an impurity [0063]), and
wherein the impurity includes at least one of P, As, B, C, and Ga ([0063] teaches B, Ph, and As). Rubin’s impurity-doped epitaxial layers (270) are grown in this manner and embedded into conductive contacts (280/290, FIG. 6, [0068]) in order to decrease resistance ([0072]).
Kang and Rubin are analogous art because they both are directed towards semiconductor device manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify the invention of Kang in view of Rubin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device as taught by Kang such that the epitaxial layer includes an impurity including at least one of P, As, and B, as taught by Rubin, with the purpose of decreasing electrical resistance of the contact (Rubin, [0072]), since Kang is concerned at least with electrical resistance in the bit line area (Kang, [0147]) and thus in the overall device.
Regarding claim 17, Kang as modified by Rubin teaches the semiconductor device of claim 11. Kang does not teach wherein the epitaxial layer extends from the second impurity region.
Rubin teaches in Figs. 3-6 and related text, an epitaxial layer (270, Fig. 6, [0062]) extends from an impurity region (see annotated Fig. 6 in the rejection of claim 11). Rubin’s epitaxial layers (270) are grown embedded the electrode 280 in order to decrease resistance ([0072]).
Kang and Rubin are analogous art because they both are directed towards semiconductor device manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify the invention of Kang in view of Rubin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device as taught by Kang such that the epitaxial layer extends from the second impurity region, as taught by Rubin, with the purpose of decreasing electrical resistance of the contact (Rubin, [0072]), since Kang is concerned at least with electrical resistance in the bit line area (Kang, [0147]) and thus in the overall device.
Regarding claim 18, Kang as modified by Rubin teaches the semiconductor device of claim 11. Kang does not explicitly teach wherein each of the first insulating layers (206) extends to be longer than the second insulating layer (410) horizontally.
However Kang appears to teach in FIG. 34 wherein each of the first insulating layers (206) extends to be longer than the second insulating layer (410) horizontally. Kang also teaches layer 410 “occupies less than 25%, 20%, 10% or 5% of the area between” layers 115 and 186. It would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have created each of the first insulating layers extending to be longer than the second insulating layer horizontally, as taught by Kang. Although the drawings are not to scale, they may be relied upon for what they would reasonably teach one of ordinary skill in the art when interpreted in view of the specification. (MPEP 2125(II); In re Wright, 569 F.2d 1124, 1127-28, 193 USPQ 332, 335-36 (CCPA 1977)).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in U.S. Patent Application Publication US 2021/0249415 (hereinafter Kang) and in view of Rubin in U.S. Patent Application Publication 2020/0126987 (hereinafter Rubin).
Regarding claim 19, Kang teaches in Fig. 34 and related text, a semiconductor device (500, [0162]) comprising:
a semiconductor pattern (117/115/119, [0161]/[0138]/[0144]) extending in a first direction (x-direction) parallel to an upper surface of a substrate (200, [0116]) and stacked to be spaced apart from each other (spaced apart in z-direction) on the substrate (200);
a first conductive pattern (120, [0093]) intersecting the semiconductor pattern (117/115/119; intersecting inasmuch as shown in Applicant’s FIG. 3) and extending in a second direction (in/out of plane of the figure, see FIG. 4), perpendicular to the first direction (x-direction);
a second conductive pattern (375/370, [0145]) extending in a third direction (z) perpendicular to the first direction (x) and the second direction (in/out of plane of figure) on the substrate (200) and disposed to be adjacent to a first end surface of the semiconductor pattern (117/115/119, see annotated FIG. 34 below);
a capacitor (182/184/186, [0098]) electrically connected the semiconductor pattern (117/115/119),
wherein the second conductive pattern (375/370) includes a first portion (see annotated FIG. 34 below), and a second portion (annotated FIG. 34 below).
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Annotated FIG. 34 (Kang)
Kang does not explicitly teach an epitaxial layer extending from the first end surface of the semiconductor pattern (117/115/119) and having a vertical thickness thicker than a vertical thickness of the semiconductor pattern (117/115/119); and a metal-semiconductor compound layer surrounding a surface of the epitaxial layer, wherein the second conductive pattern (375/370) includes a first portion disposed above the epitaxial layer and overlapping the epitaxial layer in the third direction, and a second portion disposed below the epitaxial layer and overlapping the epitaxial layer in the third direction.
However, Rubin teaches in Figs. 3-6: an epitaxial layer (270, [0062], Fig. 5) extending from a first end surface of a semiconductor pattern (N2/N4, [0060], Fig. 5) and having a vertical thickness thicker than a vertical thickness of the semiconductor pattern (N2/N4; see annotated Fig. 5 above in the rejection of claim 14); and
a metal-semiconductor compound layer (275, Fig. 6, [0068]) surrounding a surface of the epitaxial layer (270, Fig. 6),
wherein a conductive pattern (280, FIG. 6, [0068]) includes a first portion disposed above the epitaxial layer (270) and overlapping the epitaxial layer (270) in the vertical direction, and a second portion disposed below the epitaxial layer (270) and overlapping the epitaxial layer (270) in the vertical direction. Rubin’s epitaxial layers (270) are grown embedded the electrode 280 in order to decrease resistance ([0072]).
Kang and Rubin are analogous art because they both are directed towards semiconductor device manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify the invention of Kang in view of Rubin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device as taught by Kang to include an epitaxial layer extending from the first end surface of the semiconductor pattern and having a vertical thickness thicker than a vertical thickness of the semiconductor pattern, and a metal-semiconductor compound layer surrounding a surface of the epitaxial layer, wherein the second conductive pattern includes a first portion disposed above the epitaxial layer and overlapping the epitaxial layer in the third direction, and a second portion disposed below the epitaxial layer and overlapping the epitaxial layer in the third direction, as taught by Rubin, since Kang is concerned at least with electrical resistance in the bit line area (Kang, [0147]) and thus in the overall device. Although the drawings are not to scale, they may be relied upon for what they would reasonably teach one of ordinary skill in the art when interpreted in view of the specification. (MPEP 2125(II); In re Wright, 569 F.2d 1124, 1127-28, 193 USPQ 332, 335-36 (CCPA 1977)).
Regarding claim 20, Kang as modified by Rubin teaches the semiconductor device of claim 19. Kang further teaches in wherein the semiconductor pattern (117/115/119) includes a channel region (115) overlapping the first conductive pattern (120) and a first impurity region (119) and a second impurity region (115) disposed on sides of the channel region (115).
Kang does not teach wherein the epitaxial layer includes an impurity, and
wherein an impurity concentration of the epitaxial layer is greater than an impurity concentration of the first impurity region and an impurity concentration of the second impurity region.
Rubin teaches an epitaxial layer (270) includes an impurity ([0063]), and wherein an impurity concentration of the epitaxial layer (270) is greater than an impurity concentration of the first impurity region and an impurity concentration of the second impurity region (refer to annotated FIG. 6 in the rejection of claim 11 above). Rubin teaches epitaxial layers (270, Fig. 6, [0062]) are in-situ doped with impurities ([0063]). Rubin further teaches the epitaxial layers (270) are thermally annealed, thereby injecting some of the impurities from the epitaxial layers into the semiconductor pattern N2/N4 to create impurity regions in the semiconductor pattern N/N4 ([0063], see annotated FIG. 6 in the rejection of claim 11 above), which would create an impurity concentration gradient between the epitaxial layers (270) and the semiconductor patterns (N2/N4). Rubin’s epitaxial layers are grown in this manner and embedded into conductive contacts (280/290, FIG. 6, [0068]) in order to decrease resistance ([0072]).
Kang and Rubin are analogous art because they both are directed towards semiconductor device manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify the invention of Kang in view of Rubin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device as taught by Kang to include an epitaxial layer including an impurity, and wherein an impurity concentration of the epitaxial layer is greater than an impurity concentration of the first impurity region and an impurity concentration of the second impurity region, with the purpose of decreasing electrical resistance of the contact (Rubin, [0072]), since Kang is concerned at least with electrical resistance in the bit line area (Kang, [0147]) and thus in the overall device.
It is noted that the limitation "epitaxial", as recited throughout the claims, is considered a product-by-process claim. “[E]ven though product-by process limitations are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Response to Arguments
Applicant’s remarks on page 9 regarding the status of the claims in the Instant Application are acknowledged. The Examiner notes claims 5 and 10 have been cancelled in the reply filed on 07/28/2025, and claims 16 and 21-25 were previously cancelled.
Applicant’s remarks on page 9, section I, regarding the Interview Summary are acknowledged. The Examiner likewise thanks Applicant’s representative for their courtesies extended in the interview held on 07/09/2025.
Applicant’s arguments in section II, pages 9-10, regarding the rejection of claim 17 under 35 USC 112(b) in the Final Office Action mailed on 06/11/2025 (hereinafter previous Office Action) are acknowledged.
In response, the Examiner finds Applicant’s amendment to claim 17 sufficient to overcome the 112(b) rejection. However, the Examiner notes new rejections made under 35 USC 112(b) in the Instant Office Action.
Applicant’s arguments in section III, pages 10-13, regarding rejections made under 35 USC 102(a)(1) in the previous Office Action over the Lee reference are acknowledged. Applicant argues on page 10 Lee fails to disclose “wherein the plurality of first epitaxial layers overlap the second conductive pattern in the first direction”. Specifically, Applicant argues on page 11 the Examiner appears to apply a meaning of the term “overlap” that is inconsistent with the plan and ordinary meaning of the term as understood by a person of ordinary skill in the art.
In response, the Examiner finds this argument non persuasive. The Examiner stated on page 3 of the Office Action “overlap” can mean to cover part of the same space. The meaning of the verb still applies whether used transitively or intransitively. Additionally, Applicant’s definition of overlap stated on page 12: “to extend over or past and cover a part of” still applies to the Lee reference. For example, FIG. 14 of Lee shows SD1 extending over and covering part of second conductive line BL/BS in the vertical direction. It is noted the second conductive pattern is interpreted as BL/BS in the Instant Office Action.
Applicant’s arguments in section IV.A, pages 13-14, that the 103 rejections of dependent claims 3, 4, and 7-9 over Lee and Rubin should be withdrawn since Lee and Rubin fail to teach or suggest all the limitations of claim 1.
In response, this argument in moot since the Examiner finds Lee and Rubin substantially teach all of the claimed limitations of claim 1.
Applicant’s arguments in section IV.B, pages 13-18, regarding the 103 rejections of dependent claims 11-18 over Kang and Rubin are acknowledged. Applicant states Kang and Rubin fail to teach or suggest “wherein the capacitor overlaps the epitaxial layer in the first direction”. Specifically, Applicant stages on page 16 “…Rubin does not disclose “a capacitor.” Thus, Rubin necessarily cannot teach or suggest, inter alia, “wherein the capacitor overlaps the epitaxial layer in the first direction”.
In response, the Examiner finds the argument non persuasive since the previous Office Action did not identify Rubin alone as teaching the claimed limitation. Rather, the combination of Kang and Rubin is cited as teaching the limitation.
Applicant further argues on page 16 the Office Action “provides no information about where Rubin’s epitaxial source/drain layers 270 would be added to Kang…”. In response, the Examiner finds this argument non persuasive, since the Office Action stated on page 15 “Rubin’s epitaxial layers are grown in this manner and overlap conductive contacts (280/290) in order to decrease resistance”. Since the claimed capacitor was aligned with 182/184/186 of Kang, layer 186 of which is an outer electrode (i.e. conductive contact) of the capacitor, one of ordinary skill in the art would be motivated to use the teachings of Rubin to overlap the capacitor electrode 186 of Kang with epitaxial layers in order to decrease resistance.
Applicant further argues on pages 17-18 “Kang does not teach or suggest that an epitaxial growth process is performed to form the doped layer 117. And one of skill in the art would not have been motivated to modify Kang to add an additional manufacturing process to form an additional component for no discernable advantage”.
In response, the Examiner finds this argument non persuasive. The Office Action clearly stated the advantage for modifying Kang in view of Rubin on page 16: “with the purpose of decreasing electrical resistance of the contact”. Additionally, Rubin also teaches the epitaxial layers are doped using a gas phase doping process (Rubin, [0063]) which is not incompatible with Applicant’s arguments on page 17 detailing the “pull back” process of Kang which also uses a gas phase doping process.
Applicant argues on 18-21 Kang as modified by Rubin does not teach the limitation of claim 18: “wherein the second conductive pattern includes a first portion disposed above the epitaxial layer and overlapping the epitaxial layer in the third direction, and a second portion disposed below the epitaxial layer and overlapping the epitaxial layer in the third direction”. Specifically, Applicant argues on page 21: “one of ordinary skill in the art would not have been motivated to modify Kang to add an epitaxial layer, such as Rubin’s an epitaxial layer 270, to extend from Kang’s source/drain region 119”.
In response, the Examiner finds this argument non persuasive. The Office Action clearly identified the motivation for this modification on page 24: “Rubin’s epitaxial layers (270) are gown and embedded the electrode 80 in order to decrease resistance (Rubin, [0072]).
Applicant further argues on pages 21 and 22 there is no benefit in the proposed modification because of the presence of the bit line barrier in Kang. The Examiner finds this argument non persuasive. The stated motivation of decreasing resistance is applicable regardless of the presence of a bit line barrier or not. Rubin also teaches in [0069] a barrier layer may be formed between the epitaxial layers 270 and the contacts 280/290.
Applicant further argues on page 22 the process of Kang uses to create the source/drain regions 119 teaches away from the proposed modification. The Examiner finds this non persuasive, as both the method cited by Applicant on page 22 and the method described by Rubin in [0063] rely on a gas phase doping process.
Conclusion
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/S.L.J./Examiner, Art Unit 2811
/ORI NADAV/Primary Examiner, Art Unit 2811
Prosecution Insights