Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 11-15 and 17-19 rejected under 35 U.S.C. 103 as being unpatentable over Grass (U.S. Patent Pub. No. 2016/0049302), in view of Doornbos (U.S. Patent Pub. No. 2023/0387296) of record, in view of Ismagilov (CN 105939779) of record.
Regarding Claim 11
FIG. 11 of Grass discloses a non-volatile memory (NVM) structure [0007] comprising: a key storage region comprising at least one first ferroelectric field effect transistor, the at least one first FeFET (110A) comprises a source region (114A), a drain region (114A), a ferroelectric material layer (116A [0011]); and a memory region located adjacent to the key storage region, the memory region comprising at least one second FeFET (110B), the at least one second FeFET comprising a source region (114B), a drain region (114B), a ferroelectric material layer (42), a gate electrode (46); and a first spacer (22) and a second spacer (62) present in the key storage region, wherein the second spacer has a bottommost surface that lands entirely on the topmost surface of the ferroelectric material layer (116A) of the at least one first FeFET, and the first spacer is located along a sidewall of the second spacer and along a sidewall of the ferroelectric material layer of the at least one first FeFET and lands on the source region and the drain region of the at least one first FeFET, and wherein the first spacer has a bottommost surface that is coplanar with a bottommost surface of the ferroelectric material layer of the at least one first FeFET; and the bottommost surface of the first spacer is vertically offset and located beneath the bottommost surface of the second spacer.
Grass is silent with respect to “a localized heater”; “the localized heater in the key storage region has a bottommost surface that lands entirely on a topmost surface of the ferroelectric material layer”; “the U-shaped localized heater in the memory region is located on a top of the ferroelectric material layer and is present along a sidewall and a bottom wall of the gate electrode of the at least one second FeFET”; “the second spacer is located along a sidewall of the localized heater of the at least one first FeFET”; and “the U-shaped localized heater has a width that is equal to a width of the ferroelectric material layer such that an outermost sidewall of the U-shaped localized heater is vertically aligned to an outermost sidewall of the ferroelectric material layer that is present in the memory region”.
FIG. 1 of Doornbos discloses a similar structure, comprising a localized heater (20), wherein the localized heater in the key storage region has a bottommost surface that lands entirely on a topmost surface of the ferroelectric material layer (18); the second spacer (34, FIG. 2) is located along a sidewall of the localized heater of the at least one first FeFET, wherein the localized heater has a width that is equal to a width of the ferroelectric material layer such that an outermost sidewall of the localized heater is vertically aligned to an outermost sidewall of the ferroelectric material layer that is present in the memory region.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Grass, as taught by Doornbos. The ordinary artisan would have been motivated to modify Grass in the above manner for purpose of increasing the temperature of the ferroelectric layer ([0034] of Doornbos).
Grass as modified by Doornbos is silent with respect to “a U-shaped localized heater”; and “the U-shaped localized heater in the memory region is located on a top of the ferroelectric material layer and is present along a sidewall and a bottom wall of the gate electrode of the at least one second FeFET”.
FIG. 33 of Ismagilov discloses a similar structure, comprising a U-shaped localized heater (3312).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Grass, as taught by Ismagilov, such that the U-shaped localized heater in the memory region is located on a top of the ferroelectric material layer and is present along a sidewall and a bottom wall of the gate electrode of the at least one second FeFET. The ordinary artisan would have been motivated to modify Huang in the above manner for purpose of increasing the contact surface thus to improve the thermal conductance.
Regarding Claim 12
FIG. 11 of Grass discloses an interlayer dielectric material (ILD) layer (24) separating the key storage region and the memory region.
Regarding Claim 13
It would have been obvious to one of ordinary skill in the art that modified Grass discloses the U-shaped localized heater has a topmost surface that is coplanar with a topmost surface of the gate electrode present in the memory region.
Regarding Claim 14
The recitation “the localized heater in the key storage region is configured to generate Joule heating to increase temperature of the ferroelectric material layer of the at least one first FeFET higher than a Currie temperature of the ferroelectric material layer of the at least one first FeFET such that at least a private encryption key is erased” is only a statement of the inherent properties of the device. When the structure recited in the prior art is substantially identical to that of the claimed invention, then the claimed properties or functions are presumed to be inherent. Or where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. See MPEP 2112.01.
Regarding Claim 15
The recitation “the localized heater in the memory region is configured to generate Joule heating to increase temperature of the ferroelectric material layer of the at least one second FeFET higher than a Currie temperature of the ferroelectric material layer of the at least one second FeFET such that data is erased in the memory region” is only a statement of the inherent properties of the device. When the structure recited in the prior art is substantially identical to that of the claimed invention, then the claimed properties or functions are presumed to be inherent. Or where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. See MPEP 2112.01.
Regarding Claim 17
FIG. 33 of Ismagilov discloses a spacer (3313) in the memory region, wherein the spacer in the memory region is present along a sidewall of the U-shaped localized heater of the at least one second FeFET and a sidewall of the ferroelectric material layer of the at least one second FeFET.
Regarding Claim 18
FIG. 1 of Doornbos discloses the localized heater of the at least one first FeFET is wired to a processor, wherein the processor notifies the localized heater of the at least one first FeFET to active when a trigger event occurs.
Regarding Claim 19
FIG. 33 of Ismagilov discloses the U-shaped localized heater of the at least one second FeFET is wired to the processor, wherein the processor also notifies the U- shaped localized heater of the at least one second FeFET to active when the trigger event occurs.
Claim 20 rejected under 35 U.S.C. 103 as being unpatentable over Grass, Doornbos, Ismagilov and Sharma in view of Ishii (U.S. Patent Pub. No. 2016/0363892) of record.
Regarding Claim 20
Grass as modified by Doornbos, Ismagilov and Sharma discloses Claim 18.
Grass as modified by Doornbos, Ismagilov and Sharma is silent with respect to “the processor comprises at a notification unit or a tamper detection unit”.
FIG. 2 of Ishii discloses a similar structure, wherein the processor comprises at a notification unit or a tamper detection unit (Claim 8).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Grass, as taught by Ishii. The ordinary artisan would have been motivated to modify Grass in the above manner for purpose of controlling the storage system ([0023] of Ishii).
Pertinent Art
US 7,064,414 discloses a U-shaped localized heater (6+31). US 7,173,842 discloses a localized heater is applied to ferroelectric memory. U.S. Patent Pub. No. 2022/0352183 discloses the first spacer is located along a sidewall of the second spacer and along a sidewall of the ferroelectric material layer of the at least one first FeFET and lands on the source region and the drain region of the at least one first FeFET. JP 4189902 discloses ferroelectric element is heated by a heating element. One of ordinary skill in the art would understand that making the localized heater having a width equal to a width of the ferroelectric material layer would be most efficient for heating. FIG. 5 of Sharma (U.S. Patent Pub. No. 2020/0388685) discloses the first spacer (250) has a bottommost surface that is coplanar with a bottommost surface of the ferroelectric material layer (315) of the at least one first FeFET [0114]. FIG. 7 of Tu (U.S. Patent Pub. No. 2019/0103493) discloses a non-volatile memory (NVM) structure [0011] comprising: a key storage region comprising at least one first ferroelectric field effect transistor (FeFET), the at least one first FeFET comprises a source region, a drain region, a ferroelectric material layer; and a memory region located adjacent to the key storage region, the memory region comprising at least one second FeFET, the at least one second FeFET comprising a source region, a drain region, a ferroelectric material layer.
Response to Arguments
Applicant’s arguments with respect to Claim 11 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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