DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's amendments and arguments filed 10/16/2025 have been fully considered and are persuasive, the office action has been updated to address the newly amended limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 4-12 are rejected under 35 U.S.C. 103 as being unpatentable over Maa et al (U.S. Pub #2007/0099329), in view of Reznicek et al (U.S. Pub #2018/0190483).
With respect to claim 1, Maa teaches a semiconductor device, comprising:
a substrate having a first sublayer (Fig. 8, 24), wherein the dielectric layer is formed on the first sublayer.
a dielectric layer (Fig. 8, 28) formed on the first sublayer having a first surface;
a first trench (Fig. 8, 32) located in the dielectric layer;
a first semiconductor layer (Fig. 8, 36 and Paragraph 21) located in the first trench;
a second semiconductor layer (Fig. 8, 40 and/or 44 and Paragraph 22-23) comprising an active portion (Paragraph 19-20; sections 36/40/44) connecting to the first semiconductor layer; and
an electrical connector (Fig. 8, 50 and Paragraph 25) located on the first surface and connected to the second semiconductor layer.
Maa does not teach that the first sublayer comprises a cavity; the first trench connected to the cavity, the first semiconductor layer located in the cavity;
wherein the cavity has a bottom and an opening, the opening is connected to the first trench, and the cavity comprises a width increasing and decreasing along a vertical direction from the opening to the bottom.
Reznicek teaches a first sublayer of a substrate comprising a cavity (Fig. 9, 132),
a trench connected to the cavity, a semiconductor layer (Fig. 10, 136) located in the cavity;
wherein the cavity has a bottom and an opening, the opening is connected to the first trench, and the cavity comprises a width increasing and decreasing along a vertical direction from the opening to the bottom.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to form a cavity having the increasing/decreasing width of Reznicek in the first sublayer of Maa, the first semiconductor layer being located in the cavity, in order to maintain defects within the cavity (Paragraph 22).
With respect to claim 2, Maa teaches that the electrical connector (Fig. 8, 50) covers the first trench (Fig. 8, 32).
With respect to claim 4, Maa teaches that the active portion (Fig. 8, 36/40/44) comprises a first section in the first trench and a second section (Fig. 8, 40) protruding from the first trench.
With respect to claim 5, Maa teaches that the active portion contacts the first surface of the dielectric layer (Fig. 8, top surface of 28).
With respect to claim 6, Maa teaches that the second semiconductor layer further comprises a doped portion (Fig. 8, 44) located on the first surface and connecting to the active portion.
With respect to claim 7, Maa teaches the doped portion (Fig. 8, 44) covers the first trench (Fig. 8, 32).
With respect to claim 8, Maa teaches the second semiconductor layer further comprises a doped portion (Fig. 8, 44) covering the second section.
With respect to claim 9, Maa teaches the first trench, the first semiconductor layer and the active portion respectively have a depth, a first thickness and a second thickness, and a sum of the first thickness and the second thickness is greater than the depth.
With respect to claim 10, Maa teaches that the first thickness (Fig. 8, 36) is substantially equal to the depth (Fig. 8, i.e. thickness of 28).
With respect to claim 11, Maa teaches that the second semiconductor layer further comprises a doped portion (Fig. 8, 44) located on the first surface and having a third thickness, and a sum of the first thickness and the second thickness (Fig. 8, thicknesses of 36 and 40) is substantially equal to a sum of the depth and the third thickness (Fig. 8, thickness of 44 and 28).
With respect to claim 12, Maa teaches that the electrical connector (Fig. 8, 50) has a fourth thickness, and the fourth thickness is greater than the third thickness (Fig. 8, 44).
Claim 3 rejected under 35 U.S.C. 103 as being unpatentable over Maa and Reznicek, in view of Maa et al (U.S. Pub #2007/0099315).
With respect to claim 3, Maa teaches a first junction formed between the first semiconductor layer and the active portion, but does not teach that the first junction is located in the first trench.
Maa-2 teaches that a first junction formed between the first semiconductor layer (Fig. 14, 72) and an active portion (Fig. 14, 78) is located in a trench (Fig. 14, trench formed in 65/76).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to form the trench such that the junction is located in the first trench as taught by Maa-2 in order to form a window opening for the electrical contact (Paragraph 27-28).
Claim 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Maa and Reznicek, in view of Lee et al (U.S. Pub #2021/0126142).
With respect to claim 13, Maa teaches a second trench in the dielectric layer,
but does not teach that the first trench and the second trench respectively have a first width and a second width, and the first width is different from the second width.
Lee teaches PIN photodetectors, wherein first and second photodetectors can have a first width and a second width, and the first width is different from the second width (Paragraph 84-87). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to form the second trench, and resulting PIN photodetector, of Maa to have a different width from the first trench as taught by Lee in order to configure the first and second photodetectors to sense different wavelengths (Paragraph 84-87).
With respect to claim 14, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to form the the first width is greater than the second width, the first semiconductor layer is located in the second trench of Maa and a thickness of the first semiconductor layer in the first trench is greater than that of the first semiconductor layer in the second trench of Maa as taught by Lee in order to configure the first and second photodetectors to sense different wavelengths (Paragraph 84-87).
Claim 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Maa, Reznicek, and Lee, in view of Cheng et al (U.S. Pub #2016/0103278).
With respect to claim 15, Maa and Lee do no teach that the first semiconductor layers located in the first trench and the second trench have different chemical composition.
Cheng first and second PIN device structures, wherein the device structure can be formed with semiconductor layer having different chemical compositions (Paragraph 85-88). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide an additional trench in the structure of Maa having a semiconductor layer with a different chemical composition as taught by Cheng in order to achieve the predictable result of integrating different device types on the same substrate (Paragraph 85-88).
With respect to claim 16, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to form the second semiconductor layers located in the first trench and the second trench to have different chemical compositions as taught by Cheng in order to achieve the predictable result of integrating different device types on the same substrate (Paragraph 85-88).
Claim 19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Maa and Reznicek, in view of Zaizen et al (U.S. Pub #2019/0319055).
With respect to claim 19, Maa does not teach that the substrate further comprises a base layer and a second sublayer located between the first sublayer and the base layer.
Zaizen teaches that the substrate further comprises a base layer (Fig. 1, 31) and a second sublayer (Fig. 1, 32) located between the first sublayer and the base layer.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a base layer and a second sublayer located between the first sublayer and the base layer as taught Zaizen in order to achieve the predictable result of integrating the photodetectors with circuitry.
With respect to claim 21, Zaizen teaches teach that the first sublayer (Fig. 1, width of the pixel element P) comprises a width less than a width of the second sublayer (Fig. 1, second sublayer 32 extends across entire substrate).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a second sublayer as taught Zaizen in order to achieve the predictable result of integrating the photodetectors with circuitry.
Claim 20 rejected under 35 U.S.C. 103 as being unpatentable over Maa and Reznicek, in view of Liao et al (U.S. Pub #2022/0037552)
With respect to claim 20, Maa does not teach a semiconductor apparatus, comprising:
a substrate comprising a first sublayer; a semiconductor device of claim 1; and a transistor comprising a fin, wherein the fin and the first sublayer have the same material.
Liao teaches a semiconductor apparatus, a substrate comprising a first sublayer (Fig. 9, 202), and a FinFET formed on the first sublayer (Paragraph 24).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a FinFET on a first sublayer of the substrate of Maa, having the fin formed of the same material of the sublayer, as taught by Liao in order to integrate the photodetector with logic circuitry (Paragraph 24).
Claim 19, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Maa, Reznicek, in view of Cheng et al (U.S. Pub #2016/0105247).
With respect to claim 19, Maa does not teach that the substrate further comprises a base layer and a second sublayer located between the first sublayer and the base layer.
Cheng teaches a substrate comprising a base layer (Fig. 1, 2) and a second sublayer (Fig. 1, 3) located between the first sublayer of an epitaxial structure (Fig. 1, 15a) and the base layer.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to form the substrate of Maa as a base layer and a second sublayer as taught by Cheng in order to achieve the predictable of integrating epitaxial optoelectronic device on a substrate with processing circuitry (Paragraph 36-37).
With respect to claim 21, Cheng teaches that the first sublayer (Fig. 1, 15a) comprises a width less than a width of the second sublayer (Fig. 1, 3).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to form the substrate of Maa to comprise the first substrate and second sublayer as taught by Cheng in order to achieve the predictable of integrating epitaxial optoelectronic device on a substrate with processing circuitry (Paragraph 36-37).
With respect to claim 22, Cheng teaches a fin (Fig. 1, devices 20 or 45 can be a FinFET device; Paragraph 24) located on the second sublayer and separated from the first sublayer.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a fin on a second sublayer on the substrate of Maa as taught by Cheng in order to integrate an optoelectronic device on the same substrate as a switching device (Paragraph 24).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6.
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/BENJAMIN P SANDVIK/ Primary Examiner, Art Unit 2812