DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
RE: the rejection of claim(s) 14-19 under 35 USC 112(a) and 35 USC 112(b), Applicant’s arguments and/or amendments have been fully considered and resolve the issues of enablement and indefiniteness. Accordingly, the rejections of claim(s) 14-19 under 35 USC 112(a) and 35 USC 112(b) have been withdrawn.
RE: the rejection of claims under 35 USC 103, Applicant’s arguments and amendments have been fully considered but are moot in view of the new grounds of rejection presented herein. Applicant argues even if the tunnel insulation layer in Lee could be considered a "dielectric pillar," which Applicant does not concede, Lee fails to teach or suggest a "first dielectric pillar" and a "second dielectric pillar" wherein "the first dielectric pillar is located between the conductive pillar and the one or more respective memory cells," and wherein "the second dielectric pillar is located between the one or more respective memory cells and the plurality of word lines," as claimed.
However, Lee which was previously relied upon, teaches a first dielectric pillar (TIL in FIG. 4) and a second dielectric pillar (BIL1) as further discussed hereafter.
Claim Objections
Claim 20 is objected to because of the following minor informality:
Claim 20 includes “a conductive pillar extending through a plurality of levels of memory cells coupled with one or more memory cells,” which is considered a typographical error of “a conductive pillar extending through a plurality of levels of memory cells and coupled with one or more memory cells” (where the word “and” was added for grammatical correctness). Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 14-17, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20120299086A1 (“Lee”), in view of US20220320134 A1 (“Park”), further in view of US20160260490A1 (“Lee-2”).
RE: Claim 14, Lee discloses An apparatus (device in FIGs. 2-4), comprising:
a substrate (100 in FIG. 2);
a plurality of levels of memory cells (trap sites in charge storage layer CL, [0094]; The charge storage layer CL may be an insulation layer including trap sites, [0061]; under a broad reasonable interpretation, at least the trap sites are memory cells) over the substrate;
a plurality of word lines (150 and/or 150U in FIG. 2; Lee teaches gate electrodes of the memory cell transistors MCT may extend to form a plurality of word lines WL0, WL1, WL2 and WL3, [0039]; 150, 150U are gate electrodes, [0046]; Accordingly, 150, 150U are word lines) associated with accessing the plurality of levels of memory cells;
a conductive pillar (133 is a semiconductor pattern SP in FIG. 2; SP is labelled in FIG. 4, [0052], [0060]) extending through the plurality of levels of memory cells;
a first dielectric pillar (tunnel insulating layer TIL in first dielectric layer DA1 in FIG. 2; TIL is labelled in FIG. 4, [0050], [0062]) extending through the plurality of levels of memory cells, and wherein the conductive pillar protrudes above a top surface of the first dielectric pillar in a first direction (vertical direction in FIG. 2) orthogonal to the substrate (133 protrudes above a top surface of DA1 in FIG. 2 and therefore protrudes above a top surface of TIL which is in DA1);
a second dielectric pillar (blocking insulating layer BIL1 in the first dielectric layer, [0063]; BIL1 is a high-k dielectric layer such as aluminum oxide, [0064]; BIL1 is labelled in FIG. 4) extending through the plurality of levels of memory cells;
a line (198 in FIG. 2) associated with accessing the plurality of levels of memory cells; and
a contact (199, 162) coupled with the conductive pillar based at least in part on the conductive pillar protruding above the top surface of the first dielectric pillar and configured to couple the line with the conductive pillar (FIG. 2 shows the conductive pillar 133 protruding above the top surface of DA1 which includes the first dielectric pillar TIL; Accordingly, 199, 162 is coupled to the conductive pillar 133 based on it protruding above the top surface of the first dielectric pillar TIL).
Lee does not explicitly disclose:
the conductive pillar coupled with one or more respective memory cells at each level of the plurality of levels of memory cells;
wherein the first dielectric pillar is located between the conductive pillar and the one or more respective memory cells;
wherein the second dielectric pillar is located between the one or more respective memory cells and the plurality of word lines;
the line is a bit line.
In the same field of endeavor, Park discloses a charge trap layer 132 may be referred to as a charge storage layer, [0016].
In the same field of endeavor, Lee-2 discloses A plurality of memory cells MC11 to MCmn included in the memory cell array 110 are charge trap type non-volatile memory cells, each memory cell including a charge trap layer as a memory element, [0051].
Lee-2 discloses The charge trap layer CT extends to adjacent memory cells and is shared by, e.g., the plurality of memory cells MC1, MC2, MC3, . . . , MCn-1, and MCn,[0073].
FIG. 7C shows a plurality of memory cells MC1 to MCn at a plurality of levels of memory cells in the charge trap layer CT, [0069]-[0070].
FIG. 7C shows a tunnel insulating layer TI is located between a conductive pillar PL and one or more memory cells which would be in the charge trap layer CT, [0012], [0072], [0092], [0121].
FIG. 7A shows a block insulating layer BI is located between a plurality of word lines WL and the one or more memory cells which would be in the charge trap layer CT, [0078], [0054].
Lee-2 further discloses Therefore, data retention characteristics of the programmed memory cell MC2m−1 and MC2m+1 and reliability of a memory device based on the same may be improved, [0090].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to position the first dielectric pillar TIL between the conductive pillar 133/SP and the one or more memory cells/trap sites in the CL, and position the second dielectric pillar BIL1 between a plurality of word lines 180 and the one or more memory cells in CL as taught by Lee-2 in order to improve data retention characteristics and reliability of the memory device as further taught by Lee-2. As a result, the conductive pillar 133 would extend through the plurality of levels of memory cells in the charge storage layer CL and would be coupled with the one or more memory cells at each level of the plurality of levels of memory cells in CL.
Further, Lee discloses that 198 are conductive lines that are electrically connected to the vertical channel structures VS, [0059] which include a data storage layer, [0049], [0019]-[0020]. Lee further teaches bit lines BL0-BL3 may be conductive patterns (e.g., metal lines) disposed over the substrate and separated from the substrate, [0038].
Accordingly, 198 are considered bit lines as they are conductive lines that would carry data in the form of bits to be stored in VS, and 198 are disposed over the substrate 100 and separated from the substrate 100.
RE: Claim 15, Lee in view of Park, Lee-2 discloses The apparatus of claim 14, wherein the conductive pillar extends into the contact in the first direction based at least in part on protruding above the top surface of the first dielectric pillar (133 extends into 162 based on its protrusion in Lee FIGs. 2-3) and is coupled with the contact based at least in part on extending into the contact (contact area between VS and 199 is increased by 161, 162, [0090] and therefore, the contact area between VS and 199 is considered to include 161, 162 and so 133 would be coupled with 199, 162 based on 133 extending into 162).
RE: Claim 16, Lee in view of Park, Lee-2 discloses The apparatus of claim 15, wherein the contact (combination of 199, 162, 161 in Lee FIG. 2) comprises a first conductive material (Lee discloses 162 is a conductive layer, [0055], therefore 162 is considered to include a first conductive material) and a second conductive material (Lee discloses 161 is a conductive layer, [0057], therefore 161 is considered to include a second conductive material), the conductive pillar extending into the first conductive material in the first direction (Lee FIG. 2 shows 133 extending vertically into a cavity defined by 162), wherein the contact is coupled to a dielectric material (120U in Lee FIG. 2, [0068], [0093]) located above the first dielectric pillar in the first direction orthogonal to the substrate (Lee FIG. 3 shows 120U is located at a higher level than DA1 in the first vertical direction).
RE: Claim 17, Lee in view of Park, Lee-2 discloses The apparatus of claim 16, further comprising:
a cavity in the first conductive material (Lee FIG. 2 shows a cavity in 162), the conductive pillar (Lee FIG. 2 shows another cavity in 133), or both, wherein the second conductive material is at least partially located in the cavity (Lee FIG. 2 shows 161 located at least partially in the cavities in 162 and 133).
RE: Claim 19, Lee in view of Park, Lee-2 discloses The apparatus of claim 14, wherein the contact is in contact with one or more sidewalls of the conductive pillar (Lee FIG. 2 shows 161 in contact with a sidewall of 133 and 162 in contact with another sidewall of 133).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Park, Lee-2 as applied to claim 16 above, and further in view of US9722015 B1 (“Kalnitsky”).
RE: Claim 18, Lee in view of Park, Lee-2 does not explicitly disclose The apparatus of claim 16, wherein the first conductive material is a first polysilicon material and the second conductive material is a second polysilicon material.
However, Lee discloses 161 is a conductive layer formed to include silicon, [0076].
In a similar field of endeavor, Kalnitsky discloses the first, second and third conductive layers 318, 322, 326 can be made of polysilicon, Col. 6, lines 15-17.
Kalnitsky further teaches that a thin polysilicon layer is conformally deposited over the first insulating layer 108 in the trench 106, Col. 4, lines 25-26.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make 161 and 162 each out of polysilicon as taught by Kalnitsky which would allow the conformal deposition of 161 and 162 and therefore result in lower resistance of the contact areas of 161, 162. As a result, 162 would be considered to include a first polysilicon material and 161 would be considered to include a second polysilicon material.
Claim(s) 20-22, 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Park, further in view of Lee-2.
RE: Claim 20, Lee discloses An apparatus (device in FIGs. 18-19), comprising:
a conductive pillar (133 is a semiconductor pattern SP, [0060], [0052]) extending through a plurality of levels of memory cells (trap sites in charge storage layer CL, [0094]) coupled with one or more memory cells (The charge storage layer CL may be an insulation layer including trap sites, [0061]; under a broad reasonable interpretation, at least the trap sites are memory cells);
a line (198 in FIG. 18) configured to access the one or more memory cells via the conductive pillar; and
a contact (combination of 199, 161, 163) configured to couple the conductive pillar with the line based at least in part on the conductive pillar protruding above a top surface of a first dielectric pillar (tunnel insulating layer TIL in FIG. 19, [0062]; Lee teaches a dielectric layer includes TIL, [0062]; Accordingly, Lee teaches TIL is dielectric) and a second dielectric pillar (blocking insulation layer BIL in FIG. 19, [0094]; Lee teaches a dielectric layer includes a blocking insulation layer, [0063]; Accordingly, Lee teaches BIL is dielectric), the contact comprising:
a first conductive material (163 is a conductive layer, [0096], therefore 163 is considered to include a first conductive material) in contact with one or more sidewalls of the conductive pillar based at least in part on the conductive pillar extending through the first conductive material (FIG. 19 shows 163 is in contact with one or more sidewalls of the conductive pillar 133 based at least in part on the conductive pillar 133 extending through 163); and
a second conductive material (161 and 199 are conductive layers, [0057]; 199 are contact plugs providing electrical connection, [0059], therefore 199 is considered electrically conductive; in combination, 161 and 199 are considered to include a second conductive material) extending from the line at least to the first conductive material.
Lee does not explicitly disclose:
the conductive pillar coupled with the one or more memory cells at each level of the plurality of levels of memory cells;
wherein the first dielectric pillar is located between the conductive pillar and the one or more memory cells, and wherein the second dielectric pillar is located between a plurality of word lines and the one or more memory cells;
the line is a bit line.
However, Lee discloses that gate electrodes of the memory cell transistors MCT may extend to form a plurality of word lines WL0, WL1, WL2 and WL3, [0039].
As Lee teaches 180 are gate electrodes, [0092], 180 are considered word lines.
In the same field of endeavor, Park discloses a charge trap layer 132 may be referred to as a charge storage layer, [0016].
In the same field of endeavor, Lee-2 discloses A plurality of memory cells MC11 to MCmn included in the memory cell array 110 are charge trap type non-volatile memory cells, each memory cell including a charge trap layer as a memory element, [0051].
Lee-2 discloses The charge trap layer CT extends to adjacent memory cells and is shared by, e.g., the plurality of memory cells MC1, MC2, MC3, . . . , MCn-1, and MCn,[0073].
FIG. 7C shows a plurality of memory cells MC1 to MCn at a plurality of levels of memory cells in the charge trap layer CT, [0069]-[0070].
FIG. 7C shows a tunnel insulating layer TI is located between a conductive pillar PL and one or more memory cells which would be in the charge trap layer CT, [0012], [0072], [0092], [0121].
FIG. 7A shows a block insulating layer BI is located between a plurality of word lines WL and the one or more memory cells which would be in the charge trap layer CT, [0078], [0054].
Lee-2 further discloses Therefore, data retention characteristics of the programmed memory cell MC2m−1 and MC2m+1 and reliability of a memory device based on the same may be improved, [0090].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to position the first dielectric pillar TIL between the conductive pillar 133/SP and the one or more memory cells/trap sites in the CL, and position the second dielectric pillar BIL between a plurality of word lines 180 and the one or more memory cells in CL as taught by Lee-2 in order to improve data retention characteristics and reliability of the memory device as further taught by Lee-2. As a result, the conductive pillar 133 would extend through the plurality of levels of memory cells in the charge storage layer CL and would be coupled with the one or more memory cells at each level of the plurality of levels of memory cells in CL.
Further, Lee discloses that 198 are conductive lines that are electrically connected to the vertical channel structures VS, [0059] which include a data storage layer, [0049], [0019]-[0020]. Lee further teaches bit lines BL0-BL3 may be conductive patterns (e.g., metal lines) disposed over the substrate and separated from the substrate, [0038].
Accordingly, 198 are considered bit lines as they are conductive lines that would carry data in the form of bits to be stored in VS, and 198 are disposed over the substrate 100 and separated from the substrate 100.
RE: Claim 21, Lee in view of Park, Lee-2 discloses The apparatus of claim 20, further comprising: a cavity in the first conductive material (Lee FIG. 19 shows a cavity in 163), the conductive pillar (Lee FIG. 19 shows another cavity in 133), or both, wherein the second conductive material is at least partially located in the cavity (Lee FIG. 19 shows 161 located at least partially in the cavities in 163 and 133).
RE: Claim 22, Lee in view of Park, Lee-2 discloses The apparatus of claim 20, wherein the second conductive material is in contact with the first conductive material and the conductive pillar (Lee discloses conductive lines 198 may be electrically connected to the channel structures VS through contact plugs 199, [0110]; Further, Lee discloses a contact area between VS and 199, [0090] therefore, 199 is in electrical contact with VS which includes 133, 163 as shown in FIG. 18).
RE: Claim 24, Lee in view of Park, Lee-2 discloses The apparatus of claim 20, wherein: the bit line is located over the plurality of levels of memory cells, the conductive pillar, and the contact (Lee FIG. 18 shows the bit line 198 located over 199 and VS which includes DA, CL, 133), and
the contact is located between the bit line and the plurality of levels of memory cells (Lee FIG. 18 shows 199 is located between the bit line 198 and VS which includes DA, CL).
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Park, Lee-2 as applied to claim 20 above, and further in view of Kalnitsky.
RE: Claim 25, Lee in view of Park, Lee-2 does not explicitly disclose The apparatus of claim 20, wherein the first conductive material is a first polysilicon material and the second conductive material is a second polysilicon material.
However, Lee discloses 163 is a conductive layer including silicon, [0098].
Lee discloses 161 is a conductive layer including silicon, [0057].
Lee discloses 199 is formed of a doped semiconductor material, [0059].
In a similar field of endeavor, Kalnitsky discloses the first, second and third conductive layers 318, 322, 326 can be made of polysilicon, Col. 6, lines 15-17.
Kalnitsky further teaches that a thin polysilicon layer is conformally deposited over the first insulating layer 108 in the trench 106, Col. 4, lines 25-26.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make 161, 163, 199 each out of polysilicon as taught by Kalnitsky which would allow the conformal deposition of 161 and 163 and therefore result in lower resistance of the contact areas of 161, 163, 199. As a result, 163 would be considered to include a first polysilicon material and 161, 199 would be considered to include a second polysilicon material.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
