DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 11, 2026 has been entered.
Response to Arguments
Regarding the rejection of claim 14 under 35 USC 103, Applicant argues even if the gate electrode patterns, as in Lee, could be considered a "plurality of word lines", which Applicant does not concede, the gate electrode patterns of Lee are separated from a tunnel insulation layer by a charge storage layer and a blocking insulation layer. Therefore, Lee does not teach or suggest a dielectric pillar "directly coupled to the plurality of word lines and the one or more respective memory cells," as recited in amended independent claim 14.
Accordingly, Applicant argues because there are intervening layers between the gate electrode patterns and tunnel insulation layer, they are not directly coupled to each other. Based on this interpretation of “directly coupled”, claim 14 is rejected under 35 USC 112(a) and 35 USC 112(b) as discussed hereafter.
FIG. 2 of Lee is still used to meet the limitations of claim 14 as best understood by the Examiner.
Further, FIG. 18 of Lee is used to meet the limitations of claim 20 in the new grounds of rejection presented herein.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 14-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 14 requires “a dielectric pillar extending through the plurality of levels of memory cells and located between the conductive pillar and the one or more respective memory cells” and “wherein the dielectric pillar is directly coupled to the plurality of word lines and the one or more respective memory cells” and this is not supported by the instant application. The terminology “directly coupled” is interpreted to mean there are no intervening layer(s) between the dielectric pillar and the word lines which is consistent with Applicant’s arguments (see bottom paragraph of page 8 of Applicant’s remarks).
For example, dielectric pillar 330-a in FIG. 3H of the instant application is directly coupled to the word lines 375 and to the memory cells 385.
However, the dielectric pillar 330-a is not between the conductive pillar 340 and the memory cells 385 and does not extend through the plurality of memory cells 385 (as the pillar 330-a is outside the memory cells 385). Accordingly, the above limitation is considered new matter.
Claims 15-19 are rejected due to their dependency from claim 14.
Claims 14-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 14 requires “a dielectric pillar … located between the conductive pillar and the one or more respective memory cells” and “wherein the dielectric pillar is directly coupled to the plurality of word lines and the one or more respective memory cells” and this is not supported by the instant application. The terminology “directly coupled” is interpreted to mean there are no intervening layer(s) between the dielectric pillar and the word lines which is consistent with Applicant’s arguments (see bottom paragraph of page 8 of Applicant’s remarks).
For example, dielectric pillar 330-a in FIG. 3H of the instant application is directly coupled to the word lines 375 and to the memory cells 385.
In order for the dielectric pillar 330-a to be positioned between the conductive pillar 340 and the memory cells 385, the memory cells would have to be positioned outside the dielectric pillar 330-a. Such a structure was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claims 15-19 are rejected due to their dependency from claim 14.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 requires “a dielectric pillar … located between the conductive pillar and the one or more respective memory cells” and “wherein the dielectric pillar is directly coupled to the plurality of word lines and the one or more respective memory cells” and this is not supported by the instant application. The terminology “directly coupled” is interpreted to mean there are no intervening layer(s) between the dielectric pillar and the word lines which is consistent with Applicant’s arguments (see bottom paragraph of page 8 of Applicant’s remarks).
For example, dielectric pillar 330-a in FIG. 3H of the instant application is directly coupled to the word lines 375 and to the memory cells 385.
In order for the dielectric pillar 330-a to be positioned between the conductive pillar 340 and the memory cells 385, the memory cells would have to be positioned outside the dielectric pillar 330-a, causing them to be in contact with word lines 375, rendering the device nonfunctional. Accordingly, the structural relationship between the elements is indefinite. For the purposes of examination of claims 14-19, the terminology “directly coupled” will be interpreted as “coupled.”
The Examiner recommends the terminology “directly contacts” when no intervening layers are present.
Claims 15-19 are rejected due to their dependency from claim 14.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 14-17, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20120299086A1 (hereinafter “Lee”).
RE: Claim 14, Lee discloses An apparatus (device in FIGs. 2-4), comprising:
a substrate (100 in FIG. 2);
a plurality of levels of memory cells (trap sites in charge storage layer CL in first dielectric layer DA1 in FIG. 2, [0061]; CL is labelled in FIG. 4, [0054]) over the substrate;
a plurality of word lines (150 and/or 150U in FIG. 2) associated with accessing the plurality of levels of memory cells;
a conductive pillar (133 is a semiconductor pattern SP in FIG. 2; SP is labelled in FIG. 4, [0052], [0060]) extending through the plurality of levels of memory cells and coupled with one or more respective memory cells at each level of the plurality of levels of memory cells;
a dielectric pillar (tunnel insulating layer TIL in first dielectric layer DA1 in FIG. 2; TIL is labelled in FIG. 4, [0050], [0062]) extending through the plurality of levels of memory cells and located between the conductive pillar and the one or more respective memory cells, wherein the conductive pillar protrudes above a top surface of the dielectric pillar in a first direction (vertical direction in FIG. 2) orthogonal to the substrate (133 protrudes above a top surface of DA1 in FIG. 2 and therefore protrudes above a top surface of TIL) and wherein the dielectric pillar is directly coupled to the plurality of word lines and the one or more respective memory cells (FIG. 4 shows TIL is coupled to 150 and CL);
a bit line (198) associated with accessing the plurality of levels of memory cells; and
a contact (199, 162) coupled with the conductive pillar based at least in part on the conductive pillar protruding above the top surface of the dielectric pillar and configured to couple the bit line with the conductive pillar.
Lee does not explicitly disclose that trap sites in the charge storage layer CL in DA1 are memory cells. However, Lee teaches that the first dielectric layer DA1 is included in a data storage layer, [0049], and that the data storage layer is included in memory cell transistors MCT, [0043]. Accordingly, the trap sites in the charge storage layer are considered memory cells as they trap charges which would be considered to correspond to storing memory.
Lee does not explicitly disclose that 150, 150U are word lines.
However, Lee discloses that The lowermost electrode pattern among the electrode patterns 150 and 150U may be a lower selection gate pattern, and the uppermost electrode pattern among the electrode patterns 150 and 150U may be an upper selection gate pattern 150U, [0046]. Lee further teaches gate electrodes of the memory cell transistors MCT may extend to form a plurality of word lines WL0, WL1, WL2 and WL3, [0039].
Accordingly, the gate electrode patterns 150, 150U are considered to form word lines.
Lee does not explicitly disclose that 198 are bit lines.
However, Lee discloses that 198 are conductive lines that are electrically connected to the vertical channel structures VS, [0059] which include a data storage layer, [0049], [0019]-[0020]. Lee further teaches bit lines BL0-BL3 may be conductive patterns (e.g., metal lines) disposed over the substrate and separated from the substrate, [0038].
Accordingly, 198 are considered bit lines as they are conductive lines that would carry data in the form of bits to be stored in VS, and 198 are disposed over the substrate 100 and separated from the substrate 100.
RE: Claim 15, Lee discloses wherein the conductive pillar extends into the contact in the first direction based at least in part on protruding above the top surface of the dielectric pillar (133 extends into 162 based on its protrusion in FIG. 2) and is coupled with the contact based at least in part on extending into the contact (contact area between VS and 199 is increased by 161, 162, [0090] and therefore, the contact area between VS and 199 is considered to include 161, 162 and so 133 would be coupled with 199, 162 based on 133 extending into 162).
RE: Claim 16, Lee discloses wherein the contact (combination of 199, 162, 161) comprises a first conductive material (162 are conductive layers, [0055], therefore 162 is considered to include a first conductive material) and a second conductive material (161 are conductive layers, [0057], therefore 161 is considered to include a second conductive material), the conductive pillar extending into the first conductive material in the first direction (FIG. 2 shows 133 extending vertically into a cavity defined by 162), wherein the contact is coupled to a dielectric material (120U) located above the dielectric pillar in the first direction orthogonal to the substrate (FIG. 3 shows 120U is located at a higher level than DA1 in the first vertical direction).
RE: Claim 17, Lee discloses further comprising:
a cavity in the first conductive material (FIG. 2 shows a cavity in 162), the conductive pillar (FIG. 2 shows another cavity in 133), or both, wherein the second conductive material is at least partially located in the cavity (FIG. 2 shows 161 located at least partially in the cavities in 162 and 133).
RE: Claim 19, Lee discloses wherein the contact is in contact with one or more sidewalls of the conductive pillar (FIG. 2 shows 161 in contact with a sidewall of 133 and 162 in contact with another sidewall of 133).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 16 above, and further in view of US9722015 B1 to Kalnitsky et al. (hereinafter “Kalnitsky”).
RE: Claim 18, Lee does not explicitly disclose wherein the first conductive material is a first polysilicon material and the second conductive material is a second polysilicon material.
However, in the same field of endeavor, Kalnitsky discloses the first, second and third conductive layers 318, 322, 326 can be made of polysilicon, Col. 6, lines 15-17.
Kalnitsky further teaches that a thin polysilicon layer is conformally deposited over the first insulating layer 108 in the trench 106, Col. 4, lines 25-26.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make 161 and 162 each out of polysilicon as taught by Kalnitsky which would allow the conformal deposition of 161 and 162 and therefore result in lower resistance of the contact areas of 161, 162. As a result, 162 would be considered to include a first polysilicon material and 161 would be considered to include a second polysilicon material.
Claim(s) 20-22, 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of US20220320134 A1 (“Park”), further in view of US20160260490A1 (“Lee-2”).
RE: Claim 20, Lee discloses An apparatus (device in FIGs. 18-19), comprising:
a conductive pillar (133 is a semiconductor pattern SP, [0060]; [0052]) coupled with one or more memory cells (charge storage layer CL, [0094]; The charge storage layer CL may be an insulation layer including trap sites, [0061]; under a broad reasonable interpretation, at least the trap sites are memory cells);
a line (198 in FIG. 18) configured to access the one or more memory cells via the conductive pillar; and
a contact (combination of 199, 161, 163) configured to couple the conductive pillar with the line based at least in part on the conductive pillar protruding above a top surface of an insulating pillar (pillar BIL; FIG. 19 shows 163 is coupled to 133 based at least in part on 133 protruding above a top surface of an insulating pillar BIL since 163 is able to directly contact the upper portion of 133 because it protrudes above BIL) and wherein the insulating pillar is directly coupled to a plurality of word lines (180) and the one or more memory cells (FIG. 18 shows the outer surface of DA is directly coupled to 180; FIG. 19 shows the outer surface of DA is the outer surface of BIL and BIL is directly coupled to 180; Accordingly, BIL is directly coupled to the plurality of word lines 180; Further, FIG. 19 shows BIL is directly coupled to the charge storage layer CL), the contact comprising:
a first conductive material (163 is a conductive layer, [0096], therefore 163 is considered to include a first conductive material) in contact with one or more sidewalls of the conductive pillar based at least in part on the conductive pillar extending through the first conductive material (FIG. 19 shows 163 is in contact with one or more sidewalls of the conductive pillar 133 based at least in part on the conductive pillar 133 extending through 163); and
a second conductive material (161 and 199 are conductive layers, [0057]; 199 are contact plugs providing electrical connection, [0059], therefore 199 is considered electrically conductive; in combination, 161 and 199 are considered to include a second conductive material) extending from the line at least to the first conductive material (FIG. 18 shows 199 extending from 198; Lee discloses a contact area between VS and 199, [0090] and therefore, the contact area between VS and 199 is considered to include 161, 163, therefore the combination of 161, 199 extends from 198 to contact 163.
Lee does not explicitly disclose:
the conductive pillar extends through a plurality of levels of memory cells and is coupled with the one or more memory cells at each level of the plurality of levels of memory cells;
the line is a bit line;
the blocking insulation layer BIL is a dielectric pillar.
However, in the same field of endeavor, Park discloses a charge trap layer 132 may be referred to as a charge storage layer, [0016].
In the same field of endeavor, Lee-2 discloses A plurality of memory cells MC11 to MCmn included in the memory cell array 110 are charge trap type non-volatile memory cells, each memory cell including a charge trap layer as a memory element, [0051].
Lee-2 discloses The charge trap layer CT extends to adjacent memory cells and is shared by, e.g., the plurality of memory cells MC1, MC2, MC3, . . . , MCn-1, and MCn,[0073].
FIG. 7C shows a plurality of memory cells MC1 to MCn at a plurality of levels of memory cells in the charge trap layer CT, [0069].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of memory cells at different levels in the charge trap layer as taught by Lee-2 in order to more independently control the different memory cells. As a result, the conductive pillar 133 would extends through a plurality of levels of memory cells in the charge storage layer CL and would be coupled with the one or more memory cells at each level of the plurality of levels of memory cells. Further, the charge storage layer CL would be considered at least part of the memory cells.
Further, Lee discloses that 198 are conductive lines that are electrically connected to the vertical channel structures VS, [0059] which include a data storage layer, [0049], [0019]-[0020]. Lee further teaches bit lines BL0-BL3 may be conductive patterns (e.g., metal lines) disposed over the substrate and separated from the substrate, [0038].
Accordingly, 198 are considered bit lines as they are conductive lines that would carry data in the form of bits to be stored in VS, and 198 are disposed over the substrate 100 and separated from the substrate 100.
Further, Lee discloses the first blocking insulation layer BIL1 may be one of high-k dielectric layers such as an aluminum oxide layer and a hafnium oxide layer, [0064], see FIG. 4. Accordingly, before the effective filing date of the claimed invention, there was a need to select a material for the blocking insulation layer BIL in FIG. 18.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use an aluminum oxide layer as the blocking insulation layer BIL in FIG. 18 as this would have been obvious to try since an aluminum oxide layer is one solution for a blocking insulation layer BIL, and this would have had a reasonable expectation of success, see MPEP 2143. As a result, the blocking insulation layer BIL would form a dielectric pillar in FIGs. 18-19.
RE: Claim 21, Lee in view of Park, Lee-2 discloses The apparatus of claim 20, further comprising: a cavity in the first conductive material (FIG. 19 shows a cavity in 163), the conductive pillar (FIG. 19 shows another cavity in 133), or both, wherein the second conductive material is at least partially located in the cavity (FIG. 19 shows 161 located at least partially in the cavities in 163 and 133).
RE: Claim 22, Lee in view of Park, Lee-2 discloses The apparatus of claim 20, wherein the second conductive material is in contact with the first conductive material and the conductive pillar (conductive lines 198 may be electrically connected to the channel structures VS through contact plugs 199, [0110]; Further, Lee discloses a contact area between VS and 199, [0090] therefore, 199 is in electrical contact with VS which includes 133, 163 as shown in FIG. 18).
RE: Claim 24, Lee in view of Park, Lee-2 discloses The apparatus of claim 20, wherein: the bit line is located over the plurality of levels of memory cells, the conductive pillar, and the contact (FIG. 18 shows the bit line 198 located over 199 and VS which includes DA, CL, 133), and
the contact is located between the bit line and the plurality of levels of memory cells (FIG. 18 shows 199 is located between the bit line 198 and VS which includes DA).
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Park, Lee-2 as applied to claim 20 above, and further in view of Kalnitsky.
RE: Claim 25, Lee in view of Park, Lee-2 does not explicitly disclose The apparatus of claim 20, wherein the first conductive material is a first polysilicon material and the second conductive material is a second polysilicon material.
However, in the same field of endeavor, Kalnitsky discloses the first, second and third conductive layers 318, 322, 326 can be made of polysilicon, Col. 6, lines 15-17.
Kalnitsky further teaches that a thin polysilicon layer is conformally deposited over the first insulating layer 108 in the trench 106, Col. 4, lines 25-26.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make 161, 163, 199 each out of polysilicon as taught by Kalnitsky which would allow the conformal deposition of 161 and 163 and therefore result in lower resistance of the contact areas of 161, 163, 199. As a result, 163 would be considered to include a first polysilicon material and 161, 199 would be considered to include a second polysilicon material.
Conclusion
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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