Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/12/2026 has been entered.
Claim Rejections – 35 U.S.C. 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 3 rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Sahu (WO 2018013695) of record
Regarding Claim 1
FIGS. 4 and 5 of Sahu disclose a decoupling capacitor of a chip, comprising: a plurality of p-type devices (418a), comprising: first source/drain contacts (422a) formed over a p-type oxide diffusion (420a); first gates (432), wherein each of the first gates is disposed between a respective pair of the first source/drain contacts (text: For example, the source/drain regions of the pMOS transistors 418a each include a diffusion region 420a, a CA interconnect 422a, and a via V0 424a that connect the source/drain regions of the pMOS transistors 418a to the voltage source 436a); a first bridge (connecting G, S and D of 502a) coupling a first one of the first source/drain contacts, a first one of the first gates, and a second one of the first source/drain contacts; a first metal routing (436a) coupled to the first one of the first source/drain contacts; and a second metal routing (440a) coupled to the second one of the first source/drain contacts; the first metal routing and the second metal routing are coupled together through the first bridge (the first source/drain contacts and the second one of the first source/drain contacts are coupled through the first bridge); and the first metal routing and the second metal routing are coupled to a power rail (Vdd); a plurality of n-type devices (418b), comprising: second source/drain contacts (422b) formed over an n-type oxide diffusion (420b); second gates (432), wherein each of the second gates is disposed between a respective pair of the second source/drain contacts; a second bridge (connecting G, S and D of 502b) coupling a first one of the second source/drain contacts, a first one of the second gates, and a second one of the second source/drain contacts; a third metal routing (440b) coupled to the second one of the second source/drain contacts; and a fourth metal routing (436b) coupled to the first one of the second source/drain contacts, wherein: the third metal routing and the fourth metal routing are coupled together through the second bridge (the first source/drain contacts and the second one of the second source/drain contacts are coupled through the second bridge), and the third metal routing and the fourth metal routing are coupled to a low rail; and the low rail is configured to have a lower potential (Vss) than the power rail (Vdd).
Regarding Claim 3
FIG. 4 of Sahu discloses the first metal routing (436a) is coupled to a third one of the first source/drain contacts (422a).
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 9, 13, 15, 27 and 29 rejected under 35 U.S.C. 103 as being unpatentable over Sahu, in view of Chen (U.S. Patent Pub. No. 2012/0286341) of record, in view of Tsai (U.S. Patent Pub. No. 2014/0021558) of record
Regarding Claim 9
Sahu disclose Claim 1.
Sahu is silent with respect to “the first bridge is a first continuous conductive structure that is formed over and couples together the first one of the first source/drain contacts, the first one of the first gates, and the second one of the first source/drain contacts; the first bridge is formed from a gate contact layer disposed below a metal routing layer; the second bridge is a second continuous conductive structure that is formed over and couples together the first one of the second source/drain contacts, the first one of the second gates, and the second one of the second source/drain contacts; the second bridge is formed from the gate contact layer disposed below the metal routing layer; the first metal routing and the second metal routing are formed from the metal routing layer above the gate contact layer; and the third metal routing and the fourth metal routing are formed from the metal routing layer above the gate contact layer”.
FIG. 2 of Chen discloses a similar chip, comprising a first bridge (connecting 50A1 and 54) coupling a first one of the first source/drain contacts (left 54), a first one of the first gates (50A1), and a second one (right 54) of the first source/drain contacts; the first bridge is a first continuous conductive structure that is formed over and couples together the first one of the first source/drain contacts, the first one of the first gates, and the second one of the first source/drain contacts, and the first bridge is formed from a gate contact layer (contact of 50A1 and vertical line of 30) disposed below a metal routing layer (40); the first metal routing and the second metal routing are coupled together through the first bridge (FIG. 1); and the first gate contact is formed from the gate contact layer; a third metal routing (vertical line of 30 connecting right 54) coupled to the second one of the second source/drain contacts. It would have been obvious to one of ordinary skill in the art to modify the device of Sahu, as taught by Chen, such that a second bridge coupling a first one of the second source/drain contacts, a first one of the second gates, and a second one of the second source/drain contacts, the second bridge is a second continuous conductive structure that is formed over and couples together the first one of the second source/drain contacts, the first one of the second gates, and the second one of the second source/drain contacts; the second bridge is formed from the gate contact layer disposed below the metal routing layer; and a fourth metal routing coupled to the first one of the second source/drain contacts, because mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See MPEP 2144.04.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Sahu, as taught by Chen, because the claimed configuration was a matter of choice, which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant. In re Dailey 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton 97 US 3,24 (USSC 1878). MPEP 2144.04. The ordinary artisan would have been motivated to modify Sahu in the above manner for purpose of decoupling capacitors ([0005] of Chen).
Sahu as modified by Chen is silent with respect to “the first metal routing and the second metal routing are formed from a metal layer above the gate contact layer”.
FIG. 6 of Tsai discloses a similar chip, comprising a first gate contact (154) disposed on a second one of the first gates (91); and a first via [0037] coupled between the first gate contact and the second metal routing (180), wherein the first metal routing (181) is formed from a metal layer above the gate contact layer. It would have been obvious to one of ordinary skill in the art to modify the device of Sahu, as taught by Tsai, such that the second metal routing is formed from a metal layer above the gate contact layer, because mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See MPEP 2144.04.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Sahu, as taught by Tsai, because the claimed configuration was a matter of choice, which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant. In re Dailey 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton 97 US 3,24 (USSC 1878). MPEP 2144.04. The ordinary artisan would have been motivated to modify Sahu in the above manner for purpose of providing voltage sources ([0029] of Tsai).
Regarding Claim 13
FIG. 4 of Sahu discloses the first metal routing is coupled to a third one of the first source/drain contacts, a fourth one of the first source/drain contacts, and a fifth one of the first source/drain contacts, the second metal routing is coupled to a sixth one of the first source/drain contacts, a second one of the first gates, and a third one of the first gates, the third metal routing is coupled to a third one of the second source/drain contacts, a second one of the second gates, and a third one of the second gates, the fourth metal routing is coupled to a fourth one of the second source/drain contacts, a fifth one of the second source/drain contacts, and a sixth one of the second source/drain contacts.
Regarding Claim 15
FIG. 4 of Sahu discloses each of the first gates and the second gates (432) extends in a first direction, the second metal routing and the third metal routing are parallel and adjacent to each other, each of the first metal routing (436a), the second metal routing (440a), the third metal routing (436b), and the fourth metal routing (440b) extends in a second direction that is perpendicular to the first direction, and the first metal routing, the second metal routing, the third metal routing, and the fourth metal routing are spaced apart in the first direction.
Regarding Claim 27
FIG. 4 of Sahu discloses the low rail (VSS) is coupled to a ground.
Regarding Claim 29
FIG. 4 of Sahu discloses the first bridge is between the first metal routing and the second metal routing in the first direction.
Claim 30 rejected under 35 U.S.C. 103 as being unpatentable over Sahu, Chen and Tsai, in view of Jarrar (U.S. Patent No. 10,497,794) of record
Regarding Claim 30
Sahu as modified by Chen and Tsai discloses Claim 15.
Sahu as modified by Chen and Tsai is silent with respect to “a second via coupled between the first one of the first source/drain contacts and the first metal routing; and a third via coupled between the second one of the first source/drain contacts and the second metal routing, wherein the third via and the second via are spaced apart in the first direction”.
FIG. 3 of Jarrar discloses a similar chip, comprising a second via (48) coupled between the first one of the first source/drain contacts (SD) and the first metal routing; and a third via (62) coupled between the second one of the first source/drain contacts and the second metal routing, wherein the third via and the second via are spaced apart in the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chen, as taught by Jarrar. The ordinary artisan would have been motivated to modify Chen in the above manner for purpose of improving capacitor structures (Col. 1, Lines 23-25 of Jarrar).
Pertinent Art
US 20140246715 discloses decoupling capacitors formed between gate and source/drain contacts. US 20170352651 discloses a bridge coupling a first one of the first source/drain contacts; a first metal routing coupled to the first one of the first source/drain contacts; and a second metal routing coupled to the second one of the first source/drain contacts. US 20150228641 discloses the first metal routing and the second metal routing are formed from a metal layer above the contact layer. Pertinent art also includes US 20120187494 and 20210273119.
Response to Arguments
Applicant’s arguments with respect to Claim 1 have been considered but they are not persuasive. FIGS. 4 and 5 of Sahu disclose a decoupling capacitor of a chip, comprising: a plurality of p-type devices (418a), comprising: first source/drain contacts (422a) formed over a p-type oxide diffusion (420a); first gates (432), wherein each of the first gates is disposed between a respective pair of the first source/drain contacts (text: For example, the source/drain regions of the pMOS transistors 418a each include a diffusion region 420a, a CA interconnect 422a, and a via V0 424a that connect the source/drain regions of the pMOS transistors 418a to the voltage source 436a); a first bridge (connecting G, S and D of 502a) coupling a first one of the first source/drain contacts, a first one of the first gates, and a second one of the first source/drain contacts; a first metal routing (436a) coupled to the first one of the first source/drain contacts; and a second metal routing (440a) coupled to the second one of the first source/drain contacts; the first metal routing and the second metal routing are coupled together through the first bridge (the first source/drain contacts and the second one of the first source/drain contacts are coupled through the first bridge); and the first metal routing and the second metal routing are coupled to a power rail (Vdd); a plurality of n-type devices (418b), comprising: second source/drain contacts (422b) formed over an n-type oxide diffusion (420b); second gates (432), wherein each of the second gates is disposed between a respective pair of the second source/drain contacts; a second bridge (connecting G, S and D of 502b) coupling a first one of the second source/drain contacts, a first one of the second gates, and a second one of the second source/drain contacts; a third metal routing (440b) coupled to the second one of the second source/drain contacts; and a fourth metal routing (436b) coupled to the first one of the second source/drain contacts, wherein: the third metal routing and the fourth metal routing are coupled together through the second bridge (the first source/drain contacts and the second one of the second source/drain contacts are coupled through the second bridge), and the third metal routing and the fourth metal routing are coupled to a low rail; and the low rail is configured to have a lower potential (Vss) than the power rail (Vdd).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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