DETAILED ACTION
This Office Action is in response to Amendment filed March 31, 2026.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-3 and 5-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention. Regarding claim 1, Applicants did not originally disclose the step of “mechanically roughening a first surface of the bulk substrate facing away from the semiconductor device thereby making the first surface not composed of (000-1) oriented crystal planes” recited on lines 4-6, because (a) Applicants originally disclosed in paragraph [0031] of current application that “A first surface of the bulk substrate facing away from the semiconductor device is mechanically roughened 701 such that the first surface is not predominantly composed of (000-1) oriented crystal planes”, (b) however, Applicants did not originally disclose that the step of mechanically roughening makes “the first surface not composed of (000-1) oriented crystal planes” as recited on lines 4-6, and (c) in other words, Applicants originally disclosed that the mechanically roughened surface has some (000-1) oriented crystal planes but is not predominantly (000-1) oriented, but did not originally disclose that the mechanically roughened surface does not have (000-1) oriented crystal planes as implied in the limitation recited on lines 4-6 of the amended claim 1. Claims 2, 3 and 5-10 depend on claim 1, and therefore, claims 2, 3 and 5-10 also fail to comply with the written description requirement.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 5-13 and 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claim 1, it is not clear what the newly added limitation “the first surface not composed of (000-1) oriented crystal planes” recited on lines 5-6 suggests, because (a) as discussed above under 35 USC 112(a) rejection, Applicants did not originally disclose the newly added limitation cited above, (b) therefore, it is not clear whether the limitation cited above implies that “the first surface” does not comprise any “(000-1) oriented crystal planes”, or “the first surface” can comprise a single (000-1) oriented crystal plane, but should not comprise two or more (000-1) oriented crystal planes.
(2) Also regarding claim 1, it is not clear how the step of “mechanically roughening a first surface of the bulk substrate facing away from the semiconductor device” has anything to do with “making the first surface not composed of (000-1) oriented crystal planes” as recited on lines 4-6, because (a) “a first surface of the bulk substrate” exists before the step of “mechanically roughening a first surface of the bulk substrate” is performed, and (b) it appears that Applicants may have intended to claim that the step of “mechanically roughening a first surface of the bulk substrate” alters the surface orientation(s), surface roughness(es) and/or surface texture(s) of “a first surface” to form an altered or roughened surface rather than “making the first surface not composed of (000-1) oriented crystal planes”.
(3) Further regarding claim 1, it is not clear whether “the first surface” recited on line 5 refers to “a first surface” recited on line 4, because (a) Applicants claim that “the first surface not composed of (000-1) oriented crystal planes” on lines 5-6, (b) however, “a first surface” recited on line 4 before the step of mechanically roughening is performed should be a flat surface as shown in Fig. 2 of current application, which is also illustrated below, (c) in this case, “a first surface” recited on line 4 would inherently be “not composed of (000-1) oriented crystal planes” as recited on lines 5-6 since, whatever the surface orientation of the first surface of the bulk substrate of n-type GaN is before the step of mechanically roughening is performed, the first surface is composed of a single crystal plane rather than a plurality of (000-1) oriented crystal planes, and (d) in other words, either the limitation “the first surface not composed of (000-1) oriented crystal planes” recited on lines 5-6 is inherent, which does not appear to be Applicants’ intention, or the limitation “the first surface” recited on line 5 lacks antecedent basis since “the first surface” recited on line 5 does not refer to “a first surface” recited on line 4.
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(4) Regarding claims 1 and 11, it is not clear what “the roughened first surface” recited on line 7 of claims 1 and 11 refers to, because (a) “a first surface of the bulk substrate” recited on line 4 of claims 1 and 11 should refer to a surface corresponding to the horizontal line illustrated above, which is the top surface of the Bulk GaN 200, (b) the newly added limitation “the roughened first surface” should refer to a corrugated surface 202 shown above, (c) also, Applicants originally disclosed in paragraph [0019] of current application that “A wafer grind (fixed abrasive) process (as represented by grinder 206), lapping, or other similar thinning creates a first surface 202 that may be characterized by a multiplicity of exposed planes, as distinct from a smooth surface consisting exclusively or predominantly of the N face of the GaN crystal, which is a (0001) plane (emphasis added)”, (d) therefore, it appears that, while “a first surface” recited on line 4 of claims 1 and 11 should be the flat surface illustrated above, Applicants claim as if the term “a first surface” of the limitation “mechanically roughening a first surface of the bulk substate” is a surface created as a result of the step of the mechanically roughening by using the same term “a first surface” mentioned in paragraph [0019] of current application with a different meaning, (e) however, the limitation “a first surface” recited in claims 1 and 11 is different from “a first surface” mentioned in paragraph [0019] of current application since the former is a surface before the step of mechanically roughening is carried out, and the latter is a surface after the step of mechanically roughening is carried out, (f) in this case, there would be no “roughened first surface” since the roughened surface created as a result of the step of mechanically roughening the first surface is not exactly related to the first surface that existed only before the step of mechanically roughening is performed since the original/initial first surface and the roughened surface are disposed at different levels and with different roughnesses, and (g) therefore, unless the step of mechanically roughening is performed to remove less than a monolayer of the bulk substrate, and therefore, there is a vestige of the first surface after the step of mechanically roughening is performed, the limitation “the roughened first surface” would be indefinite since there would be no trace of “a first surface” after the step of mechanically roughening is performed.
(5) Regarding claim 11, it is not clear what the limitation “mechanically roughening a first surface of the bulk substrate facing away from the semiconductor device to break molecular bonds at the first surface resulting” recited on lines 4-5 suggests, because (a) the limitation appears to be incomplete, and (b) it is not clear what results from the step of “mechanically roughing a first surface of the bulk substrate”.
Claims 2, 3 and 5-10 depend on claim 1, and claims 12, 13 and 15-20 depend on claim 11, and therefore, claims 2, 3, 5-10, 12, 13 and 15-20 are also indefinite.
(6) Regarding claim 16, it is not clear how “a negative electrical contact” can be formed “on the roughened first surface” as recited on line 7 of claim 11 when the step of “chemically treating the roughened surface using a wet etch chemical” is performed “before forming the negative electrical contact”, because (a) it is not clear whether “the roughened first surface” recited in claim 11 is the same with or different from “the roughened surface” recited in claim 16, and (b) if they are the same surface, it is not clear how one can form “a negative electrical contact on the roughened first surface” after the step of chemically treating the roughened surface recited in claim 16 is carried out since (i) the roughened surface may become flat by the step of chemically treating, and (ii) at least the step of chemically treating recited in claim 16 would alter the surface roughness of the already roughened surface, and therefore, the negative electrical contact cannot exactly be formed “on the roughened first surface”. Claim 17 depends on claim 16, and therefore, claim 17 is also indefinite.
(7) Regarding claim 19, claim 19 is indefinite for the same reasons stated above with regard to claim 1; in other words, the two limitations “the first surface” on line 2 do not refer to the same “first surface”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-13 and 15-20, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Sonoda et al. (US 2009/0141502) in view of Wakai et al. (US 10,381,516)
Regarding claim 1, Sonoda et al. disclose a method, comprising: forming a semiconductor device (device structure formed on n-GaN 600, which is disposed under n-GaN 600 in Fig. 6) ([0039]) on a bulk substrate of n-type GaN (not-shown n-GaN substrate before roughened surface 622 is formed similar to GaN substrate 400 shown in Fig. 4a) ([0031]), the semiconductor device comprising an epitaxial layer ([0017], epitaxial growth layer of n-GaN layer 602 in [0039], and [0041]); roughening a first surface (surface of not-shown n-GaN substrate before roughened surface 622 is formed) of the bulk substrate facing away from the semiconductor device thereby making the first surface not composed of (000-1) oriented crystal planes, because (a) as discussed above under 35 USC 112(b) rejections, this limitation is indefinite, and (b) in addition, before the roughening step, the surface of the bulk substrate should be oriented along a certain direction, and thus would not comprise a plurality of crystal planes, not to mention a plurality of “(000-1) oriented crystal planes” recited in claim 1; and forming a negative electrical contact (618) ([0039]) on the roughened first surface using a low work function metal (Ti/Al or their metal), because (a) the limitation “the roughened first surface” is indefinite as discussed above under 35 USC 112(b) rejections, and (b) Applicants’ low function metal is formed of Ti, Al and/or TiN as recited in claim 8.
Sonoda et al. differ from the claimed invention by not showing that the roughening is a mechanically roughening.
Wakai et al. disclose a method (col. 1, line 59 - col. 2, line 5), comprising mechanically roughening a first surface of a bulk substrate (grinding GaN substrate) to improve light emitting efficiency, which is also the function of the roughened surface 622 of Sonoda et al.
Since both Sonoda et al. and Wakai et al. teach a method, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the roughening disclosed by Sonoda et al. can be a mechanically roughening disclosed by Wakai et al., because (a) both roughened surfaces disclosed by Sonoda et al. and Wakai et al. are formed opposite to light emitting layers to improve light emitting efficiency, and (b) therefore, the roughened surface 622 shown in Fig. 6 of Sonoda et al. can be formed by using the method disclosed by Wakai et al. including the mechanical roughening to improve light emitting efficiency.
Please refer to the explanations of the corresponding limitations above.
Regarding claim 11, Sonoda et al. disclose a method, comprising: forming a semiconductor device (device structure formed on n-GaN 600 in Fig. 6) on a bulk substrate of n-type GaN (600), the semiconductor device comprising an epitaxial layer (layer including 602) grown on the bulk substrate; roughening a first surface of the bulk substrate facing away from the semiconductor device to inherently break molecular bonds at the first surface resulting, because (a) this limitation is indefinite as discussed above under 35 USC 112(b) rejections, and (b) the step of forming the roughened surface 622 shown in Fig. 6 of Sonoda et al. exposes the atoms that were buried before the roughening is performed, and therefore, breaking of molecular bonds of those buried atoms would occur at the first surface; and forming a negative electrical contact (618) on the roughened first surface using a low work function metal (Ti/Al or their metal).
Sonoda et al. differ from the claimed invention by not showing that the roughening is a mechanically roughening.
Wakai et al. disclose a method (col. 1, line 59 - col. 2, line 5), comprising mechanically roughening a first surface of a bulk substrate (grinding GaN substrate) to improve light emitting efficiency.
Since both Sonoda et al. and Wakai et al. teach a method, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the roughening disclosed by Sonoda et al. can be a mechanically roughening disclosed by Wakai et al., because (a) both roughened surfaces disclosed by Sonoda et al. and Wakai et al. are formed opposite to light emitting layers to improve light emitting efficiency, and (b) therefore, the roughened surface 622 shown in Fig. 6 of Sonoda et al. can be formed by using the method disclosed by Wakai et al. including the mechanical roughening.
Regarding claims 2 and 12, Wakai et al. further disclose that the mechanically roughening of the first surface comprises wafer grinding (grinding GaN substrate) or lapping the first surface.
Regarding claims 3 and 13, Sonoda et al. in view of Wakai et al. differ from the claimed invention by not showing that the wafer grinding or lapping is performed using particles having a particle size of 6 µm or more (claim 3), and the wafer grinding or lapping uses a particle size of 6 µm or more (claim 13).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the wafer grinding or lapping can use a particle size of 6 µm or more, because (a) the particle size should be selected and optimized according to wavelength of light emitted from the light emitting device to improve light emitting efficiency through the roughened surface since the particle size of the particles used during the wafer grinding or lapping would approximately correspond to the roughness of the roughened surface, and (b) the claims are prima facie obvious without showing that the claimed range of the particle size achieves unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claims 5 and 15, Sonoda et al. further disclose for the method of claims 1 and 11 that after forming the negative electrical contact (618), the negative electrical contact is not exposed to any anneal of > 300°C or an anneal of more than one minute at > 200°C, because the step of forming the negative electrical contact 618 is the final step of the manufacturing process disclosed by Sonoda et al.
Regarding claims 6, 7, 16 and 17, Sonoda et al. in view of Wakai et al. differ from the claimed invention by not further comprising chemically treating the first surface using a wet etch chemical before forming the negative electrical contact (claims 6 and 16), wherein the wet etch chemical comprises any combination of HCI and HF containing a buffered oxide etch (claims 7 and 17).
Wakai et al. further disclose that “the ground surface is further chemically treated (dry etching) to form circular cones in high density as micro concaves/convexes” on lines 65-67 of column 1.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the method disclosed by Sonoda et al. in view of Wakai et al. can further comprise chemically treating the first surface using a wet etch chemical before forming the negative electrical contact, wherein the wet etch chemical comprises any combination of HCI and HF containing a buffered oxide etch, because (a) a dry etching and a wet etching have been commonly and interchangeable employed in manufacturing semiconductor devices, depending on the manufacturing processes, optimal etching methods and manufacturing costs, and (b) a wet chemical etching by HCl and HF containing a buffered oxide etch has been commonly employed in semiconductor manufacturing processes instead of a dry etching due to their well-known etching parameters such as an etching rate, a preferential etching direction, an etch selectivity, etc.
Regarding claims 8-10 and 18-20, Sonoda et al. further disclose for the method of claims 1 and 11 that the low work function metal (Ti/Al or their metal) comprises at least one of Ti, Al, or TiN (claims 8 and 18), the mechanical roughening of the first surface of the bulk substrate results in broken molecular bonds at the first surface, because (a) the step of forming the roughened surface 622 shown in Fig. 6 of Sonoda et al. exposes the atoms that were buried before the roughening is performed, and (b) therefore, broken molecular bonds of those initially buried atoms at the first surface would occur during and after the roughening step (claim 9), the epitaxial layer comprises a p-type epitaxial layer (606) ([0039]), the method further comprising forming a positive electrical contact (608, 612 and/or 616) ([0039]) on the p-type epitaxial layer (claims 10 and 20), and the mechanical roughening of the first surface of the bulk substrate results in the first surface not being predominantly composed of (000-1) oriented crystal structures, because this limitation is indefinite as discussed above (claim 19).
Response to Arguments
Applicants' arguments filed March 31, 2026 have been fully considered but they are not persuasive, especially because the amended claim 1 fails to comply with the written description requirement, and both the amended claims 1 and 11 are still indefinite.
Applicants’ arguments traversing the 35 USC 103 rejection of claims 1 and 11 and their dependent claims in the REMARKS filed March 31, 2026 are based on Applicants’ mere allegations or opinions without any substantiating evidence. Applicants simply argue that the teachings of Sonoda et al. and Wakai et al. cannot be combined, because the detailed features that Sonoda et al. and Wakai et al. disclose are not the same. However, the Examiner used the secondary reference of Wakai et al. in the Non Final Office Action mailed December 31, 2025 to show that the roughening step disclosed by the primary reference of Sonoda et al. can be mechanical. In response to Applicants' arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Furthermore, Applicants’ arguments also appear to be related to a bodily incorporation of the entire teachings of the secondary reference of Wakai et al. into the teachings of Sonoda et al. even though the Examiner only used a portion of the teachings of Wakai et al. In other words, the Wakai et al. reference was used to show that a micrometer-scale roughness structure or lens can be formed by a step of mechanically roughening, not to incorporate all the other teachings of Wakai et al. The Examiner believes that Applicants did not provide any substantiating evidence that the step of mechanically roughening disclosed by Wakai et al. to form a micrometer-scale roughness structure or lens cannot be employed for the step of roughening disclosed by Sonoda et al.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Matsubara et al. (US 8,633,087)
Bruderl et al. (US 2006/0172506)
Eichler et al. (US 7,943,484)
Kagawa et al., “AlGaN/GaN/3C-SiC on diamond HEMTs with thick nitride layers prepared by bonding-first process,” Applied Physics Express 15 (2022) 041003.
Applicants' amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 April 7, 2026
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