DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amended title is sufficiently specific.
The amendments to the specification overcome the objections.
The claim amendments overcome the 112 rejections.
See the new art rejections below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 8, and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Luo, US 2022/0199637 A1, in view of Lee, KR 2017-0042449 A, and Hopkins, US 2021/0358805 A1. Claims 19, 21, 25, 30 are rejected over Luo in view of Matsuno, US 2022/0254728 A1.
Claim 1: Luo discloses
a stack structure including a cell array region (right hand side FIG. 10) and a contact region (left hand side FIG. 10) with a stepped structure, the contact region extending from the cell array region, the stack structure including a plurality of interlayer insulating layers and a plurality of conductive patterns, which are alternately stacked in a first direction (vertical);
a channel structure (652) extending through the cell array region of the stack structure in the first direction (FIG. 10);
a memory layer (“MONOS”, [0108]) between the channel structure and the stack structure;
a groove (120) defined in the contact region of the stack structure;
a filling insulating layer (130) inside the groove;
a barrier insulating layer (126 and/or 128) disposed between the filling insulating layer and the stack structure, the barrier insulating layer extending along a sidewall of the groove and a bottom surface of the filling insulating layer;
“Referring to FIG. 1B, the filled trenches 120 may individually be filled with multiple (e.g., more than one) dielectric materials. For example, as shown in FIG. 1B, each filled trench 120 may include a first dielectric material 126 (e.g., a dielectric liner material), a second dielectric material 128 (e.g., an additional dielectric liner material), and a third dielectric material 130 (e.g., a dielectric fill material). For an individual filled trench 120, the first dielectric material 126 may be formed on or over surfaces (e.g., horizontally extending surfaces, vertically extending surfaces) of the stadium structure 114 (e.g., the first stadium structure 114A), the crest regions 122, and the bridge regions 124 (FIG. 1A) of the preliminary block 110 (FIG. 1A) defining boundaries (e.g., horizontal boundaries, vertical boundaries) of the filled trench 120; the second dielectric material 128 may be formed on or over the first dielectric material 126; and the third dielectric material 130 may be formed on or over the second dielectric material 128. As depicted in FIG. 1B, one or more (e.g., each) of the first dielectric material 126, the second dielectric material 128, and the third dielectric material 130 may also be formed to extend beyond boundaries (e.g., horizontal boundaries, vertical boundaries) of the filled trenches 120. For example, first dielectric material 126, the second dielectric material 128, and the third dielectric material 130 may also be formed to extend over uppermost surfaces of the crest regions 122 and/or the bridge regions 124 (FIG. 1A) of individual preliminary blocks 110 (FIG. 1A) of the preliminary stack structure 102 (FIG. 1A) of the microelectronic device structure 100.” [0050].
and at least one conductive gate contact (140) penetrating the filling insulating layer, the barrier insulating layer.
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Luo does not explicitly disclose that the conductive gate contacts penetrate the stepped structure of the stack structure. However, this was common in the art. See Lee FIG. 10K.
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It would have been obvious to have had this in Luo to facilitate connection of the gate contacts.
Luo does not disclose that each of the barrier insulating layer and the plurality of interlayer insulating layers has a higher oxygen content than that of the filling insulating layer. However, this was known in the art. See Hopkins, which discloses that each of the barrier insulating layer (70, silicon oxide, [0055]) and the plurality of interlayer insulating layers (28, silicon oxide, [0047]) has a higher oxygen content than that of the filling insulating layer (76, fluorosilicate glass, [0061]). Silicon oxide is SiO2, with an oxygen content of 66.7 at%. Fluorosilicate glass is a silica (SiO2) with fluorine added, which reduces the oxygen fraction of the glass relative to silica, and thus the filling insulating layer has a lower oxygen content (how much lower depending on how much fluorine and potentially other additives are in the glass). It would have been obvious to have used these materials in Luo as known in the art for 3D memory devices with a stairstep structure such as Luo discloses.
Note: Hopkins at [0055] discloses that “the liner material 70 may comprise, consist essentially of, or consist of one or more of SiO, AlO, HfO, ZrO, and TaO; where the chemical formulas indicate primary constituents rather than specific stoichiometries.” By far the most stable and commonly used oxide of silicon is silicon dioxide, and thus those in the art would understand this to be primarily what is referred to by Hopkins, and thus the calculation is based on silicon dioxide.
Claim 2: the sidewall of the groove is defined by the stack structure. The front and back sidewalls of the groove 120 are defined by the stack structure, FIG. 1A. The left sidewall is also defined by the stack structure, in that the height of the sidewall is determined by the height of the stack structure.
Luo [0050] discloses or suggests that the entire opening 120, including vertical surfaces, is covered by the layers 126 and 128: “the filled trenches 120 may individually be filled with multiple (e.g., more than one) dielectric materials. For example, as shown in FIG. 1B, each filled trench 120 may include a first dielectric material 126 (e.g., a dielectric liner material), a second dielectric material 128 (e.g., an additional dielectric liner material), and a third dielectric material 130 (e.g., a dielectric fill material).”
Claim 8: the filling insulating layer is formed of a material different from a material of the stack structure. The stack structure is formed in part by the insulating layers 104, which can be made of a number of materials listed at [0034] that are different than the materials of filling insulating layer 130 [0056], e.g. ZrOx.
Claim 11: the filling insulating layer is formed of a SiNy ([0054]), SiOxNy or a SixOy, wherein x is less than y for the SiOxNy (x=0), and wherein x is greater than y for the SixOy.
Claim 12: Luo discloses a first slit (124) penetrating the filling insulating layer while facing the third sidewall.
Claim 13: the first slit includes a sidewall defined by the filling insulating layer (FIG. 4B).
Claim 19: Luo discloses
a lower stack structure (114D, FIG. 1A) including a plurality of first interlayer insulating layers (104) and a plurality of first conductive patterns (134), which are alternately stacked in a first direction;
a channel structure (652) extending in a cell array region of the lower stack structure;
a memory layer (“MONOS”, [0108]) between the channel structure and the lower stack structure;
a first stepped groove (120, righthand side, FIG. 1A) spaced apart from the channel structure (FIG. 10), the first stepped groove penetrating the lower stack structure;
a first barrier insulating layer (126 and/or 128) covering a surface of the first stepped groove [0050];
a first filling insulating layer (130) disposed inside the first stepped groove, the first filling insulating layer being formed on the first barrier insulating layer [0050];
an upper stack structure (114C) including a plurality of second conductive patterns (134) and a plurality of second interlayer insulating layers (104), which are alternately stacked, wherein the upper stack structure extends onto the cell array region of the lower stack structure, and the channel structure and the memory layer extend in the upper stack structure;
As seen in FIG. 10, the channel and memory structures extend to all the stack structures.
a second stepped groove (114C) spaced apart from the channel structure, the second stepped groove penetrating the upper stack structure (FIGS. 1 and 10);
a second barrier insulating layer (126 and/or 128 over 114C) covering a surface of the second stepped groove ([0050]);
a second filling insulating layer (130 over 114C) disposed inside the second stepped groove, the second filling insulating layer being formed on the second barrier insulating layer;
a first conductive gate contact (140 over 114D) penetrating the second filling insulating layer, the second barrier insulating layer, and the lower stack structure; and
a second conductive gate contact (140 over 114C) penetrating the upper stack structure, the first filling insulating layer, and the first barrier insulating layer.
Claim 19 recites that the upper stack structure includes “a plurality of second conductive patterns and a plurality of second interlayer insulating layers, which are alternately stacked over the first filling insulating layer in the first direction”. This could be met by Luo under a broad definition of over, as in “I have a flag flying over my front door”, even though the flag is to the front of the door. Under a narrower definition (directly above), this was known in the art. See Matsuno, FIG. 8A, which discloses a plurality of second conductive patterns (sacrificial layers 242L are replaced by those conductive patterns) and a plurality of second interlayer insulating layers (232L), which are alternately stacked over the first filling insulating layer (165) in the first direction. It would have been obvious to have applied the invention of Luo to the structure of Matsuno as a very similar memory stack manufactured by a known method.
Claim 21: Lou discloses at [0040] that “at least one stadium structures 114 may be modified to include a forward staircase structure 116A but not a reverse staircase structure 116B (e.g., the reverse staircase structure 116B may be absent), or at least one stadium structure 114 may be modified to include a reverse staircase structure 116B but not a forward staircase structure 116A (e.g., the forward staircase structure 116A may be absent).” In such a case, the first stepped groove includes a first sidewall (front wall, FIG. 1A) with a stepped structure, a second sidewall (back wall, FIG. 1A) facing the first sidewall, and a third sidewall (bottom left wall, where staircase 116B would be missing) between the first sidewall and the second sidewall, and wherein the first barrier insulating layer extends along the first sidewall, the second sidewall, and the third sidewall of the first stepped groove ([0050]).
Claim 25: Lou discloses at [0040] that “at least one stadium structures 114 may be modified to include a forward staircase structure 116A but not a reverse staircase structure 116B (e.g., the reverse staircase structure 116B may be absent), or at least one stadium structure 114 may be modified to include a reverse staircase structure 116B but not a forward staircase structure 116A (e.g., the forward staircase structure 116A may be absent).” In such a case, the second stepped groove includes a first sidewall (front wall, FIG. 1A) with a stepped structure, a second sidewall (back wall, FIG. 1A) facing the first sidewall, and a third sidewall (bottom left wall, where staircase 116B would be missing) between the first sidewall and the second sidewall, and wherein the second barrier insulating layer extends along the first sidewall, the second sidewall, and the third sidewall of the second stepped groove ([0050]).
Claim 30: each of the first filling insulating layer and the second filling insulating layer includes a SiNy (SiN, [0054]), a SiOxNy, or a SixOy, wherein x is less than y for the SiOxNy, andwherein x is greater than y for the SixOy.
Claims 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Luo in view of Lee, Hopkins, and Kai, US 2021/0335805 A1. Claims 22-24 and 26-28 are rejected under 35 U.S.C. 103 as being unpatentable over Luo in view of Lee, Matsuno, and Kai.
Claim 3: Luo discloses that the stack structure includes a plurality of interlayer insulating layers (104) and a plurality of conductive patterns (134), which are alternately stacked in a length direction of the channel structure.
Lou does not show that each of the plurality of conductive patterns includes a first part surrounding the channel structure and a second part extending from the first part to form the stepped structure, and that a thickness of the second part is different from a thickness of the first part. See Kai, FIG. 9E, which teaches this feature:
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It would have been obvious to have had such a structure for the conductive pattern as known in the art.
Claim 4: the plurality of conductive patterns include a contact-conductive pattern in contact with the conductive gate contact and a separation-conductive pattern spaced apart from the conductive gate contact.
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Claim 5: a portion (top) of the contact-conductive pattern connected to the conductive gate contact corresponds to the second part.
Claim 6: Luo discloses a contact insulating pattern disposed between the separation-conductive pattern and the conductive gate contact.
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Claim 7: the separation-conductive pattern is disposed at at least one level among levels upper and lower than the contact-conductive pattern. See the annotated figure above; the separation-conductive pattern is disposed at an upper level.
Claim 22: each of the plurality of first conductive patterns includes a first part surrounding the channel structure and a second part extending from the first part to form the stepped structure of the first stepped groove, and wherein a thickness of the second part is different from a thickness of the first part:
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Claim 23: the plurality of first conductive patterns include a contact-conductive pattern connected to the second conductive gate contact and a separation-conductive pattern spaced apart from the second conductive gate contact, and wherein a portion of the contact-conductive pattern (top) contacting the second conductive gate contact corresponds to the second part.
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Claim 24: Luo discloses a contact insulating pattern disposed between the separation-conductive pattern and the second conductive gate contact.
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Claim 26: each of the plurality of second conductive patterns includes a first part surrounding the channel structure and a second part extending from the first part to form the stepped structure of the second stepped groove, and wherein a thickness of the second part is different from a thickness of the first part.
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Claim 27: the plurality of second conductive patterns include a contact-conductive pattern connected to the first conductive gate contact and a separation-conductive pattern spaced apart from the first conductive gate contact, and wherein a portion of the contact-conductive pattern connected to the first conductive gate contact corresponds to the second part.
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Claim 28: Luo discloses a plurality of contact insulating patterns disposed between the separation-conductive pattern among the plurality of second conductive patterns and the first conductive gate contact and between the plurality of first conductive patterns and the first conductive gate contact.
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Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Luo in view of Lee, Hopkins, and Hanifi, “Independent but Additive Effects of Fluorine and Nitrogen Substitution on Properties of a Calcium Aluminosilicate Glass", J. Am. Ceram. Soc., 95 [2] 600–606 (2012). Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Luo in view of Matsuno, Hopkins, and Hanifi.
Claim 9: Hopkins discloses at 61 that the fill material may be “doped silicate glass (e.g., borophosphosilicate glass, phosphosilicate glass, fluorosilicate glass, etc.).” Hanifi discloses a doped silicate glass (calcium aluminosilicate glass doped with fluorine nitrogen) which has a high young’s modulus and microhardness (p. 600). It would have been obvious to use such a material as being a material that Hopkins discloses is an appropriate fill material, which has good strength properties. Note as aluminum oxide and calcium oxide have a lower fraction of oxygen atoms (3/5 and ½, respectively) than silicon oxide (2/3), and also because nitrogen and fluorine and substituted for oxygen in Hanifi, the oxygen level will be lower than the silicon oxide layers claimed in claim 1. Because the layer will have nitride, and the silicon oxide barrier layer, which is silicon oxide (see claim 1) has none, the filling insulating layer includes a higher content of at least one of nitrogen and silicon as compared with the barrier insulating layer.
Claim 29: in Luo in view of Hopkins and Hanifi, as set forth with respect to claim 9, each of the first filling insulating layer and the second filling insulating layer includes a higher content of at least one of nitrogen and silicon (nitrogen) as compared with the first barrier insulating layer, the second barrier insulating layer, the plurality of first interlayer insulating layers, and the plurality of second interlayer insulating layers, as these other layers are silicon oxide, and have no nitrogen.
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Luo in view of Lee, Hopkins, and Lee ‘696, US 2022/0208696 A1.
Claim 14: Luo does not disclose the claimed dummy hole and plug. However, it was well-known in the art to use dummy channels for structural support of the device. See Lee, which discloses
a dummy hole (272) penetrating a portion of the stack structure, which extends along the third sidewall of the groove;
an insulating layer (282) extending along a sidewall of the dummy hole; and
a dummy plug (286) disposed inside the dummy hole.
It would have been obvious to have had such dummy structures to support the device of Luo; see Lee ‘696 [0155].
Claim 15: the stack structure includes a plurality of interlayer insulating layers (Luo 104; Lee ‘696 240) and a plurality of conductive patterns (Luo 134; Lee ‘696 297), which are alternately stacked in a length direction of the channel structure, wherein the plurality of interlayer insulating layers includes an upper insulating layer and a lower insulating layer (above and below WL1), which are adjacent to each other in the first direction, and wherein the insulating layer protrudes to a space between the upper insulating layer and the lower insulating layer (FIG. 24).
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Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Luo in view of Matsuno and Oh, US 2020/0161326 A1. Luo FIG. 10 discloses an arrangement in which the various stepped grooves 120 (see 614 in FIG. 10) are to the side of the cell region (to the right in FIG. 10). However, there were other common arrangements. See Oh, FIG. 9, which shows the memory region to the left of the connection regions arranged serially to the right. It would have been obvious to have used such an arrangement in Luo as a mere rearrangement of parts in a known configuration. In such a case, the second stepped grooves and the first conductive gate contact are disposed between the channel structure and the first stepped groove.
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Note that the gate contacts are not shown in Oh FIG. 9, but are structures 140 of Luo that are in the stepped regions.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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