DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner proposes SEMICONDUCTOR MEMORY WITH BARRIER LAYER
The specification is objected to because:
reference characters “CP” and “CP2” have both been used to designate second conductive patterns (e.g. [00108], [00109]).
Reference characters 102 and 103 have both been used to designate the lower second material layer (e.g. [00172]).
Paragraph 115 of the specification reads in part: “Hereinafter, overlapping descriptions components identical to those shown in FIG. 7 will be omitted.” This is non-grammatical. The examiner assumes this should read “descriptions of components”.
Paragraph 67 states that “The lower stack structure LST may extend to form a common plane with the lower first sidewall S1L, the lower second sidewall S2L, the lower third sidewall S3L, and the lower fourth sidewall S4L.” This does not make sense with the illustrated figures; S1L-S4L are the sides of a rectangle, and are not in a common plane. See the analysis in the 112 rejection below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 5, 11, 13, 27, and 30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites that “the stack structure forms a common plane with each of the first sidewall, the second sidewall, and the third sidewall of the groove.” This tracks the specification, which states that “[t]he lower stack structure LST may extend to form a common plane with the lower first sidewall S1L, the lower second sidewall S2L, the lower third sidewall S3L, and the lower fourth sidewall S4L.” [0067]. This does not make sense with the illustrated figures; S1L-S4L are the sides of a rectangle, and are not in a common plane. It appears to the examiner that the intended meaning of the claim is that the three recited sides (first through third sidewalls) form common respective planes with three sides of the stack structure. The examiner will interpret the claims in this wall for present, but a clarifying amendment is required.
Claim 13 has the same problem.
Claim 5 recites “the conductive gate contact is connected to the second part of the contact-conductive pattern.” “the second part of the contact-conductive pattern” lacks antecedent basis, and there is no context to tell what part of the contact-conductive pattern this might refer to. For present purposes, the examiner will assume that it refers to any part of the contact-conductive pattern.
Claim 27 has the same problem.
Claim 11 recites that “the filling insulating layer is formed of a SiOxNy or a SixOy, wherein x is equal to zero and x is less than y for the SiOxNy”. This is confusing, as it recites that x is equal to zero, but also that x is less than y, which of course it would have to be if x is equal to zero. Also, if x must be zero, then it would not make sense to set forth the composition as SiOxNy; it would simply be SiNy. Also, the specification at [00114] states that “the first filling insulating layer 115 and the second filling insulating layer 139 may be formed of a SiOxNy (x=0 or x<y) or a SixOy (x>y).” The examiner believes that this claim language is likely a translation error, that it should read “x is greater than or equal to zero”, as is set forth in the specification, and will interpret it in this way pending a clarifying amendment.
Claim 30 has the same problem.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 8, 9 12, 13, 19, 21, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Luo, US 2022/0199637 A1, in view of Lee, KR 2017-0042449 A.
Claim 1: Luo discloses
a stack structure including a cell array region (right hand side FIG. 10) and a contact region (left hand side FIG. 10) with a stepped structure, the contact region extending from the cell array region;
a channel structure (652) extending in the cell array region of the stack structure;
a memory layer (“MONOS”, [0108]) between the channel structure and the stack structure;
a groove (120) defined in the contact region of the stack structure, the groove including a first sidewall (front wall, FIG. 1A) defined by the stepped structure of the stack structure, a second sidewall (back wall, FIG. 1A) facing the first sidewall, and a third sidewall (left wall, FIG. 1A) between the first sidewall and the second sidewall:
a filling insulating layer (130) inside the groove;
a barrier insulating layer (126 and/or 128) disposed between the filling insulating layer and the stack structure, the barrier insulating layer being formed of a material different from a material of the filling insulating layer ([0054]-[0056], e.g. silicon nitride vs. silicon oxide), the barrier insulating layer extending along the first sidewall, the second sidewall, and the third sidewall of the groove and a bottom surface of the filling insulating layer;
“For an individual filled trench 120, the first dielectric material 126 may be formed on or over surfaces (e.g., horizontally extending surfaces, vertically extending surfaces) of the stadium structure 114 (e.g., the first stadium structure 114A), the crest regions 122, and the bridge regions 124 (FIG. 1A) of the preliminary block 110 (FIG. 1A) defining boundaries (e.g., horizontal boundaries, vertical boundaries) of the filled trench 120; the second dielectric material 128 may be formed on or over the first dielectric material 126; and the third dielectric material 130 may be formed on or over the second dielectric material 128. As depicted in FIG. 1B, one or more (e.g., each) of the first dielectric material 126, the second dielectric material 128, and the third dielectric material 130 may also be formed to extend beyond boundaries (e.g., horizontal boundaries, vertical boundaries) of the filled trenches 120. For example, first dielectric material 126, the second dielectric material 128, and the third dielectric material 130 may also be formed to extend over uppermost surfaces of the crest regions 122 and/or the bridge regions 124 (FIG. 1A) of individual preliminary blocks 110 (FIG. 1A) of the preliminary stack structure 102 (FIG. 1A) of the microelectronic device structure 100.” [0050].
and at least one conductive gate contact (140) penetrating the filling insulating layer, the barrier insulating layer.
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Luo does not explicitly disclose that the conductive gate contacts penetrate the stepped structure of the stack structure. However, this was common in the art. See Lee FIG. 10K.
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It would have been obvious to have had this in Luo to facilitate connection of the gate contacts.
Claim 2: the stack structure forms a common plane with each of the first sidewall, the second sidewall, and the third sidewall of the groove (FIG. 1A).
Claim 8: the filling insulating layer is formed of a material different from a material of the stack structure. The stack structure is formed in part by the insulating layers 104, which can be made of a number of materials listed at [0034] that are different than the materials of filling insulating layer 130 [0056], e.g. ZrOx.
Claim 9: Luo discloses that “The second dielectric material 128 may be formed of and include at least one dielectric material having different etch selectivity than the third dielectric material 130.” [0054]. It then discloses, as is commonly known in the art, that SiN and SiO have etch selectivity with respect to each other. While the disclosed example, with the filling insulating layer 130 being SiO, [0056], and the barrier insulating layer being SiN, [0054], is one way to have etch selectivity, the opposite is also true. This would have fulfilled the requirement of etch selectivity from [0054], and would have thus been clearly obvious to those in the art. In this case, the filling insulating layer 130 would include a higher content of at least one of nitrogen and silicon as compared with the barrier insulating layer 128.
Claim 10: in the case described with respect to claim 9, the barrier insulating layer includes a higher content of oxygen as compared with the filling insulating layer. Luo discloses that “The second dielectric material 128 may be formed of and include at least one dielectric material having different etch selectivity than the third dielectric material 130.” [0054]. It then discloses, as is commonly known in the art, that SiN and SiO have etch selectivity with respect to each other. While the disclosed example, with the
Claim 11: the filling insulating layer is formed of a SiOxNy (SiN) or a SixOy, wherein x is equal to zero and x is less than y for the SiOxNy (x=0), and wherein x is greater than y for the SixOy.
Claim 12: Luo discloses a first slit (124) penetrating the filling insulating layer while facing the third sidewall.
Claim 13: the first slit includes a sidewall forming a common plane with the filling insulating layer (FIG. 4B).
Claim 19: Luo discloses
a lower stack structure (114D, FIG. 1A) including a plurality of first interlayer insulating layers (104) and a plurality of first conductive patterns (134), which are alternately stacked in a first direction;
a channel structure (652) extending in the lower stack structure;
a memory layer (“MONOS”, [0108]) between the channel structure and the lower stack structure;
a first stepped groove (120, righthand side, FIG. 1A) spaced apart from the channel structure (FIG. 10), the first stepped groove penetrating the lower stack structure;
a first barrier insulating layer (126 and/or 128) covering a surface of the first stepped groove [0050];
a first filling insulating layer (130) disposed inside the first stepped groove, the first filling insulating layer being formed on the first barrier insulating layer [0050];
an upper stack structure (114C) including a plurality of second conductive patterns (134) and a plurality of second interlayer insulating layers (104), which are alternately stacked on the lower stack structure in the first direction, wherein the channel structure and the memory layer extend in the upper stack structure;
As seen in FIG. 10, the channel and memory structures extend to all the stack structures.
a second stepped groove (114C) spaced apart from the channel structure, the second stepped groove penetrating the upper stack structure (FIGS. 1 and 10);
a second barrier insulating layer (126 and/or 128 over 114C) covering a surface of the second stepped groove ([0050]);
a second filling insulating layer (130 over 114C) disposed inside the second stepped groove, the second filling insulating layer being formed on the second barrier insulating layer;
a first conductive gate contact (140 over 114D) penetrating the second filling insulating layer, the second barrier insulating layer, and the lower stack structure; and
a second conductive gate contact (140 over 114C) penetrating the upper stack structure, the first filling insulating layer, and the first barrier insulating layer.
Claim 21: Lou discloses at [0040] that “at least one stadium structures 114 may be modified to include a forward staircase structure 116A but not a reverse staircase structure 116B (e.g., the reverse staircase structure 116B may be absent), or at least one stadium structure 114 may be modified to include a reverse staircase structure 116B but not a forward staircase structure 116A (e.g., the forward staircase structure 116A may be absent).” In such a case, the first stepped groove includes a first sidewall (front wall, FIG. 1A) with a stepped structure, a second sidewall (back wall, FIG. 1A) facing the first sidewall, and a third sidewall (bottom left wall, where staircase 116B would be missing) between the first sidewall and the second sidewall, and wherein the first barrier insulating layer extends along the first sidewall, the second sidewall, and the third sidewall of the first stepped groove ([0050]).
Claim 25: Lou discloses at [0040] that “at least one stadium structures 114 may be modified to include a forward staircase structure 116A but not a reverse staircase structure 116B (e.g., the reverse staircase structure 116B may be absent), or at least one stadium structure 114 may be modified to include a reverse staircase structure 116B but not a forward staircase structure 116A (e.g., the forward staircase structure 116A may be absent).” In such a case, the second stepped groove includes a first sidewall (front wall, FIG. 1A) with a stepped structure, a second sidewall (back wall, FIG. 1A) facing the first sidewall, and a third sidewall (bottom left wall, where staircase 116B would be missing) between the first sidewall and the second sidewall, and wherein the second barrier insulating layer extends along the first sidewall, the second sidewall, and the third sidewall of the second stepped groove ([0050]).
Claim 29: in the case described with respect to claim 9, the barrier insulating layer includes a higher content of oxygen as compared with the filling insulating layer. Luo discloses that “The second dielectric material 128 may be formed of and include at least one dielectric material having different etch selectivity than the third dielectric material 130.” [0054]. It then discloses, as is commonly known in the art, that SiN and SiO have etch selectivity with respect to each other. While the disclosed example, with the
Claim 30: the filling insulating layer is formed of a SiOxNy (SiN) or a SixOy, wherein x is equal to zero and x is less than y for the SiOxNy (x=0), and wherein x is greater than y for the SixOy.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-7 and 21-28 are rejected under 35 U.S.C. 103 as being unpatentable over Luo in view of Lee and Kai, US 2021/0335805 A1.
Claim 3: Luo discloses that the stack structure includes a plurality of interlayer insulating layers (104) and a plurality of conductive patterns (134), which are alternately stacked in a length direction of the channel structure.
Lou does not show that each of the plurality of conductive patterns includes a first part surrounding the channel structure and a second part extending from the first part to form the stepped structure, and that a thickness of the second part is different from a thickness of the first part. See Kai, FIG. 9E, which teaches this feature:
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It would have been obvious to have had such a structure for the conductive pattern as known in the art.
Claim 4: the plurality of conductive patterns include a contact-conductive pattern in contact with the conductive gate contact and a separation-conductive pattern spaced apart from the conductive gate contact.
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Claim 5: as the 5. (Original) The semiconductor memory device of claim 4, wherein the conductive gate contact is connected to the second (top) part of the contact-conductive pattern.
Claim 6: Luo discloses a contact insulating pattern disposed between the separation-conductive pattern and the conductive gate contact.
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Claim 7: the separation-conductive pattern is disposed at at least one level among levels upper and lower than the contact-conductive pattern. See the annotated figure above; the separation-conductive pattern is disposed at an upper level.
Claim 22: each of the plurality of first conductive patterns includes a first part surrounding the channel structure and a second part extending from the first part to form the stepped structure of the first stepped groove, and wherein a thickness of the second part is different from a thickness of the first part:
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Claim 23: the plurality of first conductive patterns include a contact-conductive pattern connected to the second conductive gate contact and a separation-conductive pattern spaced apart from the second conductive gate contact, and wherein the second part of the contact-conductive pattern is in contact with the second conductive gate contact.
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Claim 24: Luo discloses a contact insulating pattern disposed between the separation-conductive pattern and the second conductive gate contact.
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Claim 26: each of the plurality of second conductive patterns includes a first part surrounding the channel structure and a second part extending from the first part to form the stepped structure of the second stepped groove, and wherein a thickness of the second part is different from a thickness of the first part.
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Claim 27: the plurality of second conductive patterns include a contact-conductive pattern connected to the first conductive gate contact and a separation-conductive pattern spaced apart from the first conductive gate contact, and wherein the second part of the contact-conductive pattern is connected to the first conductive gate contact.
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Claim 28: Luo discloses a plurality of contact insulating patterns disposed between the separation-conductive pattern among the plurality of second conductive patterns and the first conductive gate contact and between the plurality of first conductive patterns and the first conductive gate contact.
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Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Luo in view of Lee and Lee ‘696, US 2022/0208696 A1. Luo does not disclose the claimed dummy hole and plug. However, it was well-known in the art to use dummy channels for structural support of the device. See Lee, which discloses
a dummy hole (272) penetrating a portion of the stack structure, which extends along the third sidewall of the groove;
an insulating layer (282) extending along a sidewall of the dummy hole; and
a dummy plug (286) disposed inside the dummy hole.
It would have been obvious to have had such dummy structures to support the device of Luo; see Lee ‘696 [0155].
15. (Original) The semiconductor memory device of claim 14, wherein the stack structure includes a plurality of interlayer insulating layers (Luo 104; Lee ‘696 240) and a plurality of conductive patterns (Luo 134; Lee ‘696 297), which are alternately stacked in a length direction of the channel structure, wherein the plurality of interlayer insulating layers includes an upper insulating layer and a lower insulating layer (above and below WL1), which are adjacent to each other in the length direction of the channel structure, and wherein the insulating layer protrudes to a space between the upper insulating layer and the lower insulating layer (FIG. 24).
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Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Luo in view of Lee and Oh, US 2020/0161326 A1. Luo FIG. 10 discloses an arrangement in which the various stepped grooves 120 (see 614 in FIG. 10) are to the side of the cell region (to the right in FIG. 10). However, there were other common arrangements. See Oh, FIG. 9, which shows the memory region to the left of the connection regions arranged serially to the right. It would have been obvious to have used such an arrangement in Luo as a mere rearrangement of parts in a known configuration. In such a case, the second stepped grooves and the first conductive gate contact are disposed between the channel structure and the first stepped groove.
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Note that the gate contacts are not shown in Oh FIG. 9, but are structures 140 of Luo that are in the stepped regions.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and is listed in the attached Notice of References Cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897