Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/11/2025 has been entered.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Response to Arguments
Applicant's arguments filed 12/11/2025 have been fully considered but they are not persuasive.
Applicant’s remarks assert that the presence of Conductive Routing Wire 130 diverts 95% of the power to the “another transistor 140” to prevent the transitory 120 from being “punctured” by a surge current (¶0088 of Specification). This argument is technically flawed.
Under Kirchhoff’s Current Law [KCL]and the Principle of Superposition, the direction and the magnitude of the current entering a specific branch are independent of the load on a parallel branch sharing the same node. As illustrated in the amended drawing fig. 2, Node 121 serves as a junction where the surge path splits. The direction of the current flow into the branch containing transistor 120 is governed by the potential at node 121 and the internal impedance of transistor 120 itself.
At node 121, the behavior of the electricity is governed by KCL, which states that the sum of currents entering a junction must equal the sum of currents leaving it. Under normal conditions the total current coming from the input pad (Iin) would split three ways. However, as the resistance of the CRW 130 increases to a higher value to direct current away, resistance may be assumed to be infinity for simplicity, its current (I30) drops to effectively to zero. Effectively simplifying KCL equation for the circuit of newly amended figure 2 to:
Iin=I20+I30.
This means the node acts as a simple distribution point where all incoming charge is forced to divide between the two transistors. Since the path to the routing wire is effectively a dead end, the electricity treats the circuit as a parallel network, where ethe total current is simply the sum of the branches that remain open.
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No matter how high the resistance/load is on the Conductive Routing Wire 130 [CRW], it cannot change the direction or choke the surge current already heading down the parallel path toward transistor 120 (Note: Wire 130 is a independent path branching from the node 121.). Consequently, the argument that the wire 130 directs current away from the transistor is a physical impossibility under the disclosed depicted parallel configuration.
As such, a person of ordinary skill would not recognized the circuit as presented to operate as described in the written description and claims, therefore the newly amended figure placing the “another transistor 140” in parallel with the transistor 120 at the node 121 is new matter.
Note: It is however recognized that a POSITA would likely recognized the conclude the Conductive Routing Wire as a series segment located between node 121 and transistor 120, as that is the only topology that would physically allow for the described protection. However, until the drawings are amended to correctly reflect this series topology, the augments regarding the 95% diversion are based on a circuit structure not currently depicted.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1-20 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
The current disclosure provides a schematic (Fig. 2) that contradicts the functional goals of the invention. While the error may be recognizable to a POSITA, the disclosure as filed directs the user to a non-functional parallel configuration. To be enabled, the structural disclosure must accurately reflect the connectivity required to achieve the claimed result. Following the current drawing would require a POSITA to engage in “undue experimentation” to realize the schematic is in error and must be converted to a series configuration.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “wherein the conductive routing wire is configured to provide a serial resistance such that, when a surge current is inputted into the input/output port circuit through the input/output pad, a resistance value of the serial resistance increases with temperature, thereby forcing the surge current to be diverted toward the another transistor,” in combination with “another transistor” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings (specifically Fig. 2) are objected to under 37 CFR 1.83(a) for failing to show the structural relationship necessary for the stated function. The drawing depicts a parallel configuration which is physically incapable of achieving the described current diversion. A person of ordinary skill in the art would recognize this as a clerical error, as the “conductive routing wire” must be in a series-limiting position to provide the described protection. The Applicant is invited to correct the drawing by relocating the reference number 130 to the wire segment between node 121 and the transistor 120, if this is the correct understanding.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Verhaege et al. (US 20020033507 A1).
CLAIM 1. Verhaege et al. discloses an input/output port circuit (Verhaege discloses a multi-finger current ballasting ESD protection circuit, which is an input/output port circuit. See Title, Abstract): comprising:
an input/output pad 520 (Verhaege discloses a circuit terminal to be protected from an ESD event. ¶0004, Claim 43. See Title, Abstract);
a transistor, having a first connection terminal and a second connection terminal (Verhaege discloses a plurality of transistor fingers/FETs, each inherenltly having a drain [first terminal ] and a source [second terminal]; Fig. 7),
wherein the first connection terminal is electrically connected to the input/output pad through a conductive connection wire (Verhaege discloses drain terminals of FET fingers coupled to the pad through conductive input fingers/metal interconnects. (Fig. 7, 9, 13); and
the second connection terminal is electrically connected to another transistor (Verhaege discloses a multi-finger structure where the source terminals of parallel transistor fingers are interconnected, thereby being electrically connected to “another transistor”. Fig. 7, 9, 13, Claim 42); and
a conductive routing wire (Verhaege explicitly teaches that these resistive channels provide a ballast resistance to the drain of each finger. ¶0063-66);, electrically connected to the first connection terminal of the transistor, wherein the conductive routing wire is configured to provide a serial resistance such that, when a surge current is inputted into the input/output port circuit through the input/output pad (Note: It is unclear what “configured to” is intended to mean. The written description, newly filed amended figure 2, and remarks appear to have conflicting descriptions that go against standard laws of circuits (e.g. KCL).), a resistance value of the serial resistance increases with temperature (The resistance of a conductor is a function of temperature. As temperature increases resistance increases, typically attributed to collisions between free electrons and metal ions.), thereby forcing the surge current to be diverted toward the another transistor (Verhaege teaches that the ballast resistance is configured to prevent current from being forced to one finger and instead “forces” or redistributes the surge current to trigger and flow through the other parallel transistor fingers to achieve uniform conduction. ¶0007-13, 20, 63, etc..).
Verhaege is silent upon wherein the resistance of a conducting routing wire is specifically 20 ohms (Note: the resistance is temperature dependent per the claim, and this limitation is not clear is this is the starting resistance or the resistance which enables diversion of the surge.) Specific resistances, are understood in the art to be circuit variables routinely optimized for device performance. As such, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the resistance through routine experimentation and optimization to obtain optimal or desired device performance because the resistance is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
CLAIM 2. Verhaege et al. discloses an /output port circuit according to claim 1, wherein the first connection terminal of the transistor is only electrically connected to the input/output pad and the conductive routing wire (Note: this limitation contradicts the newly provided amended figure 2 argued to depict the circuit. None the less, Applying Applicant’s argued figure 2 submitted 12/11/2025 interpretation, Verhaege Fig. 7, 9, 13, would appear to demonstrate the applicant’s intended scope as best understood.).
CLAIM 3. Verhaege et al. discloses an /output port circuit according to claim 1, wherein in a layout of the input/output port circuit, the conductive connection wire and at least a portion of the conductive routing wire are located in different metal layers (Verhaege et al. fig. 6B).
CLAIM 4. Verhaege et al. discloses an /output port circuit according to claim 1, wherein in a layout of the input/output port circuit, the conductive routing wire comprises a first connection segment, a routing segment, and a second connection segment sequentially connected to each other, the first connection segment and the second connection segment are electrically connected to the first connection terminal of the transistor, respectively, and the first connection segment does not contact the second connection segment (As best understood Verhaege et al. fig. 6B, 7, 9, 13 demonstrate the analogous structural layout as described by the claim in view of the Ramarks and amended figure 2 filed 12/11/2025.).
CLAIM 5. Verhaege et al. discloses an /output port circuit according to claim 4, wherein the conductive routing wire and the conductive connection wire are located in the same metal layer, and the routing segment of the conductive routing wire does not overlap the conductive connection wire (As best understood Verhaege et al. fig. 6B, 7, 9, 13 demonstrate the analogous structural layout as described by the claim in view of the Ramarks and amended figure 2 filed 12/11/2025.).
CLAIM 6. Verhaege et al. discloses an /output port circuit according to claim 4, wherein the routing segment at least partially overlaps a layout of the transistor (As best understood Verhaege et al. fig. 6B, 7, 9, 13 demonstrate the analogous structural layout as described by the claim in view of the Ramarks and amended figure 2 filed 12/11/2025.).
CLAIM 7. Verhaege et al. discloses an /output port circuit according to claim 6, wherein the routing segment at least partially overlaps a layout of a control terminal of the transistor (As best understood Verhaege et al. fig. 6B, 7, 9, 13 demonstrate the analogous structural layout as described by the claim in view of the Ramarks and amended figure 2 filed 12/11/2025.).
CLAIM 8. Verhaege et al. discloses an /output port circuit according to claim 4, wherein the routing segment does not overlap a layout of the second connection terminal of the transistor (As best understood Verhaege et al. fig. 6B, 7, 9, 13 demonstrate the analogous structural layout as described by the claim in view of the Ramarks and amended figure 2 filed 12/11/2025.).
CLAIM 9. Verhaege et al. discloses an /output port circuit according to claim 4, wherein the first connection segment is opposite and parallel to the second connection segment; the routing
segment comprises a first routing portion, a second routing portion, a third routing portion, a fourth routing portion, and a fifth routing portion sequentially connected to each other; the routing segment is connected to the first connection segment through the first routing portion and is connected to the second connection segment through the fifth routing portion; the second routing portion is opposite to the first connection segment, the fourth routing portion is opposite to the second connection segment, and the first routing portion and the fifth routing portion are respectively opposite to the third routing portion (As best understood Verhaege et al. fig. 6B, 7, 9, 13 demonstrate the analogous structural layout as described by the claim in view of the Ramarks and amended figure 2 filed 12/11/2025.).
CLAIM 10. Verhaege et al. discloses an /output port circuit according to claim 9, wherein the third routing portion comprises a first sub-routing, a second sub-routing, a third sub-routing, a fourth sub-routing, and a fifth sub-routing sequentially connected to each other; the third routing portion is connected to the second routing portion through the first sub-routing and is connected to the fourth routing portion through the fifth sub-routing; the first sub-routing is opposite to the first routing portion, the fifth sub-routing is opposite to the fifth routing portion, and the second sub-routing is opposite to the fourth sub-routing (As best understood Verhaege et al. fig. 6B, 7, 9, 13 demonstrate the analogous structural layout as described by the claim in view of the Ramarks and amended figure 2 filed 12/11/2025.).
CLAIM 11. Verhaege et al. discloses an chip, comprising:
an input/output port circuit, comprising:
an input/output pad;
a transistor, having a first connection terminal and a second connection terminal, wherein the first connection terminal is electrically connected to the input/output pad through a conductive connection wire, and the second connection terminal is electrically connected to another transistor; and
a conductive routing wire, electrically connected to the first connection terminal of the transistor, wherein the conductive routing wire is configured to provide a serial resistance such that, when a surge current is inputted into the input/output port circuit through the input/output pad, a resistance value of the serial resistance increases with temperature, thereby forcing the surge current to be diverted toward the another transistor (Verhaege et al. fig. 1 – See regarding claim 1 ).
Verhaege is silent upon wherein the resistance of a conducting routing wire is specifically 20 ohms (Note: the resistance is temperature dependent per the claim, and this limitation is not clear is this is the starting resistance or the resistance which enables diversion of the surge.) Specific resistances, are understood in the art to be circuit variables routinely optimized for device performance. As such, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the resistance through routine experimentation and optimization to obtain optimal or desired device performance because the resistance is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
CLAIM 12. Verhaege et al. discloses an chip according to claim 11, wherein the first connection terminal of the transistor is only electrically connected to the input/output pad and the conductive routing wire (As best understood Verhaege et al. fig. 6B, 7, 9, 13 demonstrate the analogous structural layout as described by the claim in view of the Ramarks and amended figure 2 filed 12/11/2025.).
CLAIM 13. Verhaege et al. discloses an chip according to claim 11, wherein in a layout of the input/output circuit, the conductive connection wire and at least portion of the conductive routing wire are located in different metal layers (As best understood Verhaege et al. fig. 6B, 7, 9, 13 demonstrate the analogous structural layout as described by the claim in view of the Ramarks and amended figure 2 filed 12/11/2025.).
CLAIM 14. Verhaege et al. discloses an chip according to claim 11, wherein in a layout of the input/output circuit, the conductive routing wire comprises a first connection segment, a routing segment, and a second connection segment sequentially connected to each other, the first connection segment and the second connection segment are electrically connected to the first connection terminal of the transistor, respectively, and the first connection segment does not contact the second connection segment (As best understood Verhaege et al. fig. 6B, 7, 9, 13 demonstrate the analogous structural layout as described by the claim in view of the Ramarks and amended figure 2 filed 12/11/2025.).
CLAIM 15. Verhaege et al. discloses an chip according to claim 14, wherein the conductive routing wire and the conductive connection wire are located in the same metal layer, and the routing segment of the conductive routing wire does not overlap the conductive connection wire (As best understood Verhaege et al. fig. 6B, 7, 9, 13 demonstrate the analogous structural layout as described by the claim in view of the Ramarks and amended figure 2 filed 12/11/2025.).
CLAIM 16. Verhaege et al. discloses an chip according to claim 14, wherein the routing segment at least partially overlaps a layout of the transistor (As best understood Verhaege et al. fig. 6B, 7, 9, 13 demonstrate the analogous structural layout as described by the claim in view of the Ramarks and amended figure 2 filed 12/11/2025.).
CLAIM 17. Verhaege et al. discloses an chip according to claim 16, wherein the routing segment at least partially overlaps a layout of a control terminal of the transistor (As best understood Verhaege et al. fig. 6B, 7, 9, 13 demonstrate the analogous structural layout as described by the claim in view of the Ramarks and amended figure 2 filed 12/11/2025.).
CLAIM 18. Verhaege et al. discloses an chip according to claim 14, wherein the routing segment does not overlap a layout of the second connection terminal of the transistor (As best understood Verhaege et al. fig. 6B, 7, 9, 13 demonstrate the analogous structural layout as described by the claim in view of the Ramarks and amended figure 2 filed 12/11/2025.).
CLAIM 19. Verhaege et al. discloses an chip according to claim 14, wherein the first connection segment is opposite and parallel to the second connection segment; the routing segment comprises a first routing portion, a second routing portion, a third routing portion, a fourth routing portion, and a fifth routing portion sequentially connected to each other; the routing segment is connected to the first connection segment through the first routing portion and is connected to the second connection segment through the fifth routing portion; the second routing portion is opposite to the first connection segment, the fourth routing portion is opposite to the second connection segment, and the first routing portion and the fifth routing portion are respectively opposite to the third routing portion (As best understood Verhaege et al. fig. 6B, 7, 9, 13 demonstrate the analogous structural layout as described by the claim in view of the Ramarks and amended figure 2 filed 12/11/2025.).
CLAIM 20. Verhaege et al. discloses an chip according to claim 19, wherein the third routing portion comprises a first sub-routing, a second sub-routing, a third sub-routing, a fourth sub-routing, and a fifth sub-routing sequentially connected to each other; the third routing portion is connected to the second routing portion through the first sub-routing and is connected to the fourth routing portion through the fifth sub-routing; the first sub-routing is opposite to the first routing portion, the fifth sub-routing is opposite to the fifth routing portion, and the second sub-routing is opposite to the fourth sub-routing (As best understood Verhaege et al. fig. 6B, 7, 9, 13 demonstrate the analogous structural layout as described by the claim in view of the Ramarks and amended figure 2 filed 12/11/2025.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
1/20/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898