DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I in the reply filed on 10/20/2025 is acknowledged. The traversal is on the ground(s) that there would be no undue burden to the Examiner to examine all inventions. This is not found persuasive because this proposed process shows at least two different inventions that would require a diverse field of search since their different classification has already been established. It would require undue burdensome search to examine all inventions.
The requirement is still deemed proper and is therefore made FINAL.
Claims 21-28 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 6/8/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 8-10 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kumakura et al., US Patent No. 10,020,373 B1.
Re claim 1. Kumakura et al. disclose an electronic device, comprising: a semiconductor body of silicon carbide 11 and having a first type of electrical conductivity (e.g., n-type, figs. 1-5 and col. 4, lines 30-40); a first insulating layer 15 over a first surface of the semiconductor body, the first insulating layer having a first material with electrical-insulator or dielectric characteristics (e.g., SiO2, figs. 1-5 and col. 4, line 39); a first metal layer 21 extending in part over the first surface of the semiconductor body and in part over the first insulating layer 15 (e.g., figs. 1-5); an interface layer 31 (e.g., fig. 2); 31 or 41 (e.g., fig. 3) of a second material over the first metal layer 21 and over the first insulating layer 15, the second material (e.g., silicon nitride) different from the first material; and a passivation layer 32 (e.g., fig. 2-3) of the first material on the interface layer, see figs. 1-5 and cols. 1-12 for more details.
Re claim 2. The electronic device according to claim 1, wherein the first material is one or more of silicon oxide or TEOS (e.g., SiO2, figs. 1-5 and col. 4, line 39).
Re claim 3. The electronic device according to claim 1, wherein the second material is silicon nitride (e.g., figs. 2-3 and col. 5, lines 35-40.
Re claim 4. The electronic device according to claim 1, further comprising a second insulating layer 32 interposed between the interface layer 41 and the first insulating layer 15 and between the interface layer 41 and the first metal layer 21 (e.g., fig. 3).
Re claim 5. The electronic device according to claim 4, wherein the second insulating layer is of the first material (e.g., col. 5, lines 38-40).
Re claim 6. The electronic device according to claim 1, further comprising an active area (e.g., under the element 21, figs. 1-5) at the first surface of the semiconductor body, the first metal layer 21 at least in part overlapping, and in electrical contact with, the active area (e.g., figs. 1-5).
Re claim 8. The electronic device according to claim 6, further comprising a second metal layer (e.g., cathode) on a second surface, opposite to the first surface, of the semiconductor body, wherein the first metal layer and the second metal layer form respective electrical-conduction terminals of the electronic device (e.g., col. 4, lines 45-49).
Re claim 9. The electronic device according to claim 6, further comprising one or more of a junction barrier diode or a Schottky diode in the active area (e.g., figs. 1-5).
Re claim 10. The electronic device according to claim 1, further comprising, in the semiconductor body, one or more of: a Schottky diode, a PiN diode, a PN diode, an MPS device, a JBS diode, a MOSFET, an IGBT, or a power device (e.g., figs. 1-5).
Re claim 19. Kumakura et al. disclose an electronic device, comprising: a semiconductor body of silicon carbide and having an active area at a first surface of the semiconductor body 11 (e.g., figs. 1-5); a first insulating layer 15 of a first dielectric material over the first surface of the semiconductor body (e.g., fig. 3 and 5); a first metal layer 21 of a metal material extending in part over the active area and in part over the first insulating layer (e.g., fig. 3 and 5); an interface layer 31 (e.g., figs. 3 and 5 and col. 9, lines 62 to col. 10, line 6) of a second dielectric material over the first metal layer and over the first insulating layer; and a passivation layer 32 (fig. 3 and/or 5) of the first dielectric material over the interface layer, the interface layer 31 extending beyond the passivation layer 32 (e.g., vertically, fig. 3) or fig. 5, see figs. 1-5 and cols. 1-12 for more details.
Re claim 20. The device of claim 19, comprising a protection layer 33 (e.g., fig. 3 and/or 5) over the passivation layer and the interface layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kumakura et al., US Patent No. 10,020,373 B1.
Although the exact recitation “an edge- termination region surrounding, at least in part, the active area … and has a second type of electrical conductivity opposite to the first type of electrical conductivity of the semiconductor body, and the first insulating layer extends over the first surface at a distance from the active area and at least partially overlapping the edge-termination region” of the instant claim is not explicitly stated by Kumakura et al. in the related text, it appears that the p-type region/layer within the layer 11 (e.g., col. 4, lines 60-67) could act as the edge-termination region. Therefore, the instant claim appears to be Prima Facie obvious over Kumakura et al. Further in this regard, the process limitation of how the edge- termination region is formed has no patentable weight in claim drawn to structure. Note that a product by process claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al, 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a product by process claim, and not the patentability of the process, and that an old or obvious product by a new method is not patentable as a product, whether claimed in product by process claims or not. Note that applicant has the burden of proof in such cases, as the above caselaw makes clear.
Therefore, the process limitation of the instant claim is thus non-limiting.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm.
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/JACK S CHEN/Primary Examiner, Art Unit 2893
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