DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 1 through 11 allowed, claims 12 and 13 rejected, claims 14 through 18 objected, claims 19 through 20 non-elected.
Present action: claims 6 through 11 objected, claims 1 through 5, 12, 13 and 15 through 18 rejected, and claims 19 through 20 non-elected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12, 13, 15, 16, 17, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation "the stack body" in line 13. There is insufficient antecedent basis for this limitation in the claim. Previously the claim referred to “at least one stack body” in line 11.
Claim 12 recites the limitation "the stack body of the plurality of electrode layers" in line 13. There is insufficient antecedent basis for this limitation in the claim. Previously the claim referred to “a stack of a plurality of electrode layers” in lined 11 and 12.
Claims 13, 15, 16, 17 and 18 are rejected as depending on and incorporating claim 12.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 3, 4, and 5 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Kim (US 2021/0391289).
Regarding claim 1.
Kim teaches:
A semiconductor storage device comprising: a substrate (fig 7: 101; [para 0044]);
a circuit (fig 7:peri; [para 0043]) provided on the substrate (fig 7:; [para 0044]);
a plurality of first electrodes (fig 7:180; [para 0044]) provided above the substrate (fig 7:; [para 0044]) and connected to the circuit (fig 7:peri; [para 0043]) through a plurality of first contacts (fig 7:160; [para 0044]);
a plurality of second electrodes (fig 7:280; [para 0048]) connected to the plurality of first electrodes (fig 7:180; [para 0044]);
a memory cell array (fig 7:cell1,2; [para 0049]) connected to the plurality of second electrodes (fig 7:280; [para 0048]) through a plurality of second contacts (fig 9b:235; [para 0091]), the memory cell array (fig 7:cell1,2; [para 0091]) including a block (fig 10a:I; [para 0100]), the block (fig 10a:I; [para 0100]) including a plurality of units (fig 7,9b:cell1,2; [para 0091]), each of the units (fig 7,9b:cell1,2; [para 0091]) including a plurality of memory cell transistors (fig 5:100b; [para 0081]) and a plurality of first column-shaped parts (fig 7:ch1,2; [para 0050]), and the plurality of first column-shaped parts (fig 7:ch1,2; [para 0050]) penetrating through at least one stack body (fig 7:230,220; [para 0050]) that is a stack of a plurality of electrode layers (fig 7:230; [para 0050]) between which an insulating layer (fig 5:220; [para 0050]) is interposed;
a first source region (fig 7:260; [para 0057]) provided above the memory cell array (fig 7:cell1; [para 0091]) and electrically connected to a portion of the plurality of memory cell transistors (fig 5:100b; [para 0081]);
a second source region (fig 7:260; [para 0057]) provided above the memory cell array (fig 7:cell1; [para 0091]) and electrically connected to another portion (fig 10a) of the plurality of memory cell transistors (fig 7:cell1; [para 0091]);
and a first slit (fig 10a,11I:210; [para 0050]) insulating the first source region (fig 10a,11I:260; [para 0057]) and the second source region (fig 10a,11I:260; [para 0057]) for each of the units.
Regarding claim 2.
Kim teaches the semiconductor storage device according to claim 1,
Kim teaches:
wherein a first voltage can be supplied (fig 3a:SSL2_1; [para 0039]) to the first source region (fig 7:260; [para 0057]), and a second voltage different from the first voltage can be supplied (fig 3a:SSL2_2; [para 0039]) to the second source region (fig 7:260; [para 0057]).
Regarding claim 3.
Kim teaches the semiconductor storage device according to claim 1,
Kim teaches:
a plurality of first selection gates (fig 3a:SST2_2; [para 0036]) provided in the stack body (fig 7:230,220; [para 0050]) of the plurality of electrode layers (fig 7:180; [para 0044]) and used to select the plurality of units (fig 7,9b:cell1,2; [para 0091]) in the block (Fig 10a:I; [para 0100]);
and a second slit (fig 10a,11I:210; [para 0050]) dividing, for each of the units (fig 7,9b:cell1,2; [para 0091]), an upper region of the stack body (fig 7:230,220; [para 0050])including the plurality of first selection gates (fig 3a:SST2_2; [para 0036]).
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Regarding claim 4.
Kim teaches the semiconductor storage device according to claim 1,
Kim teaches:
a third voltage can be supplied (fig 3a:SSL1_1; [para 0039]) to a portion of the plurality of first selection gates (fig 3a:SST1_1; [para 0035]),and a fourth voltage different from the third voltage can be supplied (fig 3a:SSL1_2; [para 0039]) to another portion of the plurality of first selection gates (fig 3a:SST1_2; [para 0035]).
Regarding claim 5.
Kim teaches the semiconductor storage device according to claim 3,
Kim teaches:
an upper end of the second slit (fig 10a,11I:210; [para 0050]) is connected to a lower end of the first slit (fig 10a,11I:210; [para 0050]).
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Claim(s) 12, 13, and 15 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Kim (US 2021/0391289)
Regarding claim 12.
Kim teaches:
A semiconductor storage device comprising: a substrate (fig 4:101; [para 0044]);
a circuit (fig 4:peri; [para 0043]) provided on the substrate (fig 4:10; [para 0044]);
a plurality of first electrodes (fig 4:180; [para 0044]) provided above the substrate (fig 4:101; [para 0044]) and connected to the circuit (fig 4:peri; [para 0043]) through a first contact (fig 4:160; [para 0044]);
a plurality of second electrodes (fig 4:280; [para 0048]) connected to the plurality of first electrodes (fig 4:180; [para 0048]);
a memory cell array (fig 4:cell1,2; [para 0049]) connected to the plurality of second electrodes (fig 4:280; [para 0048]) through a plurality of second contacts (fig 9b:235; [para 0091]), the memory cell array (fig 4,9b:cell1,2; [para 0091]) including a block (fig 10a:I; [para 0100]), the block including a plurality of units (fig 4,9b:cell1,2; [para 0091]), each of the units including a plurality of memory cell transistors (fig 5:100b; [para 0081]) and a plurality of first column-shaped parts (fig 5:ch1,2; [para 0050]), and the plurality of first column-shaped parts (fig 5:ch1,2; [para 0050]) penetrating through at least one stack body (fig 5:230,220; [para 0050]) that is a stack of a plurality of electrode layers (fig 5:230; [para 0050]) between which an insulating layer (fig 5:220; [para 0050]) is interposed;
a first slit (fig 11l:210; [para 0050]) dividing, for each of the units, an upper region (fig 5,10a:cell2; [para 0051]) of the stack body (fig 5:230,220; [para 0050])including a plurality of first selection gates (fig 3a:SST2; [para 0035]) used to select the plurality of units in the block;
a plurality of second selection gates (fig 3a:GST2; [para 0036]) provided in the stack body (fig 5:230,220; [para 0050]) of the plurality of electrode layers (fig 5:230; [para 0050]) and used to select the plurality of units in the block;
and a second slit (fig 11l,11j:210; [para 0050]) dividing, for each of the units, a lower region (fig 5,10a:cell1; [para 0050]) of the stack body (fig 5:230,220; [para 0050]) including the plurality of second selection gates (fig 3a:SST1; [para 0039]), wherein the second slit is formed vertically below the first slit (fig 5).
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Regarding claim 13.
Kim teaches the semiconductor storage device according to claim 12,
Kim teaches:
a first voltage can be supplied (fig 3a:SSL2_1; [para 0039]) to a portion of the plurality of first selection gates (fig 3a:SST2_1; [para 0035]), and a second voltage different from the first voltage can be supplied (fig 3a:SSL2_2; [para 0039]) to another portion of the plurality of first selection gates (fig 3a:SST2_2; [para 0035]).
Regarding claim 15.
Kim teaches the semiconductor storage device according to claim 12,
Kim teaches:
a third voltage can be supplied (fig 3a:SSL1_1; [para 0039]) to a portion of the plurality of second selection gates (fig 3a:SST1_1; [para 0035]), and a fourth voltage different from the third voltage can be supplied (fig 3a:SSL1_2; [para 0039]) to another portion of the plurality of second selection gates (fig 3a:SST1_2; [para 0035]).
Allowable Subject Matter
Claims 6 through 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 16, 17, and 18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 6, the prior art does not teach in combination with other elements of the claim a semiconductor storage device comprising: a second source region provided above the memory cell array and electrically connected to another portion of the plurality of memory cell transistors; and a first slit insulating the first source region and the second source region for each of the units, a plurality of first selection gates provided in the stack body of the plurality of electrode layers and used to select the plurality of units in the block; and a second slit dividing, for each of the units, an upper region of the stack body including the plurality of first selection gates; and a third slit dividing, for each of the units, a lower region of the stack body including the plurality of second selection gates, wherein the third slit is formed vertically below the second slit.
Regarding claim 8, the prior art does not teach in combination with other elements of the claim a semiconductor storage device comprising: a second source region provided above the memory cell array and electrically connected to another portion of the plurality of memory cell transistors; and a first slit insulating the first source region and the second source region for each of the units, a plurality of first selection gates provided in the stack body of the plurality of electrode layers and used to select the plurality of units in the block; and a second slit dividing, for each of the units, wherein a fourth slit is formed in an array direction of the plurality of second column-shaped parts in an upper region of each of the second column-shaped parts and filled with the insulation material.
Regarding claim 15, the prior art does not teach in combination with other elements of the claim
A semiconductor storage device comprising: a first slit dividing, for each of the units, an upper region of the stack body including a plurality of first selection gates used to select the plurality of units in the block; a second slit dividing, for each of the units, a lower region of the stack body including the plurality of second selection gates, wherein the second slit is formed vertically below the first slit,the memory cell array includes a plurality of blocks, the semiconductor storage device further comprises a plurality of second column- shaped parts disposed between one of the blocks and a portion of another of the blocks and filled with an insulation material, and a coupling slit is formed in an array direction of the plurality of second column- shaped parts in an upper region of each of the second column-shaped parts and filled with the insulation material.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim(s) 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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