Prosecution Insights
Last updated: July 17, 2026
Application No. 17/942,339

EXPOSURE APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Sep 12, 2022
Priority
Jan 25, 2022 — JP 2022-009549 +1 more
Examiner
WHITESELL, STEVEN H
Art Unit
1759
Tech Center
1700 — Chemical & Materials Engineering
Assignee
KIOXIA Corporation
OA Round
3 (Non-Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
789 granted / 964 resolved
+16.8% vs TC avg
Moderate +13% lift
Without
With
+12.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
38 currently pending
Career history
1011
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
78.9%
+38.9% vs TC avg
§102
12.3%
-27.7% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 964 resolved cases

Office Action

§103
DETAILED ACTION Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 9, 2026 has been entered. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 9-10 and 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Segawa [US 9,625,831] in view of Hubbard et al. [US 2014/0356981] and Kikuchi [US 2004/0126004]. For claims 1 and 9, Segawa teaches an exposure apparatus (see Figs. 1 and 2) configured to implement an exposure process (see Fig. 3) for exposing a substrate to light (projecting the reticle pattern onto the wafer by illumination of the reticle, see Fig. 2), the exposure apparatus comprising: a stage (140) configured to hold the substrate; a storage device (32) configured to store a correction map (see col. 7 lines 11-16); a measurement device configured to measure a plurality of alignment marks arranged on the substrate; a controller (31) configured to control in the exposure process an exposure position relative to the substrate (exposure processing shot position based on the correction map, step S30, see Fig. 3) by generating a correction map based on measurement results of a plurality of alignment positions arranged on the substrate (alignment measurement data used to generate correction map, see Figs. 3-4) or an amount of warpage of the substrate (surface shape data used to generate correction map, see Figs. 3-4) and moving the stage based on the generated correction map (S30, see Fig. 3). Segawa fails to teach the correction map being obtained by measuring an overlay deviation amount of two substrates, and measuring a plurality of alignment marks arranged on a substrate; calculating an alignment correction coefficient of a magnification component in a surface of the substrate based on measurement results of the plurality of alignment marks, and generating a correction map based on a magnitude of the alignment correction coefficient. Hubbard teaches measuring a plurality of alignment marks arranged on a substrate (measuring grid distortion based on alignment mark positions, see Fig. 2 and [0040]); calculating an alignment correction coefficient of a magnification component in a surface of the substrate based on measurement results of the plurality of alignment marks (calculating expansion/contraction amount of the magnification misalignment, see [0030]-[0037]); generating, based on a magnitude of the alignment correction coefficient, a correction map having an alignment correction value obtained by measuring overlay deviation amounts of two substrates (providing grid feedback to lithographic process based on magnification misalignment amount, see [0019], [0030]-[0050]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide correction maps that are generated based on an overlay deviation between two substrates and the associated magnification misalignment as taught by Hubbard in the correction map to adjust alignment as taught by Segawa in order to ensure accurate alignment between dies during wafer bonding. Segawa fails to explicitly teach that alignment at a plurality of positions includes a plurality of alignment marks on the substrate or selecting of a correction map from a plurality of stored correction maps each having an alignment correction value that differs from others of the correction maps. Kikuchi teaches an exposure apparatus (see Figs. 1 and 2) configured to implement an exposure process for exposing a substrate to light (exposure of the wafer W to illumination light IL patterned by the mark R, see Fig. 2) , the exposure apparatus comprising: a stage (WST) configured to hold the substrate; a storage device (hard disk or RAM, see [0138]) configured to store a plurality of correction maps (correction maps generated and stored, see [0138]) each having an alignment correction value that differs from others of the correction maps (correction information for each different shot area for each wafer, see [0162]-[0165], [0217]-[0221], and [0244]); and a controller (20) configured to control in the exposure process an exposure position relative to the substrate by selecting a correction map from the correction maps (see Fig. 9) and moving the stage based on the selected correction map (position deviation based on the selected correction map, see [0221]) and based on measurement results of a plurality of alignment marks arranged on the substrate (position coordinates calculated based on EGA, 338, see Fig. 9). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed in invention to provide the plurality of alignment marks on the substrate for alignment measurement and selecting of a correction map from a plurality of stored correction maps as taught by Kikuchi in the control process as taught by Segawa because the alignment marks are known in the art for providing easily recognizable registration marks associated with each shot area for optical measurement to ensure alignment of the substrate within the exposure apparatus for accurate positioning and use of selecting a correction map from previously created set of correction maps allows for reducing computation time during exposure processing and maintaining throughput. For claim 12, Segawa teaches a semiconductor manufacturing system (see Figs. 1-3) , comprising: an exposure apparatus configured to implement an exposure process for exposing a substrate to light (see Fig. 2), the exposure apparatus including: a stage (140), a measurement device (alignment scope, see col. 4 lines 23-32), a storage device (32), and a controller (31), the stage being configured to hold the substrate, the measurement device being configured to measure a plurality of alignment positions arranged on the substrate (alignment measurement in exposure unit 10 for performing step S24), the storage device configured to store a correction map (see Fig. 1), and the controller being configured to control, in the exposure process, an exposure position relative to the substrate (exposure processing shot position based on the correction map, step S30, see Fig. 3) by generating a correction map based on measurement results of the plurality of alignment positions arranged on the substrate (alignment measurement data used to generate correction map, see Figs. 3-4) or an amount of warpage of the substrate (surface shape data used to generate correction map, see Figs. 3-4) and moving the stage based on the correction map (S30, see Fig. 3). Segawa fails to teach the correction map being obtained by measuring an overlay deviation amount of two substrates, and measuring a plurality of alignment marks arranged on a substrate; calculating an alignment correction coefficient of a magnification component in a surface of the substrate based on measurement results of the plurality of alignment marks, and generating a correction map based on a magnitude of the alignment correction coefficient. Hubbard teaches measuring a plurality of alignment marks arranged on a substrate (measuring grid distortion based on alignment mark positions, see Fig. 2 and [0040]); calculating an alignment correction coefficient of a magnification component in a surface of the substrate based on measurement results of the plurality of alignment marks (calculating expansion/contraction amount of the magnification misalignment, see [0030]-[0037]); generating, based on a magnitude of the alignment correction coefficient, a correction map having an alignment correction value obtained by measuring overlay deviation amounts of two substrates (providing grid feedback to lithographic process based on magnification misalignment amount, see [0019], [0030]-[0050]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide correction maps that are generated based on an overlay deviation between two substrates and the associated magnification misalignment as taught by Hubbard in the correction map to adjust alignment as taught by Segawa in order to ensure accurate alignment between dies during wafer bonding. Segawa fails to explicitly teach that alignment at a plurality of positions includes a plurality of alignment marks on the substrate or selecting of a correction map from a plurality of stored correction maps each having an alignment correction value that differs from others of the correction maps. Kikuchi teaches an exposure apparatus (see Figs. 1 and 2) configured to implement an exposure process for exposing a substrate to light (exposure of the wafer W to illumination light IL patterned by the mark R, see Fig. 2) , the exposure apparatus comprising: a stage (WST) configured to hold the substrate; a storage device (hard disk or RAM, see [0138]) configured to store a plurality of correction maps (correction maps generated and stored, see [0138]) each having an alignment correction value that differs from others of the correction maps (correction information for each different shot area for each wafer, see [0162]-[0165], [0217]-[0221], and [0244]); and a controller (20) configured to control in the exposure process an exposure position relative to the substrate by selecting a correction map from the correction maps (see Fig. 9) and moving the stage based on the selected correction map (position deviation based on the selected correction map, see [0221]) and based on measurement results of a plurality of alignment marks arranged on the substrate (position coordinates calculated based on EGA, 338, see Fig. 9). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed in invention to provide the plurality of alignment marks on the substrate for alignment measurement and selecting of a correction map from a plurality of stored correction maps as taught by Kikuchi in the control process as taught by Segawa because the alignment marks are known in the art for providing easily recognizable registration marks associated with each shot area for optical measurement to ensure alignment of the substrate within the exposure apparatus for accurate positioning and use of selecting a correction map from previously created set of correction maps allows for reducing computation time during exposure processing and maintaining throughput. For claims 2 and 10, Segawa teaches the exposure process includes exposure of a plurality of shots with respect to the substrate, and the correction map includes an alignment correction value for each shot (correction values (CPE) for every shot by using fine wafer alignment residual data, and generates a correction map that is correction information, see col. 6 lines 1-23). For claims 13 and 14, in the combination, Segawa teaches a wafer shape distortion (see col. 1 lines 20-30) and Hubbard teaches the overlay deviation amount of the two substrates (see [0019], [0030]-[0050]). Accordingly, an overlay deviation of a random component indicates an overlay deviation component that is randomly generated in the surface of the substrate is and inherent feature to the overlay determination because the wafer has a distorted shape (“the overlay deviation of the random component depending on the amount of warpage of an upper wafer” see page 83 of the instant specification). For claim 15, in the combination, Segawa teaches different shot positions on the substrate (shots on a wafer, see col. 2 lines 41-43), and Hubbard teaches the magnification component in the surface of the substrate is a magnification component between the two substrates obtained by measuring the plurality of alignment marks (measuring grid distortion based on alignment mark positions, see Fig. 2 and [0040] and calculating expansion/contraction amount of the magnification misalignment, see [0030]-[0037]). For claim 16, in the combination, Segawa teaches generating a correction map based on the amount of warpage of the substrate (surface shape data used to generate correction map, see Figs. 3-4) and Kikuchi teaches the controller selects the correction map from the correction maps (see Fig. 9). Response to Arguments Applicant’s arguments with respect to claims 1, 9, and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Hubbard is relied upon to teach the salient features of the claimed. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Asano et al. [US 2021/0199596] teaches wafer bonding correction by lithography magnification adjustment (see [0204]). Any inquiry concerning this communication or earlier communications from the examiner should be directed to Steven H Whitesell whose telephone number is (571)270-3942. The examiner can normally be reached Mon - Fri 9:00 AM - 5:30 PM (MST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Curt Mayes can be reached at 571-272-1234. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Steven H Whitesell/Primary Examiner, Art Unit 1759
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Prosecution Timeline

Show 1 earlier event
Jun 20, 2025
Non-Final Rejection mailed — §103
Sep 22, 2025
Response Filed
Nov 04, 2025
Examiner Interview Summary
Nov 04, 2025
Applicant Interview (Telephonic)
Dec 09, 2025
Final Rejection mailed — §103
Mar 09, 2026
Request for Continued Examination
Mar 11, 2026
Response after Non-Final Action
May 19, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
95%
With Interview (+12.9%)
2y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 964 resolved cases by this examiner. Grant probability derived from career allowance rate.

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