DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on November 26, 2025 has been entered. Claim(s) 5 and 10 has/have been canceled and claim(s) 12 and 13 has/have been added. Therefore, claim(s) 1-4, 6-9 and 11-13 remain(s) pending in the application with claims 3-4, 8-9 and 11 withdrawn from consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 6-7 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 2002/0056894, hereinafter “Kuo”, previously cited, under a different interpretation from that previously used), in view of Miyaki et al. (US 2002/0146864, hereinafter “Miyaki”, previously cited) and Aoki (US 5,834,691, hereinafter “Aoki”, previously cited).
Regarding claim 1, Kuo teaches in Figs. 4 and 5 (annotated Figs. 4 and 5 shown below) and related text a lead frame (5, annotated Fig. 4, 8, annotated Fig. 5 and ¶¶[0014] and [0017]) comprising:
a die pad (517, annotated Fig. 4, 81, annotated Fig. 5 and ¶¶[0014] and [0017]) that includes a mounting surface (e.g. 517 and an area that includes through holes 511-516, annotated Fig. 4, 815 and an area that includes through holes 811-814, annotated Fig. 5 and ¶¶[0014] and [0017]) for mounting a semiconductor chip (i.e. die 7, annotated Fig. 4 and ¶[0015]); and
a film member (6, annotated Fig. 4 and ¶[0015]) that is bonded to the mounting surface of the die pad so as to fit within a range of the mounting surface, wherein
the mounting surface of the die pad includes a through hole (511-516, annotated Fig. 4, 811-814, annotated Fig. 5 and ¶¶[0014] and [0017]) that is formed in an area that includes an outer periphery of the film member (annotated Figs. 4 and 5).
[AltContent: ][AltContent: ][AltContent: textbox (area that includes an outer periphery of the film member)][AltContent: rect][AltContent: textbox (mounting surface of die pad/
range of the mounting surface)][AltContent: textbox (mounting area for mounting semiconductor chip directly under the area of the semiconductor chip on the film member)][AltContent: ][AltContent: rect][AltContent: textbox ((Annotated Figure))]
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[AltContent: ][AltContent: textbox (area that includes an outer periphery of the film member)][AltContent: textbox ((Annotated Figure))][AltContent: textbox (mounting surface of die pad/
range of the mounting surface)][AltContent: ][AltContent: rect][AltContent: rect]
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Kuo, however, does not explicitly teach that the film member is formed by an insulating resin tape.
Miyaki, in a similar field of endeavor, teaches in Figs. 10 through 12 and related text, that a semiconductor die (2, Fig. 12) can be attached to a die pad using not only sliver paste (8, Figs. 10 and 12 and ¶[0223]), as disclosed by Kuo, but also an adhesive tape (5 or 7, Fig. 12, ¶¶[0223] and [0225]) in addition to the silver paste (8, Fig. 12) or only an adhesive tape (5, Fig. 11), which is known in the art to include an insulating resin, such as epoxy, as evidenced by Aoki (Aoki, col. 9, ll. 38-52) in order to reinforce the join strength of the semiconductor chip (Miyaki, ¶[0223]).
Thus, since the prior art teaches all of the claimed elements, using such elements would lead to predictable results, and as such it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the insulating resin instead of or in addition to the solder paste disclosed by Kuo as doing so would amount to nothing more as using known material for its intended purpose that would result in a predictable result of reinforcing the join strength of the semiconductor chip.
Regarding claim 2 (1), the combined teaching of Kuo, Miyaki and Aoki discloses wherein the through hole (e.g. 811-814, annotated Fig. 5 and ¶[0017]) is formed in an area that includes a vertex of the film member (annotated Fig. 5).
Regarding claim 12 (1), the combined teaching of Kuo, Miyaki and Aoki discloses wherein
a mounting area for mounting the semiconductor chip (7, annotated Fig. 4), having a size that fits within the area of the film member when viewed from above, is provided on the film member (annotated Fig. 5).
Regarding claim 6, Kuo teaches in Figs. 4 and 5 (annotated Figs. 4 and 5 shown above) and related text, a semiconductor device comprising:
a lead frame (5, annotated Fig. 4, 8, annotated Fig. 5 and ¶¶[0014] and [0017]);
a semiconductor chip (i.e. die 7, annotated Fig. 4 and ¶[0015]) that is mounted on the lead frame (annotated Fig. 4); and
wherein the lead frame includes
a die pad (51, annotated Fig. 4, 81, annotated Fig. 5 and ¶¶[0014] and [0017]) that includes a mounting surface (e.g. 517 and an area that includes through holes 511-516, annotated Fig. 4, 815 and an area that includes through holes 811-814, annotated Fig. 5 and ¶¶[0014] and [0017]) for mounting the semiconductor chip (i.e. die 7, annotated Fig. 4 and ¶[0015]); and
a film member (6, annotated Fig. 4 and ¶[0015]) that is bonded to the mounting surface of the die pad and that bonds the semiconductor chip to the die pad (annotated Fig. 4), so as to fit within a range of the mounting surface (annotated Figs. 4 and 5), and
the die pad includes a through hole (511-516, Fig. 4, 811-814, Fig. 5 and ¶¶[0014] and [0017]) that is formed in an area including an outer periphery of the film member (Figs. 4 and 5).
Kuo, however, does not explicitly teach that the film member is formed by an insulating resin tape and that an encapsulating resin encapsulates the semiconductor chip.
Miyaki, in a similar field of endeavor, teaches in Figs. 10-12 and 15 and related text, that an encapsulating (molding) resin (10, Fig. 15 and ¶[0220]) can be formed around a semiconductor chip attached to a lead frame, similar to that disclosed by Kuo, in order to seal and protect the semiconductor chip of the final semiconductor package (¶[0018]). Moreover, Miyaki, also teaches that a semiconductor die (2, Fig. 12) can be attached to a die pad using not only sliver paste (8, Figs. 10 and 12 and ¶[0223]), as disclosed by Kuo, but also an adhesive tape (5 or 7, Fig. 12, ¶¶[0223] and [0225]) in addition to the silver paste (8, Fig. 12) or only an adhesive tape (5, Fig. 11), which is known in the art to include an insulating resin, such as epoxy, as evidenced by Aoki (Aoki, col. 9, ll. 38-52) in order to reinforce the join strength of the semiconductor chip (Miyaki, ¶[0223]).
Thus, since the prior art teaches all of the claimed elements, using such elements would lead to predictable results, and as such it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the encapsulating resin disclosed by Miyaki so as to encapsulate the semiconductor chip disclosed by Kuo, in order to seal and protect the semiconductor chip of the final semiconductor package and to use the insulating resin instead of or in addition to the solder paste disclosed by Kuo as doing so would amount to nothing more as using known material for its intended purpose that would result in a predictable result of reinforcing the join strength of the semiconductor chip.
Regarding claim 7 (6), the combined teaching of Kuo, Miyaki and Aoki discloses
wherein the through hole (e.g. 811-814, annotated Fig. 5 and ¶[0017]) is formed in an area that includes a vertex of the film member (Kuo, annotated Fig. 5).
Regarding claim 13 (6), the combined teaching of Kuo, Miyaki and Aoki discloses wherein
a mounting area for mounting the semiconductor chip (7, annotated Fig. 4), having a size that fits within the area of the film member when viewed from above, is provided on the film member (annotated Fig. 5).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 6 have been considered but are moot because the new ground of rejections, under a different interpretation of the Kuo reference, in combination with Miyaki and Aoki, does not rely on any reference applied in the prior rejection of record for the teaching or matter specifically challenged in the argument. Specifically, as discussed above in the rejection of claims 1 and 6, Kuo in combination with Miyaki and Aoki discloses all of the elements of the amened claims. Namly, Kuo, Miyaki and Aoki disclose the mounting surface of a die pad, with an insulating resin tape bonded to it so as to fit within its range, where the mounting surface includes a through hole formed in an area that includes an outer periphery of the insulating resin tape. Accordingly, the cited prior art is considered as teaching all of the elements of the claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.B.C/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893